timing: Improve robustness to dangling/undriven logic

Signed-off-by: David Shah <dave@ds0.me>

1 files changed, 10 insertions, 0 deletions

diff --git a/common/timing.cc b/common/timing.cc
index 4e84fffe..ae9a95fe 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -177,10 +177,20 @@ struct Timing
                     // the current output port, increment fanin counter
                     for (auto i : input_ports) {
                         DelayInfo comb_delay;
+                        if (cell.second->ports[i].net->driver.cell == nullptr)
+                            continue;
                         bool is_path = ctx->getCellDelay(cell.second.get(), i, o->name, comb_delay);
                         if (is_path)
                             port_fanin[o]++;
                     }
+                    // If there is no fanin, add the port as a false startpoint
+                    if (!port_fanin.count(o) && !net_data.count(o->net)) {
+                        topographical_order.emplace_back(o->net);
+                        TimingData td;
+                        td.false_startpoint = true;
+                        td.max_arrival = 0;
+                        net_data[o->net][ClockEvent{async_clock, RISING_EDGE}] = td;
+                    }
                 }
             }
         }