Add ice40 ICESTORM_LC bels

Signed-off-by: Clifford Wolf <clifford@clifford.at>

3 files changed, 157 insertions, 12 deletions

diff --git a/ice40/chip.cc b/ice40/chip.cc
index b59e2e80..10c493d1 100644
--- a/ice40/chip.cc
+++ b/ice40/chip.cc
@@ -23,13 +23,13 @@
 
 IdString belTypeToId(BelType type)
 {
-	if (type == TYPE_A) return "A";
+	if (type == TYPE_ICESTORM_LC) return "ICESTORM_LC";
 	return IdString();
 }
 
 BelType belTypeFromId(IdString id)
 {
-	if (id == "A") return TYPE_A;
+	if (id == "ICESTORM_LC") return TYPE_ICESTORM_LC;
 	return TYPE_NIL;
 }
 
@@ -37,15 +37,33 @@ BelType belTypeFromId(IdString id)
 
 IdString PortPinToId(PortPin type)
 {
-	if (type == PIN_FOO) return "FOO";
-	if (type == PIN_BAR) return "BAR";
+	if (type == PIN_IN_0) return "IN_0";
+	if (type == PIN_IN_1) return "IN_1";
+	if (type == PIN_IN_2) return "IN_2";
+	if (type == PIN_IN_3) return "IN_3";
+	if (type == PIN_O   ) return "O";
+	if (type == PIN_LO  ) return "LO";
+	if (type == PIN_CIN ) return "CIN";
+	if (type == PIN_COUT) return "COUT";
+	if (type == PIN_CEN ) return "CEN";
+	if (type == PIN_CLK ) return "CLK";
+	if (type == PIN_SR  ) return "SR";
 	return IdString();
 }
 
 PortPin PortPinFromId(IdString id)
 {
-	if (id == "FOO") return PIN_FOO;
-	if (id == "BAR") return PIN_BAR;
+	if (id == "IN_0") return PIN_IN_0;
+	if (id == "IN_1") return PIN_IN_1;
+	if (id == "IN_2") return PIN_IN_2;
+	if (id == "IN_3") return PIN_IN_3;
+	if (id == "O"   ) return PIN_O;
+	if (id == "LO"  ) return PIN_LO;
+	if (id == "CIN" ) return PIN_CIN;
+	if (id == "COUT") return PIN_COUT;
+	if (id == "CEN" ) return PIN_CEN;
+	if (id == "CLK" ) return PIN_CLK;
+	if (id == "SR"  ) return PIN_SR;
 	return PIN_NIL;
 }
 
diff --git a/ice40/chip.h b/ice40/chip.h
index 99fd5e25..a5fc7021 100644
--- a/ice40/chip.h
+++ b/ice40/chip.h
@@ -35,7 +35,7 @@ struct DelayInfo
 enum BelType
 {
 	TYPE_NIL,
-	TYPE_A
+	TYPE_ICESTORM_LC
 };
 
 IdString belTypeToId(BelType type);
@@ -44,8 +44,17 @@ BelType belTypeFromId(IdString id);
 enum PortPin
 {
 	PIN_NIL,
-	PIN_FOO = 1,
-	PIN_BAR = 2
+	PIN_IN_0,
+	PIN_IN_1,
+	PIN_IN_2,
+	PIN_IN_3,
+	PIN_O,
+	PIN_LO,
+	PIN_CIN,
+	PIN_COUT,
+	PIN_CEN,
+	PIN_CLK,
+	PIN_SR
 };
 
 IdString PortPinToId(PortPin type);
@@ -83,6 +92,16 @@ struct WireInfoPOD
 	BelPortPOD *bels_downhill;
 };
 
+extern int num_bels_384;
+extern int num_bels_1k;
+extern int num_bels_5k;
+extern int num_bels_8k;
+
+extern BelInfoPOD bel_data_384[];
+extern BelInfoPOD bel_data_1k[];
+extern BelInfoPOD bel_data_5k[];
+extern BelInfoPOD bel_data_8k[];
+
 extern int num_wires_384;
 extern int num_wires_1k;
 extern int num_wires_5k;
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 9e783dd0..d0711a6a 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -7,10 +7,24 @@ dev_width = None
 dev_height = None
 num_wires = None
 
+tiles = dict()
+
 wire_uphill = dict()
 wire_downhill = dict()
 wire_bidir = dict()
 
+bel_name = list()
+bel_type = list()
+
+wire_uphill_belport = dict()
+wire_downhill_belports = dict()
+
+wire_names = dict()
+wire_names_r = dict()
+
+def cmp_wire_names(newname, oldname):
+    return newname < oldname
+
 with open(sys.argv[1], "r") as f:
     mode = None
 
@@ -39,11 +53,35 @@ with open(sys.argv[1], "r") as f:
             mode = ("routing", int(line[3]))
             continue
 
+        if line[0] == ".io_tile":
+            tiles[(int(line[1]), int(line[2]))] = "io"
+            mode = None
+            continue
+
+        if line[0] == ".logic_tile":
+            tiles[(int(line[1]), int(line[2]))] = "logic"
+            mode = None
+            continue
+
+        if line[0] == ".ramb_tile":
+            tiles[(int(line[1]), int(line[2]))] = "ramb"
+            mode = None
+            continue
+
+        if line[0] == ".ramt_tile":
+            tiles[(int(line[1]), int(line[2]))] = "ramt"
+            mode = None
+            continue
+
         if (line[0][0] == ".") or (mode is None):
             mode = None
             continue
 
         if mode[0] == "net":
+            wname = (int(line[0]), int(line[1]), line[2])
+            wire_names[wname] = mode[1]
+            if (mode[1] not in wire_names_r) or cmp_wire_names(wname, wire_names_r[mode[1]]):
+                wire_names_r[mode[1]] = wname
             continue
 
         if mode[0] == "buffer":
@@ -68,16 +106,72 @@ with open(sys.argv[1], "r") as f:
             wire_bidir[wire_b].add(wire_b)
             continue
 
+def add_bel_input(bel, wire, port):
+    if wire not in wire_downhill_belports:
+        wire_downhill_belports[wire] = set()
+    wire_downhill_belports[wire].add((bel, port))
+
+def add_bel_output(bel, wire, port):
+    assert wire not in wire_uphill_belport
+    wire_uphill_belport[wire] = (bel, port)
+
+def add_bel_lc(x, y, z):
+    bel = len(bel_name)
+    bel_name.append("%d_%d_lc%d" % (x, y, z))
+    bel_type.append("ICESTORM_LC")
+
+    wire_cen = wire_names[(x, y, "lutff_global/cen")]
+    wire_clk = wire_names[(x, y, "lutff_global/clk")]
+    wire_s_r = wire_names[(x, y, "lutff_global/s_r")]
+
+    if z == 0:
+        wire_cin = wire_names[(x, y, "carry_in_mux")]
+    else:
+        wire_cin = wire_names[(x, y, "lutff_%d/cout" % (z-1))]
+
+    wire_in_0 = wire_names[(x, y, "lutff_%d/in_0" % z)]
+    wire_in_1 = wire_names[(x, y, "lutff_%d/in_1" % z)]
+    wire_in_2 = wire_names[(x, y, "lutff_%d/in_2" % z)]
+    wire_in_3 = wire_names[(x, y, "lutff_%d/in_3" % z)]
+    wire_out  = wire_names[(x, y, "lutff_%d/out"  % z)]
+    wire_cout = wire_names[(x, y, "lutff_%d/cout" % z)]
+    wire_lout = wire_names[(x, y, "lutff_%d/lout" % z)] if z < 7 else None
+
+    add_bel_input(bel, wire_cen, "CEN")
+    add_bel_input(bel, wire_clk, "CLK")
+    add_bel_input(bel, wire_s_r, "SR")
+    add_bel_input(bel, wire_cin, "CIN")
+
+    add_bel_input(bel, wire_in_0, "IN_0")
+    add_bel_input(bel, wire_in_1, "IN_1")
+    add_bel_input(bel, wire_in_2, "IN_2")
+    add_bel_input(bel, wire_in_3, "IN_3")
+
+    add_bel_output(bel, wire_out,  "O")
+    add_bel_output(bel, wire_cout, "COUT")
+
+    if wire_lout is not None:
+        add_bel_output(bel, wire_lout, "LO")
+
+for tile_xy, tile_type in sorted(tiles.items()):
+    if tile_type == "logic":
+        for i in range(8):
+            add_bel_lc(tile_xy[0], tile_xy[1], i)
+
 print('#include "chip.h"')
 
+print("int num_bels_%s = %d;" % (dev_name, num_wires))
+print("BelInfoPOD bel_data_%s[%d] = {" % (dev_name, num_wires))
+for bel in range(len(bel_name)):
+    print("  {\"%s\", TYPE_%s}%s" % (bel_name[bel], bel_type[bel], "," if bel+1 < len(bel_name) else ""))
+print("};")
+
 wireinfo = list()
 
 for wire in range(num_wires):
     num_uphill = 0
     num_downhill = 0
     num_bidir = 0
-
-    has_bel_uphill = False
     num_bels_downhill = 0
 
     if wire in wire_uphill:
@@ -98,12 +192,26 @@ for wire in range(num_wires):
         print(",\n".join(["  {%d, 1.0}" % other_wire for other_wire in wire_bidir[wire]]))
         print("};")
 
+    if wire in wire_downhill_belports:
+        num_bels_downhill = len(wire_downhill_belports[wire])
+        print("static BelPortPOD wire%d_downbels[] = {" % wire)
+        print(",\n".join(["  {%d, PIN_%s}" % it for it in wire_downhill_belports[wire]]))
+        print("};")
+
     info = "  {"
-    info += "\"wire%d\", " % wire
+    info += "\"%d_%d_%s\", " % wire_names_r[wire]
     info += "%d, %d, %d, " % (num_uphill, num_downhill, num_bidir)
     info += ("wire%d_uphill, " % wire) if num_uphill > 0 else "nullptr, "
     info += ("wire%d_downhill, " % wire) if num_downhill > 0 else "nullptr, "
     info += ("wire%d_bidir, " % wire) if num_bidir > 0 else "nullptr, "
+    info += "%d, " % (num_bels_downhill)
+
+    if wire in wire_uphill_belport:
+        info += "{%d, PIN_%s}, " % wire_uphill_belport[wire]
+    else:
+        info += "{-1, PIN_NIL}, "
+
+    info += ("wire%d_downbels" % wire) if num_bels_downhill > 0 else "nullptr"
     info += "}"
 
     wireinfo.append(info)