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| author | Maciej Dudek <mdudek@antmicro.com> | 2022-03-09 14:13:29 +0100 |
|---|---|---|
| committer | Maciej Dudek <mdudek@antmicro.com> | 2022-03-09 14:13:29 +0100 |
| commit | 191be632e23b26fa9eae484b04dde0ad5af35e39 (patch) | |
| tree | 397f9a7051e353eb7b0fd6d9c4fcf28794bd6160 /3rdparty/pybind11/docs/Doxyfile | |
| parent | 81e970867d655735920e4133ad130fe2a05172e7 (diff) | |
| download | nextpnr-191be632e23b26fa9eae484b04dde0ad5af35e39.tar.gz nextpnr-191be632e23b26fa9eae484b04dde0ad5af35e39.tar.bz2 nextpnr-191be632e23b26fa9eae484b04dde0ad5af35e39.zip | |
nexus: DCCs cannot be cascaded
This commit solves implicit cascading when clock signal drives DCC and logic
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
Diffstat (limited to '3rdparty/pybind11/docs/Doxyfile')
0 files changed, 0 insertions, 0 deletions