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* Add icebreaker example projectClifford Wolf2018-02-064-0/+153
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* Merge pull request #119 from daveshah1/up5k_improveClifford Wolf2018-01-3012-3503/+18362
|\ | | | | UltraPlus Timing Analysis Improvements
| * Tidy upDavid Shah2018-01-303-1154/+0
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| * Misc UltraPlus fixesDavid Shah2018-01-301-29/+35
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| * Updated 5k timing data, icetime regression fixDavid Shah2018-01-296-12479/+13778
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| * DSP related fixesDavid Shah2018-01-282-269/+2
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| * Working DSP timing analysisDavid Shah2018-01-262-3/+33
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| * Work on timing analysis of DSPsDavid Shah2018-01-261-8/+196
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| * Parse extra cells in icetimeDavid Shah2018-01-231-1/+50
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| * More DSP timing fuzzing, start adding new tiles to icetimeDavid Shah2018-01-223-2/+3710
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| * Seperate different DSP configs in timing dataDavid Shah2018-01-2211-2532/+13532
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* | Merge pull request #118 from daveshah1/up5k_fix_timingClifford Wolf2018-01-202-143/+88
|\| | | | | Fix 5k Timing Data
| * Fix 5k timing dataDavid Shah2018-01-202-143/+88
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* Merge pull request #116 from daveshah1/up5k_misc_fixesClifford Wolf2018-01-1614-10109/+270
|\ | | | | Miscellaneous UltraPlus fixes and improvements
| * Add example for 5k UWG30 packageDavid Shah2018-01-162-0/+39
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| * I³C IO reverse engineered and documentedDavid Shah2018-01-163-0/+56
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| * Add 5k UWG30 ieren data to dbDavid Shah2018-01-161-1/+5
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| * Remove seperate 5k RAM DB and share with 8k insteadDavid Shah2018-01-167-10016/+13
| | | | | | | | | | This should ensure that the 5k RAM routing entries are now complete, fixing #115
| * Add pinout for 5k UWG30 packageDavid Shah2018-01-161-0/+23
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| * Add SPI enable bits to docsDavid Shah2018-01-161-0/+4
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| * HFOSC trimming infoDavid Shah2018-01-162-1/+20
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| * New UltraPlus corner tracing algorithmDavid Shah2018-01-161-87/+86
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| * Misc routing tweaksDavid Shah2018-01-161-3/+7
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| * Figure out missing SPI config bits, and add to chipdbDavid Shah2018-01-163-2/+18
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* | Add "iceprog -e"Clifford Wolf2018-01-021-20/+42
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* | Merge pull request #113 from cr1901/nosleepClifford Wolf2017-12-311-20/+65
|\ \ | | | | | | Add option to `icepack` to disable SPI Deep Power-Down command in bitstream.
| * | Enable writing nosleep config bit into output bitstream.William D. Jones2017-12-311-11/+30
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| * | Add nosleep field to FpgaConfig- read_bits recognizes the option.William D. Jones2017-12-311-9/+35
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* | Merge pull request #112 from mithro/patch-2Clifford Wolf2017-12-091-0/+13
|\ \ | | | | | | Creating COPYING file.
| * | Creating COPYING file.Tim Ansell2017-12-081-0/+13
|/ / | | | | So GitHub automatically detects the license of the repo.
* | Merge pull request #110 from daveshah1/up5k_ipClifford Wolf2017-11-2820-14/+5004
|\| | | | | UltraPlus Hard IP and icetime Support
| * Whitespace fixesDavid Shah2017-11-283-9/+36
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| * Add uncommitted changes and tidy up some filesDavid Shah2017-11-283-2/+253
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| * Chipdb fix for hard IPDavid Shah2017-11-261-4/+4
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| * Add note about glitch filterDavid Shah2017-11-251-2/+12
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| * Add UltraPlus IP to chipdbDavid Shah2017-11-242-3/+212
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| * Initial 5k support in icetime (no support for new cells yet)David Shah2017-11-243-7/+28
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| * Preparations for 5k icetimeDavid Shah2017-11-243-2/+3627
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| * Documented I2C/SPI/LEDDA_IPDavid Shah2017-11-242-2/+196
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| * All 5k IP tracedDavid Shah2017-11-244-3/+129
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| * Work on UltraPlus IP tracingDavid Shah2017-11-243-0/+366
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| * Begin I2C/SPI IP reverse engineeringDavid Shah2017-11-235-0/+161
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* | Merge pull request #109 from daveshah1/up5kClifford Wolf2017-11-2144-121/+24909
|\| | | | | Support for new UltraPlus features
| * Tidy up 5k examplesDavid Shah2017-11-206-35/+18
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| * Fix whitespace and a couple of typosDavid Shah2017-11-2011-14/+14
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| * Add UltraPlus info to docsDavid Shah2017-11-191-0/+7
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| * Merge branch 'master' into up5kDavid Shah2017-11-191-0/+1
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* | Add BeagleWire linkClifford Wolf2017-11-191-0/+1
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| * Merge branch 'master' into up5kDavid Shah2017-11-188-13/+44
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* | Merge commit '05440e4'Clifford Wolf2017-11-187-12/+43
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