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-rw-r--r--icepll/icepll.cc140
1 files changed, 124 insertions, 16 deletions
diff --git a/icepll/icepll.cc b/icepll/icepll.cc
index fa06d0a..273c6a1 100644
--- a/icepll/icepll.cc
+++ b/icepll/icepll.cc
@@ -46,6 +46,15 @@ void help(const char *cmd)
printf(" -S\n");
printf(" Disable SIMPLE feedback path mode\n");
printf("\n");
+ printf(" -f <filename>\n");
+ printf(" Save PLL configuration as Verilog to file\n");
+ printf("\n");
+ printf(" -m\n");
+ printf(" Save PLL configuration as Verilog module (use with -f)\n");
+ printf("\n");
+ printf(" -q\n");
+ printf(" Do not print PLL configuration to stdout\n");
+ printf("\n");
exit(1);
}
@@ -54,9 +63,12 @@ int main(int argc, char **argv)
double f_pllin = 12;
double f_pllout = 60;
bool simple_feedback = true;
+ char* filename = NULL;
+ bool save_as_module = false;
+ bool quiet = false;
int opt;
- while ((opt = getopt(argc, argv, "i:o:S")) != -1)
+ while ((opt = getopt(argc, argv, "i:o:Smf:q")) != -1)
{
switch (opt)
{
@@ -69,6 +81,15 @@ int main(int argc, char **argv)
case 'S':
simple_feedback = false;
break;
+ case 'm':
+ save_as_module = true;
+ break;
+ case 'f':
+ filename = optarg;
+ break;
+ case 'q':
+ quiet = true;
+ break;
default:
help(argv[0]);
}
@@ -77,6 +98,10 @@ int main(int argc, char **argv)
if (optind != argc)
help(argv[0]);
+ // error: shall save as module, but no filename was given
+ if (save_as_module && filename == NULL)
+ help(argv[0]);
+
bool found_something = false;
double best_fout = 0;
int best_divr = 0;
@@ -157,29 +182,112 @@ int main(int argc, char **argv)
exit(1);
}
- printf("\n");
+ if (!quiet)
+ {
+ printf("\n");
- printf("F_PLLIN: %8.3f MHz (given)\n", f_pllin);
- printf("F_PLLOUT: %8.3f MHz (requested)\n", f_pllout);
- printf("F_PLLOUT: %8.3f MHz (achieved)\n", best_fout);
+ printf("F_PLLIN: %8.3f MHz (given)\n", f_pllin);
+ printf("F_PLLOUT: %8.3f MHz (requested)\n", f_pllout);
+ printf("F_PLLOUT: %8.3f MHz (achieved)\n", best_fout);
- printf("\n");
+ printf("\n");
- printf("FEEDBACK: %s\n", simple_feedback ? "SIMPLE" : "NON_SIMPLE");
- printf("F_PFD: %8.3f MHz\n", f_pfd);
- printf("F_VCO: %8.3f MHz\n", f_vco);
+ printf("FEEDBACK: %s\n", simple_feedback ? "SIMPLE" : "NON_SIMPLE");
+ printf("F_PFD: %8.3f MHz\n", f_pfd);
+ printf("F_VCO: %8.3f MHz\n", f_vco);
- printf("\n");
+ printf("\n");
- printf("DIVR: %2d (4'b%s)\n", best_divr, binstr(best_divr, 4));
- printf("DIVF: %2d (7'b%s)\n", best_divf, binstr(best_divf, 7));
- printf("DIVQ: %2d (3'b%s)\n", best_divq, binstr(best_divq, 3));
+ printf("DIVR: %2d (4'b%s)\n", best_divr, binstr(best_divr, 4));
+ printf("DIVF: %2d (7'b%s)\n", best_divf, binstr(best_divf, 7));
+ printf("DIVQ: %2d (3'b%s)\n", best_divq, binstr(best_divq, 3));
- printf("\n");
+ printf("\n");
- printf("FILTER_RANGE: %d (3'b%s)\n", filter_range, binstr(filter_range, 3));
+ printf("FILTER_RANGE: %d (3'b%s)\n", filter_range, binstr(filter_range, 3));
- printf("\n");
+ printf("\n");
+ }
+
+ // save PLL configuration as file
+ if (filename != NULL)
+ {
+ // open file for writing
+ FILE *f;
+ f = fopen(filename, "w");
+
+ if (save_as_module)
+ {
+ // save PLL configuration as Verilog module
+
+ // header
+ fprintf(f, "/**\n * PLL configuration\n *\n"
+ " * This Verilog module was generated automatically\n"
+ " * using the icepll tool from the IceStorm project.\n"
+ " * Use at your own risk.\n"
+ " *\n"
+ " * Given input frequency: %8.3f MHz\n"
+ " * Requested output frequency: %8.3f MHz\n"
+ " * Achieved output frequency: %8.3f MHz\n"
+ " */\n\n",
+ f_pllin, f_pllout, best_fout);
+
+ // generate Verilog module
+ fprintf(f, "module pll(\n"
+ "\tinput clock_in,\n"
+ "\toutput clock_out,\n"
+ "\toutput locked\n"
+ "\t);\n\n"
+ );
+
+ // save iCE40 PLL tile configuration
+ fprintf(f, "SB_PLL40_CORE #(\n");
+ fprintf(f, "\t\t.FEEDBACK_PATH(\"%s\"),\n", (simple_feedback ? "SIMPLE" : "NON_SIMPLE"));
+ fprintf(f, "\t\t.DIVR(4'b%s),\t\t" "// DIVR = %2d\n", binstr(best_divr, 4), best_divr);
+ fprintf(f, "\t\t.DIVF(7'b%s),\t" "// DIVF = %2d\n", binstr(best_divf, 7), best_divf);
+ fprintf(f, "\t\t.DIVQ(3'b%s),\t\t" "// DIVQ = %2d\n", binstr(best_divq, 3), best_divq);
+ fprintf(f, "\t\t.FILTER_RANGE(3'b%s)\t" "// FILTER_RANGE = %d\n", binstr(filter_range, 3), filter_range);
+ fprintf(f, "\t) uut (\n"
+ "\t\t.LOCK(locked),\n"
+ "\t\t.RESETB(1'b1),\n"
+ "\t\t.BYPASS(1'b0),\n"
+ "\t\t.REFERENCECLK(clock_in),\n"
+ "\t\t.PLLOUTCORE(clock_out),\n"
+ "\t\t);\n\n"
+ );
+
+ fprintf(f, "endmodule\n");
+ }
+ else
+ {
+ // only save PLL configuration values
+
+ // header
+ fprintf(f, "/**\n * PLL configuration\n *\n"
+ " * This Verilog header file was generated automatically\n"
+ " * using the icepll tool from the IceStorm project.\n"
+ " * It is intended for use with FPGA primitives SB_PLL40_CORE,\n"
+ " * SB_PLL40_PAD, SB_PLL40_2_PAD, SB_PLL40_2F_CORE or SB_PLL40_2F_PAD.\n"
+ " * Use at your own risk.\n"
+ " *\n"
+ " * Given input frequency: %8.3f MHz\n"
+ " * Requested output frequency: %8.3f MHz\n"
+ " * Achieved output frequency: %8.3f MHz\n"
+ " */\n\n",
+ f_pllin, f_pllout, best_fout);
+
+ // PLL configuration
+ fprintf(f, ".FEEDBACK_PATH(\"%s\"),\n", (simple_feedback ? "SIMPLE" : "NON_SIMPLE"));
+ fprintf(f, ".DIVR(4'b%s),\t\t" "// DIVR = %2d\n", binstr(best_divr, 4), best_divr);
+ fprintf(f, ".DIVF(7'b%s),\t" "// DIVF = %2d\n", binstr(best_divf, 7), best_divf);
+ fprintf(f, ".DIVQ(3'b%s),\t\t" "// DIVQ = %2d\n", binstr(best_divq, 3), best_divq);
+ fprintf(f, ".FILTER_RANGE(3'b%s)\t" "// FILTER_RANGE = %d\n", binstr(filter_range, 3), filter_range);
+ }
+
+ fclose(f);
+
+ printf("PLL configuration written to: %s\n", filename);
+ }
return 0;
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-28 10:15:25 +0000