diff options
Diffstat (limited to 'icefuzz')
| -rw-r--r-- | icefuzz/Makefile | 17 | ||||
| -rw-r--r-- | icefuzz/cached_dsp0_5k.txt | 3272 | ||||
| -rw-r--r-- | icefuzz/cached_dsp1_5k.txt | 3033 | ||||
| -rw-r--r-- | icefuzz/cached_dsp2_5k.txt | 3057 | ||||
| -rw-r--r-- | icefuzz/cached_dsp3_5k.txt | 3159 | ||||
| -rw-r--r-- | icefuzz/cached_ipcon_5k.txt | 3471 | ||||
| -rw-r--r-- | icefuzz/cached_ramb_5k.txt | 494 | ||||
| -rw-r--r-- | icefuzz/cached_ramt_5k.txt | 459 | ||||
| -rw-r--r-- | icefuzz/database.py | 27 | ||||
| -rw-r--r-- | icefuzz/fuzzconfig.py | 8 | ||||
| -rw-r--r-- | icefuzz/glbcheck.py | 44 | ||||
| -rwxr-xr-x | icefuzz/make_dsp.py | 206 | ||||
| -rwxr-xr-x | icefuzz/make_upip.py | 218 |
13 files changed, 16479 insertions, 986 deletions
diff --git a/icefuzz/Makefile b/icefuzz/Makefile index 57e9af0..3aa02ef 100644 --- a/icefuzz/Makefile +++ b/icefuzz/Makefile @@ -42,8 +42,11 @@ ifneq ($(DEVICECLASS),384) TESTS += pll TESTS += aig endif - -database: bitdata_io.txt bitdata_logic.txt bitdata_ramb$(RAM_SUFFIX).txt bitdata_ramt$(RAM_SUFFIX).txt +ifeq ($(DEVICECLASS),5k) + TESTS += dsp + TESTS += upip +endif +database: bitdata_io.txt bitdata_logic.txt bitdata_ramb$(RAM_SUFFIX).txt bitdata_ramt$(RAM_SUFFIX).txt bitdata_dsp0_5k.txt bitdata_dsp1_5k.txt bitdata_dsp2_5k.txt bitdata_dsp3_5k.txt bitdata_ipcon_5k.txt ifneq ($(RAM_SUFFIX),) cp cached_ramb.txt bitdata_ramb.txt cp cached_ramt.txt bitdata_ramt.txt @@ -135,19 +138,19 @@ bitdata_ramt$(RAM_SUFFIX).txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_, grep ^ramt$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ bitdata_dsp0_5k.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) - grep ^dsp0_5k$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ + grep ^dsp0_5k $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ bitdata_dsp1_5k.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) - grep ^dsp1_5k$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ + grep ^dsp1_5k $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ bitdata_dsp2_5k.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) - grep ^dsp2_5k$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ + grep ^dsp2_5k $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ bitdata_dsp3_5k.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) - grep ^dsp3_5k$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ + grep ^dsp3_5k $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ bitdata_ipcon_5k.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) - grep ^ipcon_5k$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ + grep ^ipcon_5k $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ datafiles: $(addprefix data_,$(addsuffix .txt,$(TESTS))) diff --git a/icefuzz/cached_dsp0_5k.txt b/icefuzz/cached_dsp0_5k.txt index e69de29..8cfe2ba 100644 --- a/icefuzz/cached_dsp0_5k.txt +++ b/icefuzz/cached_dsp0_5k.txt @@ -0,0 +1,3272 @@ +(0 10) routing glb_netwk_2 <X> glb2local_2 +(0 10) routing glb_netwk_3 <X> glb2local_2 +(0 10) routing glb_netwk_6 <X> glb2local_2 +(0 10) routing glb_netwk_7 <X> glb2local_2 +(0 11) routing glb_netwk_1 <X> glb2local_2 +(0 11) routing glb_netwk_3 <X> glb2local_2 +(0 11) routing glb_netwk_5 <X> glb2local_2 +(0 11) routing glb_netwk_7 <X> glb2local_2 +(0 12) routing glb_netwk_2 <X> glb2local_3 +(0 12) routing glb_netwk_3 <X> glb2local_3 +(0 12) routing glb_netwk_6 <X> glb2local_3 +(0 12) routing glb_netwk_7 <X> glb2local_3 +(0 13) routing glb_netwk_1 <X> glb2local_3 +(0 13) routing glb_netwk_3 <X> glb2local_3 +(0 13) routing glb_netwk_5 <X> glb2local_3 +(0 13) routing glb_netwk_7 <X> glb2local_3 +(0 14) routing glb_netwk_4 <X> wire_mult/lc_7/s_r +(0 14) routing glb_netwk_6 <X> wire_mult/lc_7/s_r +(0 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/s_r +(0 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/s_r +(0 15) routing glb_netwk_2 <X> wire_mult/lc_7/s_r +(0 15) routing glb_netwk_6 <X> wire_mult/lc_7/s_r +(0 15) routing lc_trk_g1_5 <X> wire_mult/lc_7/s_r +(0 15) routing lc_trk_g3_5 <X> wire_mult/lc_7/s_r +(0 6) routing glb_netwk_2 <X> glb2local_0 +(0 6) routing glb_netwk_3 <X> glb2local_0 +(0 6) routing glb_netwk_6 <X> glb2local_0 +(0 6) routing glb_netwk_7 <X> glb2local_0 +(0 7) routing glb_netwk_1 <X> glb2local_0 +(0 7) routing glb_netwk_3 <X> glb2local_0 +(0 7) routing glb_netwk_5 <X> glb2local_0 +(0 7) routing glb_netwk_7 <X> glb2local_0 +(0 8) routing glb_netwk_2 <X> glb2local_1 +(0 8) routing glb_netwk_3 <X> glb2local_1 +(0 8) routing glb_netwk_6 <X> glb2local_1 +(0 8) routing glb_netwk_7 <X> glb2local_1 +(0 9) routing glb_netwk_1 <X> glb2local_1 +(0 9) routing glb_netwk_3 <X> glb2local_1 +(0 9) routing glb_netwk_5 <X> glb2local_1 +(0 9) routing glb_netwk_7 <X> glb2local_1 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 +(1 11) routing glb_netwk_4 <X> glb2local_2 +(1 11) routing glb_netwk_5 <X> glb2local_2 +(1 11) routing glb_netwk_6 <X> glb2local_2 +(1 11) routing glb_netwk_7 <X> glb2local_2 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 +(1 13) routing glb_netwk_4 <X> glb2local_3 +(1 13) routing glb_netwk_5 <X> glb2local_3 +(1 13) routing glb_netwk_6 <X> glb2local_3 +(1 13) routing glb_netwk_7 <X> glb2local_3 +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g0_4 <X> wire_mult/lc_7/s_r +(1 15) routing lc_trk_g1_5 <X> wire_mult/lc_7/s_r +(1 15) routing lc_trk_g2_4 <X> wire_mult/lc_7/s_r +(1 15) routing lc_trk_g3_5 <X> wire_mult/lc_7/s_r +(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 +(1 7) routing glb_netwk_4 <X> glb2local_0 +(1 7) routing glb_netwk_5 <X> glb2local_0 +(1 7) routing glb_netwk_6 <X> glb2local_0 +(1 7) routing glb_netwk_7 <X> glb2local_0 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 +(1 9) routing glb_netwk_4 <X> glb2local_1 +(1 9) routing glb_netwk_5 <X> glb2local_1 +(1 9) routing glb_netwk_6 <X> glb2local_1 +(1 9) routing glb_netwk_7 <X> glb2local_1 +(10 0) routing sp4_h_l_40 <X> sp4_h_r_1 +(10 0) routing sp4_h_l_47 <X> sp4_h_r_1 +(10 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(10 0) routing sp4_v_t_45 <X> sp4_h_r_1 +(10 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(10 1) routing sp4_h_r_8 <X> sp4_v_b_1 +(10 1) routing sp4_v_t_40 <X> sp4_v_b_1 +(10 1) routing sp4_v_t_47 <X> sp4_v_b_1 +(10 10) routing sp4_h_r_11 <X> sp4_h_l_42 +(10 10) routing sp4_h_r_4 <X> sp4_h_l_42 +(10 10) routing sp4_v_b_2 <X> sp4_h_l_42 +(10 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(10 11) routing sp4_h_l_39 <X> sp4_v_t_42 +(10 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(10 11) routing sp4_v_b_11 <X> sp4_v_t_42 +(10 11) routing sp4_v_b_4 <X> sp4_v_t_42 +(10 12) routing sp4_h_l_39 <X> sp4_h_r_10 +(10 12) routing sp4_h_l_42 <X> sp4_h_r_10 +(10 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(10 12) routing sp4_v_t_40 <X> sp4_h_r_10 +(10 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(10 13) routing sp4_h_r_5 <X> sp4_v_b_10 +(10 13) routing sp4_v_t_39 <X> sp4_v_b_10 +(10 13) routing sp4_v_t_42 <X> sp4_v_b_10 +(10 14) routing sp4_h_r_2 <X> sp4_h_l_47 +(10 14) routing sp4_h_r_7 <X> sp4_h_l_47 +(10 14) routing sp4_v_b_5 <X> sp4_h_l_47 +(10 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(10 15) routing sp4_h_l_40 <X> sp4_v_t_47 +(10 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(10 15) routing sp4_v_b_2 <X> sp4_v_t_47 +(10 15) routing sp4_v_b_7 <X> sp4_v_t_47 +(10 2) routing sp4_h_r_10 <X> sp4_h_l_36 +(10 2) routing sp4_h_r_5 <X> sp4_h_l_36 +(10 2) routing sp4_v_b_8 <X> sp4_h_l_36 +(10 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(10 3) routing sp4_h_l_45 <X> sp4_v_t_36 +(10 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(10 3) routing sp4_v_b_10 <X> sp4_v_t_36 +(10 3) routing sp4_v_b_5 <X> sp4_v_t_36 +(10 4) routing sp4_h_l_36 <X> sp4_h_r_4 +(10 4) routing sp4_h_l_45 <X> sp4_h_r_4 +(10 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(10 4) routing sp4_v_t_46 <X> sp4_h_r_4 +(10 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(10 5) routing sp4_h_r_11 <X> sp4_v_b_4 +(10 5) routing sp4_v_t_36 <X> sp4_v_b_4 +(10 5) routing sp4_v_t_45 <X> sp4_v_b_4 +(10 6) routing sp4_h_r_8 <X> sp4_h_l_41 +(10 6) routing sp4_v_b_11 <X> sp4_h_l_41 +(10 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(10 7) routing sp4_h_l_46 <X> sp4_v_t_41 +(10 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(10 7) routing sp4_v_b_1 <X> sp4_v_t_41 +(10 7) routing sp4_v_b_8 <X> sp4_v_t_41 +(10 8) routing sp4_h_l_41 <X> sp4_h_r_7 +(10 8) routing sp4_h_l_46 <X> sp4_h_r_7 +(10 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(10 8) routing sp4_v_t_39 <X> sp4_h_r_7 +(10 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(10 9) routing sp4_h_r_2 <X> sp4_v_b_7 +(10 9) routing sp4_v_t_41 <X> sp4_v_b_7 +(10 9) routing sp4_v_t_46 <X> sp4_v_b_7 +(11 0) routing sp4_h_l_45 <X> sp4_v_b_2 +(11 0) routing sp4_h_r_9 <X> sp4_v_b_2 +(11 0) routing sp4_v_t_43 <X> sp4_v_b_2 +(11 0) routing sp4_v_t_46 <X> sp4_v_b_2 +(11 1) routing sp4_h_l_39 <X> sp4_h_r_2 +(11 1) routing sp4_h_l_43 <X> sp4_h_r_2 +(11 1) routing sp4_v_b_2 <X> sp4_h_r_2 +(11 1) routing sp4_v_b_8 <X> sp4_h_r_2 +(11 10) routing sp4_h_l_38 <X> sp4_v_t_45 +(11 10) routing sp4_h_r_2 <X> sp4_v_t_45 +(11 10) routing sp4_v_b_0 <X> sp4_v_t_45 +(11 10) routing sp4_v_b_5 <X> sp4_v_t_45 +(11 11) routing sp4_h_r_0 <X> sp4_h_l_45 +(11 11) routing sp4_h_r_8 <X> sp4_h_l_45 +(11 11) routing sp4_v_t_39 <X> sp4_h_l_45 +(11 11) routing sp4_v_t_45 <X> sp4_h_l_45 +(11 12) routing sp4_h_l_40 <X> sp4_v_b_11 +(11 12) routing sp4_h_r_6 <X> sp4_v_b_11 +(11 12) routing sp4_v_t_38 <X> sp4_v_b_11 +(11 12) routing sp4_v_t_45 <X> sp4_v_b_11 +(11 13) routing sp4_h_l_46 <X> sp4_h_r_11 +(11 13) routing sp4_v_b_11 <X> sp4_h_r_11 +(11 13) routing sp4_v_b_5 <X> sp4_h_r_11 +(11 14) routing sp4_h_l_43 <X> sp4_v_t_46 +(11 14) routing sp4_h_r_5 <X> sp4_v_t_46 +(11 14) routing sp4_v_b_3 <X> sp4_v_t_46 +(11 14) routing sp4_v_b_8 <X> sp4_v_t_46 +(11 15) routing sp4_v_t_40 <X> sp4_h_l_46 +(11 15) routing sp4_v_t_46 <X> sp4_h_l_46 +(11 2) routing sp4_h_l_44 <X> sp4_v_t_39 +(11 2) routing sp4_h_r_8 <X> sp4_v_t_39 +(11 2) routing sp4_v_b_11 <X> sp4_v_t_39 +(11 2) routing sp4_v_b_6 <X> sp4_v_t_39 +(11 3) routing sp4_h_r_2 <X> sp4_h_l_39 +(11 3) routing sp4_h_r_6 <X> sp4_h_l_39 +(11 3) routing sp4_v_t_39 <X> sp4_h_l_39 +(11 3) routing sp4_v_t_45 <X> sp4_h_l_39 +(11 4) routing sp4_h_l_46 <X> sp4_v_b_5 +(11 4) routing sp4_h_r_0 <X> sp4_v_b_5 +(11 4) routing sp4_v_t_39 <X> sp4_v_b_5 +(11 4) routing sp4_v_t_44 <X> sp4_v_b_5 +(11 5) routing sp4_h_l_40 <X> sp4_h_r_5 +(11 5) routing sp4_h_l_44 <X> sp4_h_r_5 +(11 5) routing sp4_v_b_11 <X> sp4_h_r_5 +(11 5) routing sp4_v_b_5 <X> sp4_h_r_5 +(11 6) routing sp4_h_l_37 <X> sp4_v_t_40 +(11 6) routing sp4_h_r_11 <X> sp4_v_t_40 +(11 6) routing sp4_v_b_2 <X> sp4_v_t_40 +(11 6) routing sp4_v_b_9 <X> sp4_v_t_40 +(11 7) routing sp4_h_r_9 <X> sp4_h_l_40 +(11 7) routing sp4_v_t_40 <X> sp4_h_l_40 +(11 7) routing sp4_v_t_46 <X> sp4_h_l_40 +(11 8) routing sp4_h_l_39 <X> sp4_v_b_8 +(11 8) routing sp4_h_r_3 <X> sp4_v_b_8 +(11 8) routing sp4_v_t_37 <X> sp4_v_b_8 +(11 8) routing sp4_v_t_40 <X> sp4_v_b_8 +(11 9) routing sp4_h_l_37 <X> sp4_h_r_8 +(11 9) routing sp4_h_l_45 <X> sp4_h_r_8 +(11 9) routing sp4_v_b_2 <X> sp4_h_r_8 +(11 9) routing sp4_v_b_8 <X> sp4_h_r_8 +(12 0) routing sp4_h_l_46 <X> sp4_h_r_2 +(12 0) routing sp4_v_b_2 <X> sp4_h_r_2 +(12 0) routing sp4_v_b_8 <X> sp4_h_r_2 +(12 0) routing sp4_v_t_39 <X> sp4_h_r_2 +(12 1) routing sp4_h_l_39 <X> sp4_v_b_2 +(12 1) routing sp4_h_l_45 <X> sp4_v_b_2 +(12 1) routing sp4_h_r_2 <X> sp4_v_b_2 +(12 1) routing sp4_v_t_46 <X> sp4_v_b_2 +(12 10) routing sp4_v_b_8 <X> sp4_h_l_45 +(12 10) routing sp4_v_t_39 <X> sp4_h_l_45 +(12 10) routing sp4_v_t_45 <X> sp4_h_l_45 +(12 11) routing sp4_h_l_45 <X> sp4_v_t_45 +(12 11) routing sp4_h_r_2 <X> sp4_v_t_45 +(12 11) routing sp4_h_r_8 <X> sp4_v_t_45 +(12 11) routing sp4_v_b_5 <X> sp4_v_t_45 +(12 12) routing sp4_h_l_45 <X> sp4_h_r_11 +(12 12) routing sp4_v_b_11 <X> sp4_h_r_11 +(12 12) routing sp4_v_b_5 <X> sp4_h_r_11 +(12 12) routing sp4_v_t_46 <X> sp4_h_r_11 +(12 13) routing sp4_h_l_40 <X> sp4_v_b_11 +(12 13) routing sp4_h_l_46 <X> sp4_v_b_11 +(12 13) routing sp4_h_r_11 <X> sp4_v_b_11 +(12 13) routing sp4_v_t_45 <X> sp4_v_b_11 +(12 14) routing sp4_h_r_8 <X> sp4_h_l_46 +(12 14) routing sp4_v_b_11 <X> sp4_h_l_46 +(12 14) routing sp4_v_t_40 <X> sp4_h_l_46 +(12 14) routing sp4_v_t_46 <X> sp4_h_l_46 +(12 15) routing sp4_h_l_46 <X> sp4_v_t_46 +(12 15) routing sp4_h_r_11 <X> sp4_v_t_46 +(12 15) routing sp4_h_r_5 <X> sp4_v_t_46 +(12 15) routing sp4_v_b_8 <X> sp4_v_t_46 +(12 2) routing sp4_v_b_2 <X> sp4_h_l_39 +(12 2) routing sp4_v_t_39 <X> sp4_h_l_39 +(12 2) routing sp4_v_t_45 <X> sp4_h_l_39 +(12 3) routing sp4_h_l_39 <X> sp4_v_t_39 +(12 3) routing sp4_h_r_2 <X> sp4_v_t_39 +(12 3) routing sp4_h_r_8 <X> sp4_v_t_39 +(12 3) routing sp4_v_b_11 <X> sp4_v_t_39 +(12 4) routing sp4_h_l_39 <X> sp4_h_r_5 +(12 4) routing sp4_v_b_11 <X> sp4_h_r_5 +(12 4) routing sp4_v_b_5 <X> sp4_h_r_5 +(12 4) routing sp4_v_t_40 <X> sp4_h_r_5 +(12 5) routing sp4_h_l_40 <X> sp4_v_b_5 +(12 5) routing sp4_h_l_46 <X> sp4_v_b_5 +(12 5) routing sp4_h_r_5 <X> sp4_v_b_5 +(12 5) routing sp4_v_t_39 <X> sp4_v_b_5 +(12 6) routing sp4_h_r_2 <X> sp4_h_l_40 +(12 6) routing sp4_v_b_5 <X> sp4_h_l_40 +(12 6) routing sp4_v_t_40 <X> sp4_h_l_40 +(12 6) routing sp4_v_t_46 <X> sp4_h_l_40 +(12 7) routing sp4_h_l_40 <X> sp4_v_t_40 +(12 7) routing sp4_h_r_11 <X> sp4_v_t_40 +(12 7) routing sp4_h_r_5 <X> sp4_v_t_40 +(12 7) routing sp4_v_b_2 <X> sp4_v_t_40 +(12 8) routing sp4_v_b_2 <X> sp4_h_r_8 +(12 8) routing sp4_v_b_8 <X> sp4_h_r_8 +(12 8) routing sp4_v_t_45 <X> sp4_h_r_8 +(12 9) routing sp4_h_l_39 <X> sp4_v_b_8 +(12 9) routing sp4_h_l_45 <X> sp4_v_b_8 +(12 9) routing sp4_h_r_8 <X> sp4_v_b_8 +(12 9) routing sp4_v_t_40 <X> sp4_v_b_8 +(13 0) routing sp4_h_l_39 <X> sp4_v_b_2 +(13 0) routing sp4_h_l_45 <X> sp4_v_b_2 +(13 0) routing sp4_v_t_39 <X> sp4_v_b_2 +(13 0) routing sp4_v_t_43 <X> sp4_v_b_2 +(13 1) routing sp4_h_l_43 <X> sp4_h_r_2 +(13 1) routing sp4_h_l_46 <X> sp4_h_r_2 +(13 1) routing sp4_v_b_8 <X> sp4_h_r_2 +(13 1) routing sp4_v_t_44 <X> sp4_h_r_2 +(13 10) routing sp4_h_r_2 <X> sp4_v_t_45 +(13 10) routing sp4_h_r_8 <X> sp4_v_t_45 +(13 10) routing sp4_v_b_0 <X> sp4_v_t_45 +(13 10) routing sp4_v_b_8 <X> sp4_v_t_45 +(13 11) routing sp4_h_r_0 <X> sp4_h_l_45 +(13 11) routing sp4_v_b_3 <X> sp4_h_l_45 +(13 11) routing sp4_v_t_39 <X> sp4_h_l_45 +(13 12) routing sp4_h_l_40 <X> sp4_v_b_11 +(13 12) routing sp4_h_l_46 <X> sp4_v_b_11 +(13 12) routing sp4_v_t_38 <X> sp4_v_b_11 +(13 12) routing sp4_v_t_46 <X> sp4_v_b_11 +(13 13) routing sp4_h_l_45 <X> sp4_h_r_11 +(13 13) routing sp4_v_b_5 <X> sp4_h_r_11 +(13 13) routing sp4_v_t_43 <X> sp4_h_r_11 +(13 14) routing sp4_h_r_11 <X> sp4_v_t_46 +(13 14) routing sp4_h_r_5 <X> sp4_v_t_46 +(13 14) routing sp4_v_b_11 <X> sp4_v_t_46 +(13 14) routing sp4_v_b_3 <X> sp4_v_t_46 +(13 15) routing sp4_h_r_8 <X> sp4_h_l_46 +(13 15) routing sp4_v_b_6 <X> sp4_h_l_46 +(13 15) routing sp4_v_t_40 <X> sp4_h_l_46 +(13 2) routing sp4_h_r_2 <X> sp4_v_t_39 +(13 2) routing sp4_h_r_8 <X> sp4_v_t_39 +(13 2) routing sp4_v_b_2 <X> sp4_v_t_39 +(13 2) routing sp4_v_b_6 <X> sp4_v_t_39 +(13 3) routing sp4_h_r_6 <X> sp4_h_l_39 +(13 3) routing sp4_v_b_9 <X> sp4_h_l_39 +(13 3) routing sp4_v_t_45 <X> sp4_h_l_39 +(13 4) routing sp4_h_l_40 <X> sp4_v_b_5 +(13 4) routing sp4_h_l_46 <X> sp4_v_b_5 +(13 4) routing sp4_v_t_40 <X> sp4_v_b_5 +(13 4) routing sp4_v_t_44 <X> sp4_v_b_5 +(13 5) routing sp4_h_l_39 <X> sp4_h_r_5 +(13 5) routing sp4_h_l_44 <X> sp4_h_r_5 +(13 5) routing sp4_v_b_11 <X> sp4_h_r_5 +(13 5) routing sp4_v_t_37 <X> sp4_h_r_5 +(13 6) routing sp4_h_r_11 <X> sp4_v_t_40 +(13 6) routing sp4_h_r_5 <X> sp4_v_t_40 +(13 6) routing sp4_v_b_5 <X> sp4_v_t_40 +(13 6) routing sp4_v_b_9 <X> sp4_v_t_40 +(13 7) routing sp4_h_r_2 <X> sp4_h_l_40 +(13 7) routing sp4_h_r_9 <X> sp4_h_l_40 +(13 7) routing sp4_v_b_0 <X> sp4_h_l_40 +(13 7) routing sp4_v_t_46 <X> sp4_h_l_40 +(13 8) routing sp4_h_l_39 <X> sp4_v_b_8 +(13 8) routing sp4_h_l_45 <X> sp4_v_b_8 +(13 8) routing sp4_v_t_37 <X> sp4_v_b_8 +(13 8) routing sp4_v_t_45 <X> sp4_v_b_8 +(13 9) routing sp4_h_l_37 <X> sp4_h_r_8 +(13 9) routing sp4_v_b_2 <X> sp4_h_r_8 +(13 9) routing sp4_v_t_38 <X> sp4_h_r_8 +(14 0) routing bnr_op_0 <X> lc_trk_g0_0 +(14 0) routing lft_op_0 <X> lc_trk_g0_0 +(14 0) routing sp12_h_r_0 <X> lc_trk_g0_0 +(14 0) routing sp4_h_l_5 <X> lc_trk_g0_0 +(14 0) routing sp4_h_r_8 <X> lc_trk_g0_0 +(14 0) routing sp4_v_b_0 <X> lc_trk_g0_0 +(14 0) routing sp4_v_b_8 <X> lc_trk_g0_0 +(14 1) routing bnr_op_0 <X> lc_trk_g0_0 +(14 1) routing sp12_h_l_15 <X> lc_trk_g0_0 +(14 1) routing sp12_h_r_0 <X> lc_trk_g0_0 +(14 1) routing sp4_h_l_5 <X> lc_trk_g0_0 +(14 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(14 1) routing sp4_r_v_b_35 <X> lc_trk_g0_0 +(14 1) routing sp4_v_b_8 <X> lc_trk_g0_0 +(14 10) routing bnl_op_4 <X> lc_trk_g2_4 +(14 10) routing rgt_op_4 <X> lc_trk_g2_4 +(14 10) routing sp12_v_b_4 <X> lc_trk_g2_4 +(14 10) routing sp4_h_l_33 <X> lc_trk_g2_4 +(14 10) routing sp4_h_r_36 <X> lc_trk_g2_4 +(14 10) routing sp4_v_b_28 <X> lc_trk_g2_4 +(14 10) routing sp4_v_b_36 <X> lc_trk_g2_4 +(14 11) routing bnl_op_4 <X> lc_trk_g2_4 +(14 11) routing sp12_v_b_20 <X> lc_trk_g2_4 +(14 11) routing sp12_v_b_4 <X> lc_trk_g2_4 +(14 11) routing sp4_h_l_17 <X> lc_trk_g2_4 +(14 11) routing sp4_h_l_33 <X> lc_trk_g2_4 +(14 11) routing sp4_r_v_b_36 <X> lc_trk_g2_4 +(14 11) routing sp4_v_b_36 <X> lc_trk_g2_4 +(14 11) routing tnl_op_4 <X> lc_trk_g2_4 +(14 12) routing bnl_op_0 <X> lc_trk_g3_0 +(14 12) routing rgt_op_0 <X> lc_trk_g3_0 +(14 12) routing sp12_v_b_0 <X> lc_trk_g3_0 +(14 12) routing sp4_h_l_29 <X> lc_trk_g3_0 +(14 12) routing sp4_h_r_32 <X> lc_trk_g3_0 +(14 12) routing sp4_v_b_24 <X> lc_trk_g3_0 +(14 12) routing sp4_v_t_21 <X> lc_trk_g3_0 +(14 13) routing bnl_op_0 <X> lc_trk_g3_0 +(14 13) routing sp12_v_b_0 <X> lc_trk_g3_0 +(14 13) routing sp12_v_t_15 <X> lc_trk_g3_0 +(14 13) routing sp4_h_l_13 <X> lc_trk_g3_0 +(14 13) routing sp4_h_l_29 <X> lc_trk_g3_0 +(14 13) routing sp4_r_v_b_40 <X> lc_trk_g3_0 +(14 13) routing sp4_v_t_21 <X> lc_trk_g3_0 +(14 13) routing tnl_op_0 <X> lc_trk_g3_0 +(14 14) routing bnl_op_4 <X> lc_trk_g3_4 +(14 14) routing rgt_op_4 <X> lc_trk_g3_4 +(14 14) routing sp12_v_b_4 <X> lc_trk_g3_4 +(14 14) routing sp4_h_l_33 <X> lc_trk_g3_4 +(14 14) routing sp4_h_r_36 <X> lc_trk_g3_4 +(14 14) routing sp4_v_b_28 <X> lc_trk_g3_4 +(14 14) routing sp4_v_b_36 <X> lc_trk_g3_4 +(14 15) routing bnl_op_4 <X> lc_trk_g3_4 +(14 15) routing sp12_v_b_20 <X> lc_trk_g3_4 +(14 15) routing sp12_v_b_4 <X> lc_trk_g3_4 +(14 15) routing sp4_h_l_17 <X> lc_trk_g3_4 +(14 15) routing sp4_h_l_33 <X> lc_trk_g3_4 +(14 15) routing sp4_r_v_b_44 <X> lc_trk_g3_4 +(14 15) routing sp4_v_b_36 <X> lc_trk_g3_4 +(14 15) routing tnl_op_4 <X> lc_trk_g3_4 +(14 2) routing bnr_op_4 <X> lc_trk_g0_4 +(14 2) routing lft_op_4 <X> lc_trk_g0_4 +(14 2) routing sp12_h_l_3 <X> lc_trk_g0_4 +(14 2) routing sp4_h_r_12 <X> lc_trk_g0_4 +(14 2) routing sp4_h_r_20 <X> lc_trk_g0_4 +(14 2) routing sp4_v_b_4 <X> lc_trk_g0_4 +(14 2) routing sp4_v_t_1 <X> lc_trk_g0_4 +(14 3) routing bnr_op_4 <X> lc_trk_g0_4 +(14 3) routing sp12_h_l_19 <X> lc_trk_g0_4 +(14 3) routing sp12_h_l_3 <X> lc_trk_g0_4 +(14 3) routing sp4_h_r_20 <X> lc_trk_g0_4 +(14 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(14 3) routing sp4_r_v_b_28 <X> lc_trk_g0_4 +(14 3) routing sp4_v_t_1 <X> lc_trk_g0_4 +(14 4) routing bnr_op_0 <X> lc_trk_g1_0 +(14 4) routing lft_op_0 <X> lc_trk_g1_0 +(14 4) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 4) routing sp4_h_l_5 <X> lc_trk_g1_0 +(14 4) routing sp4_h_r_8 <X> lc_trk_g1_0 +(14 4) routing sp4_v_b_0 <X> lc_trk_g1_0 +(14 4) routing sp4_v_b_8 <X> lc_trk_g1_0 +(14 5) routing bnr_op_0 <X> lc_trk_g1_0 +(14 5) routing sp12_h_l_15 <X> lc_trk_g1_0 +(14 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp4_h_l_5 <X> lc_trk_g1_0 +(14 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0 +(14 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(14 6) routing bnr_op_4 <X> lc_trk_g1_4 +(14 6) routing lft_op_4 <X> lc_trk_g1_4 +(14 6) routing sp12_h_l_3 <X> lc_trk_g1_4 +(14 6) routing sp4_h_r_12 <X> lc_trk_g1_4 +(14 6) routing sp4_h_r_20 <X> lc_trk_g1_4 +(14 6) routing sp4_v_b_4 <X> lc_trk_g1_4 +(14 6) routing sp4_v_t_1 <X> lc_trk_g1_4 +(14 7) routing bnr_op_4 <X> lc_trk_g1_4 +(14 7) routing sp12_h_l_19 <X> lc_trk_g1_4 +(14 7) routing sp12_h_l_3 <X> lc_trk_g1_4 +(14 7) routing sp4_h_r_20 <X> lc_trk_g1_4 +(14 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4 +(14 7) routing sp4_v_t_1 <X> lc_trk_g1_4 +(14 8) routing bnl_op_0 <X> lc_trk_g2_0 +(14 8) routing rgt_op_0 <X> lc_trk_g2_0 +(14 8) routing sp12_v_b_0 <X> lc_trk_g2_0 +(14 8) routing sp4_h_l_29 <X> lc_trk_g2_0 +(14 8) routing sp4_h_r_32 <X> lc_trk_g2_0 +(14 8) routing sp4_v_b_24 <X> lc_trk_g2_0 +(14 8) routing sp4_v_t_21 <X> lc_trk_g2_0 +(14 9) routing bnl_op_0 <X> lc_trk_g2_0 +(14 9) routing sp12_v_b_0 <X> lc_trk_g2_0 +(14 9) routing sp12_v_t_15 <X> lc_trk_g2_0 +(14 9) routing sp4_h_l_13 <X> lc_trk_g2_0 +(14 9) routing sp4_h_l_29 <X> lc_trk_g2_0 +(14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0 +(14 9) routing sp4_v_t_21 <X> lc_trk_g2_0 +(14 9) routing tnl_op_0 <X> lc_trk_g2_0 +(15 0) routing lft_op_1 <X> lc_trk_g0_1 +(15 0) routing sp12_h_r_1 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_1 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(15 0) routing sp4_v_t_4 <X> lc_trk_g0_1 +(15 1) routing lft_op_0 <X> lc_trk_g0_0 +(15 1) routing sp12_h_r_0 <X> lc_trk_g0_0 +(15 1) routing sp4_h_l_5 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_8 <X> lc_trk_g0_0 +(15 1) routing sp4_v_b_16 <X> lc_trk_g0_0 +(15 10) routing rgt_op_5 <X> lc_trk_g2_5 +(15 10) routing sp12_v_b_5 <X> lc_trk_g2_5 +(15 10) routing sp4_h_l_24 <X> lc_trk_g2_5 +(15 10) routing sp4_h_l_32 <X> lc_trk_g2_5 +(15 10) routing sp4_h_r_29 <X> lc_trk_g2_5 +(15 10) routing sp4_v_b_45 <X> lc_trk_g2_5 +(15 10) routing tnl_op_5 <X> lc_trk_g2_5 +(15 10) routing tnr_op_5 <X> lc_trk_g2_5 +(15 11) routing rgt_op_4 <X> lc_trk_g2_4 +(15 11) routing sp12_v_b_4 <X> lc_trk_g2_4 +(15 11) routing sp4_h_l_17 <X> lc_trk_g2_4 +(15 11) routing sp4_h_l_33 <X> lc_trk_g2_4 +(15 11) routing sp4_h_r_36 <X> lc_trk_g2_4 +(15 11) routing sp4_v_b_44 <X> lc_trk_g2_4 +(15 11) routing tnl_op_4 <X> lc_trk_g2_4 +(15 11) routing tnr_op_4 <X> lc_trk_g2_4 +(15 12) routing rgt_op_1 <X> lc_trk_g3_1 +(15 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(15 12) routing sp4_h_l_20 <X> lc_trk_g3_1 +(15 12) routing sp4_h_r_25 <X> lc_trk_g3_1 +(15 12) routing sp4_h_r_41 <X> lc_trk_g3_1 +(15 12) routing sp4_v_t_28 <X> lc_trk_g3_1 +(15 12) routing tnl_op_1 <X> lc_trk_g3_1 +(15 12) routing tnr_op_1 <X> lc_trk_g3_1 +(15 13) routing rgt_op_0 <X> lc_trk_g3_0 +(15 13) routing sp12_v_b_0 <X> lc_trk_g3_0 +(15 13) routing sp4_h_l_13 <X> lc_trk_g3_0 +(15 13) routing sp4_h_l_29 <X> lc_trk_g3_0 +(15 13) routing sp4_h_r_32 <X> lc_trk_g3_0 +(15 13) routing sp4_v_t_29 <X> lc_trk_g3_0 +(15 13) routing tnl_op_0 <X> lc_trk_g3_0 +(15 13) routing tnr_op_0 <X> lc_trk_g3_0 +(15 14) routing rgt_op_5 <X> lc_trk_g3_5 +(15 14) routing sp12_v_b_5 <X> lc_trk_g3_5 +(15 14) routing sp4_h_l_24 <X> lc_trk_g3_5 +(15 14) routing sp4_h_l_32 <X> lc_trk_g3_5 +(15 14) routing sp4_h_r_29 <X> lc_trk_g3_5 +(15 14) routing sp4_v_b_45 <X> lc_trk_g3_5 +(15 14) routing tnl_op_5 <X> lc_trk_g3_5 +(15 14) routing tnr_op_5 <X> lc_trk_g3_5 +(15 15) routing rgt_op_4 <X> lc_trk_g3_4 +(15 15) routing sp12_v_b_4 <X> lc_trk_g3_4 +(15 15) routing sp4_h_l_17 <X> lc_trk_g3_4 +(15 15) routing sp4_h_l_33 <X> lc_trk_g3_4 +(15 15) routing sp4_h_r_36 <X> lc_trk_g3_4 +(15 15) routing sp4_v_b_44 <X> lc_trk_g3_4 +(15 15) routing tnl_op_4 <X> lc_trk_g3_4 +(15 15) routing tnr_op_4 <X> lc_trk_g3_4 +(15 2) routing lft_op_5 <X> lc_trk_g0_5 +(15 2) routing sp12_h_l_2 <X> lc_trk_g0_5 +(15 2) routing sp4_h_l_0 <X> lc_trk_g0_5 +(15 2) routing sp4_h_l_8 <X> lc_trk_g0_5 +(15 2) routing sp4_h_r_5 <X> lc_trk_g0_5 +(15 2) routing sp4_v_t_8 <X> lc_trk_g0_5 +(15 3) routing lft_op_4 <X> lc_trk_g0_4 +(15 3) routing sp12_h_l_3 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_12 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_20 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(15 3) routing sp4_v_b_20 <X> lc_trk_g0_4 +(15 4) routing lft_op_1 <X> lc_trk_g1_1 +(15 4) routing sp12_h_r_1 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_1 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(15 4) routing sp4_v_t_4 <X> lc_trk_g1_1 +(15 5) routing lft_op_0 <X> lc_trk_g1_0 +(15 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(15 5) routing sp4_h_l_5 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_8 <X> lc_trk_g1_0 +(15 5) routing sp4_v_b_16 <X> lc_trk_g1_0 +(15 6) routing lft_op_5 <X> lc_trk_g1_5 +(15 6) routing sp12_h_l_2 <X> lc_trk_g1_5 +(15 6) routing sp4_h_l_0 <X> lc_trk_g1_5 +(15 6) routing sp4_h_l_8 <X> lc_trk_g1_5 +(15 6) routing sp4_h_r_5 <X> lc_trk_g1_5 +(15 6) routing sp4_v_t_8 <X> lc_trk_g1_5 +(15 7) routing lft_op_4 <X> lc_trk_g1_4 +(15 7) routing sp12_h_l_3 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_12 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_20 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(15 7) routing sp4_v_b_20 <X> lc_trk_g1_4 +(15 8) routing rgt_op_1 <X> lc_trk_g2_1 +(15 8) routing sp12_v_b_1 <X> lc_trk_g2_1 +(15 8) routing sp4_h_l_20 <X> lc_trk_g2_1 +(15 8) routing sp4_h_r_25 <X> lc_trk_g2_1 +(15 8) routing sp4_h_r_41 <X> lc_trk_g2_1 +(15 8) routing sp4_v_t_28 <X> lc_trk_g2_1 +(15 8) routing tnl_op_1 <X> lc_trk_g2_1 +(15 8) routing tnr_op_1 <X> lc_trk_g2_1 +(15 9) routing rgt_op_0 <X> lc_trk_g2_0 +(15 9) routing sp12_v_b_0 <X> lc_trk_g2_0 +(15 9) routing sp4_h_l_13 <X> lc_trk_g2_0 +(15 9) routing sp4_h_l_29 <X> lc_trk_g2_0 +(15 9) routing sp4_h_r_32 <X> lc_trk_g2_0 +(15 9) routing sp4_v_t_29 <X> lc_trk_g2_0 +(15 9) routing tnl_op_0 <X> lc_trk_g2_0 +(15 9) routing tnr_op_0 <X> lc_trk_g2_0 +(16 0) routing sp12_h_l_14 <X> lc_trk_g0_1 +(16 0) routing sp12_h_r_9 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_1 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_1 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_9 <X> lc_trk_g0_1 +(16 0) routing sp4_v_t_4 <X> lc_trk_g0_1 +(16 1) routing sp12_h_l_15 <X> lc_trk_g0_0 +(16 1) routing sp12_h_l_7 <X> lc_trk_g0_0 +(16 1) routing sp4_h_l_5 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_8 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_0 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_16 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_8 <X> lc_trk_g0_0 +(16 10) routing sp12_v_b_21 <X> lc_trk_g2_5 +(16 10) routing sp12_v_t_10 <X> lc_trk_g2_5 +(16 10) routing sp4_h_l_24 <X> lc_trk_g2_5 +(16 10) routing sp4_h_l_32 <X> lc_trk_g2_5 +(16 10) routing sp4_h_r_29 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_29 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_45 <X> lc_trk_g2_5 +(16 10) routing sp4_v_t_24 <X> lc_trk_g2_5 +(16 11) routing sp12_v_b_20 <X> lc_trk_g2_4 +(16 11) routing sp12_v_t_11 <X> lc_trk_g2_4 +(16 11) routing sp4_h_l_17 <X> lc_trk_g2_4 +(16 11) routing sp4_h_l_33 <X> lc_trk_g2_4 +(16 11) routing sp4_h_r_36 <X> lc_trk_g2_4 +(16 11) routing sp4_v_b_28 <X> lc_trk_g2_4 +(16 11) routing sp4_v_b_36 <X> lc_trk_g2_4 +(16 11) routing sp4_v_b_44 <X> lc_trk_g2_4 +(16 12) routing sp12_v_b_9 <X> lc_trk_g3_1 +(16 12) routing sp12_v_t_14 <X> lc_trk_g3_1 +(16 12) routing sp4_h_l_20 <X> lc_trk_g3_1 +(16 12) routing sp4_h_r_25 <X> lc_trk_g3_1 +(16 12) routing sp4_h_r_41 <X> lc_trk_g3_1 +(16 12) routing sp4_v_b_25 <X> lc_trk_g3_1 +(16 12) routing sp4_v_b_33 <X> lc_trk_g3_1 +(16 12) routing sp4_v_t_28 <X> lc_trk_g3_1 +(16 13) routing sp12_v_b_8 <X> lc_trk_g3_0 +(16 13) routing sp12_v_t_15 <X> lc_trk_g3_0 +(16 13) routing sp4_h_l_13 <X> lc_trk_g3_0 +(16 13) routing sp4_h_l_29 <X> lc_trk_g3_0 +(16 13) routing sp4_h_r_32 <X> lc_trk_g3_0 +(16 13) routing sp4_v_b_24 <X> lc_trk_g3_0 +(16 13) routing sp4_v_t_21 <X> lc_trk_g3_0 +(16 13) routing sp4_v_t_29 <X> lc_trk_g3_0 +(16 14) routing sp12_v_b_21 <X> lc_trk_g3_5 +(16 14) routing sp12_v_t_10 <X> lc_trk_g3_5 +(16 14) routing sp4_h_l_24 <X> lc_trk_g3_5 +(16 14) routing sp4_h_l_32 <X> lc_trk_g3_5 +(16 14) routing sp4_h_r_29 <X> lc_trk_g3_5 +(16 14) routing sp4_v_b_29 <X> lc_trk_g3_5 +(16 14) routing sp4_v_b_45 <X> lc_trk_g3_5 +(16 14) routing sp4_v_t_24 <X> lc_trk_g3_5 +(16 15) routing sp12_v_b_20 <X> lc_trk_g3_4 +(16 15) routing sp12_v_t_11 <X> lc_trk_g3_4 +(16 15) routing sp4_h_l_17 <X> lc_trk_g3_4 +(16 15) routing sp4_h_l_33 <X> lc_trk_g3_4 +(16 15) routing sp4_h_r_36 <X> lc_trk_g3_4 +(16 15) routing sp4_v_b_28 <X> lc_trk_g3_4 +(16 15) routing sp4_v_b_36 <X> lc_trk_g3_4 +(16 15) routing sp4_v_b_44 <X> lc_trk_g3_4 +(16 2) routing sp12_h_l_10 <X> lc_trk_g0_5 +(16 2) routing sp12_h_r_21 <X> lc_trk_g0_5 +(16 2) routing sp4_h_l_0 <X> lc_trk_g0_5 +(16 2) routing sp4_h_l_8 <X> lc_trk_g0_5 +(16 2) routing sp4_h_r_5 <X> lc_trk_g0_5 +(16 2) routing sp4_v_b_13 <X> lc_trk_g0_5 +(16 2) routing sp4_v_b_5 <X> lc_trk_g0_5 +(16 2) routing sp4_v_t_8 <X> lc_trk_g0_5 +(16 3) routing sp12_h_l_19 <X> lc_trk_g0_4 +(16 3) routing sp12_h_r_12 <X> lc_trk_g0_4 +(16 3) routing sp4_h_r_12 <X> lc_trk_g0_4 +(16 3) routing sp4_h_r_20 <X> lc_trk_g0_4 +(16 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(16 3) routing sp4_v_b_20 <X> lc_trk_g0_4 +(16 3) routing sp4_v_b_4 <X> lc_trk_g0_4 +(16 3) routing sp4_v_t_1 <X> lc_trk_g0_4 +(16 4) routing sp12_h_l_14 <X> lc_trk_g1_1 +(16 4) routing sp12_h_r_9 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_1 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_1 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_9 <X> lc_trk_g1_1 +(16 4) routing sp4_v_t_4 <X> lc_trk_g1_1 +(16 5) routing sp12_h_l_15 <X> lc_trk_g1_0 +(16 5) routing sp12_h_l_7 <X> lc_trk_g1_0 +(16 5) routing sp4_h_l_5 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_8 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_0 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_16 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(16 6) routing sp12_h_l_10 <X> lc_trk_g1_5 +(16 6) routing sp12_h_r_21 <X> lc_trk_g1_5 +(16 6) routing sp4_h_l_0 <X> lc_trk_g1_5 +(16 6) routing sp4_h_l_8 <X> lc_trk_g1_5 +(16 6) routing sp4_h_r_5 <X> lc_trk_g1_5 +(16 6) routing sp4_v_b_13 <X> lc_trk_g1_5 +(16 6) routing sp4_v_b_5 <X> lc_trk_g1_5 +(16 6) routing sp4_v_t_8 <X> lc_trk_g1_5 +(16 7) routing sp12_h_l_19 <X> lc_trk_g1_4 +(16 7) routing sp12_h_r_12 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_12 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_20 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(16 7) routing sp4_v_b_20 <X> lc_trk_g1_4 +(16 7) routing sp4_v_b_4 <X> lc_trk_g1_4 +(16 7) routing sp4_v_t_1 <X> lc_trk_g1_4 +(16 8) routing sp12_v_b_9 <X> lc_trk_g2_1 +(16 8) routing sp12_v_t_14 <X> lc_trk_g2_1 +(16 8) routing sp4_h_l_20 <X> lc_trk_g2_1 +(16 8) routing sp4_h_r_25 <X> lc_trk_g2_1 +(16 8) routing sp4_h_r_41 <X> lc_trk_g2_1 +(16 8) routing sp4_v_b_25 <X> lc_trk_g2_1 +(16 8) routing sp4_v_b_33 <X> lc_trk_g2_1 +(16 8) routing sp4_v_t_28 <X> lc_trk_g2_1 +(16 9) routing sp12_v_b_8 <X> lc_trk_g2_0 +(16 9) routing sp12_v_t_15 <X> lc_trk_g2_0 +(16 9) routing sp4_h_l_13 <X> lc_trk_g2_0 +(16 9) routing sp4_h_l_29 <X> lc_trk_g2_0 +(16 9) routing sp4_h_r_32 <X> lc_trk_g2_0 +(16 9) routing sp4_v_b_24 <X> lc_trk_g2_0 +(16 9) routing sp4_v_t_21 <X> lc_trk_g2_0 +(16 9) routing sp4_v_t_29 <X> lc_trk_g2_0 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_t_4 lc_trk_g0_1 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_7 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_24 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_32 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_24 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_11 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_33 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_44 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_33 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_28 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_8 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_15 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_29 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_32 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_24 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_21 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_29 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_24 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_32 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_29 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_24 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_11 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_33 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_2 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_0 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_8 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_19 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_t_4 lc_trk_g1_1 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_7 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_2 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_0 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_19 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_20 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_41 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_28 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_15 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_29 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_24 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_29 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 +(18 0) routing bnr_op_1 <X> lc_trk_g0_1 +(18 0) routing lft_op_1 <X> lc_trk_g0_1 +(18 0) routing sp12_h_r_1 <X> lc_trk_g0_1 +(18 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(18 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(18 0) routing sp4_v_b_1 <X> lc_trk_g0_1 +(18 0) routing sp4_v_b_9 <X> lc_trk_g0_1 +(18 1) routing bnr_op_1 <X> lc_trk_g0_1 +(18 1) routing sp12_h_l_14 <X> lc_trk_g0_1 +(18 1) routing sp12_h_r_1 <X> lc_trk_g0_1 +(18 1) routing sp4_h_r_1 <X> lc_trk_g0_1 +(18 1) routing sp4_h_r_17 <X> lc_trk_g0_1 +(18 1) routing sp4_r_v_b_34 <X> lc_trk_g0_1 +(18 1) routing sp4_v_b_9 <X> lc_trk_g0_1 +(18 10) routing bnl_op_5 <X> lc_trk_g2_5 +(18 10) routing rgt_op_5 <X> lc_trk_g2_5 +(18 10) routing sp12_v_b_5 <X> lc_trk_g2_5 +(18 10) routing sp4_h_l_24 <X> lc_trk_g2_5 +(18 10) routing sp4_h_l_32 <X> lc_trk_g2_5 +(18 10) routing sp4_v_b_29 <X> lc_trk_g2_5 +(18 10) routing sp4_v_t_24 <X> lc_trk_g2_5 +(18 11) routing bnl_op_5 <X> lc_trk_g2_5 +(18 11) routing sp12_v_b_21 <X> lc_trk_g2_5 +(18 11) routing sp12_v_b_5 <X> lc_trk_g2_5 +(18 11) routing sp4_h_l_32 <X> lc_trk_g2_5 +(18 11) routing sp4_h_r_29 <X> lc_trk_g2_5 +(18 11) routing sp4_r_v_b_37 <X> lc_trk_g2_5 +(18 11) routing sp4_v_t_24 <X> lc_trk_g2_5 +(18 11) routing tnl_op_5 <X> lc_trk_g2_5 +(18 12) routing bnl_op_1 <X> lc_trk_g3_1 +(18 12) routing rgt_op_1 <X> lc_trk_g3_1 +(18 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(18 12) routing sp4_h_l_20 <X> lc_trk_g3_1 +(18 12) routing sp4_h_r_41 <X> lc_trk_g3_1 +(18 12) routing sp4_v_b_25 <X> lc_trk_g3_1 +(18 12) routing sp4_v_b_33 <X> lc_trk_g3_1 +(18 13) routing bnl_op_1 <X> lc_trk_g3_1 +(18 13) routing sp12_v_b_1 <X> lc_trk_g3_1 +(18 13) routing sp12_v_t_14 <X> lc_trk_g3_1 +(18 13) routing sp4_h_r_25 <X> lc_trk_g3_1 +(18 13) routing sp4_h_r_41 <X> lc_trk_g3_1 +(18 13) routing sp4_r_v_b_41 <X> lc_trk_g3_1 +(18 13) routing sp4_v_b_33 <X> lc_trk_g3_1 +(18 13) routing tnl_op_1 <X> lc_trk_g3_1 +(18 14) routing bnl_op_5 <X> lc_trk_g3_5 +(18 14) routing rgt_op_5 <X> lc_trk_g3_5 +(18 14) routing sp12_v_b_5 <X> lc_trk_g3_5 +(18 14) routing sp4_h_l_24 <X> lc_trk_g3_5 +(18 14) routing sp4_h_l_32 <X> lc_trk_g3_5 +(18 14) routing sp4_v_b_29 <X> lc_trk_g3_5 +(18 14) routing sp4_v_t_24 <X> lc_trk_g3_5 +(18 15) routing bnl_op_5 <X> lc_trk_g3_5 +(18 15) routing sp12_v_b_21 <X> lc_trk_g3_5 +(18 15) routing sp12_v_b_5 <X> lc_trk_g3_5 +(18 15) routing sp4_h_l_32 <X> lc_trk_g3_5 +(18 15) routing sp4_h_r_29 <X> lc_trk_g3_5 +(18 15) routing sp4_r_v_b_45 <X> lc_trk_g3_5 +(18 15) routing sp4_v_t_24 <X> lc_trk_g3_5 +(18 15) routing tnl_op_5 <X> lc_trk_g3_5 +(18 2) routing bnr_op_5 <X> lc_trk_g0_5 +(18 2) routing lft_op_5 <X> lc_trk_g0_5 +(18 2) routing sp12_h_l_2 <X> lc_trk_g0_5 +(18 2) routing sp4_h_l_0 <X> lc_trk_g0_5 +(18 2) routing sp4_h_l_8 <X> lc_trk_g0_5 +(18 2) routing sp4_v_b_13 <X> lc_trk_g0_5 +(18 2) routing sp4_v_b_5 <X> lc_trk_g0_5 +(18 3) routing bnr_op_5 <X> lc_trk_g0_5 +(18 3) routing sp12_h_l_2 <X> lc_trk_g0_5 +(18 3) routing sp12_h_r_21 <X> lc_trk_g0_5 +(18 3) routing sp4_h_l_8 <X> lc_trk_g0_5 +(18 3) routing sp4_h_r_5 <X> lc_trk_g0_5 +(18 3) routing sp4_r_v_b_29 <X> lc_trk_g0_5 +(18 3) routing sp4_v_b_13 <X> lc_trk_g0_5 +(18 4) routing bnr_op_1 <X> lc_trk_g1_1 +(18 4) routing lft_op_1 <X> lc_trk_g1_1 +(18 4) routing sp12_h_r_1 <X> lc_trk_g1_1 +(18 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(18 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(18 4) routing sp4_v_b_1 <X> lc_trk_g1_1 +(18 4) routing sp4_v_b_9 <X> lc_trk_g1_1 +(18 5) routing bnr_op_1 <X> lc_trk_g1_1 +(18 5) routing sp12_h_l_14 <X> lc_trk_g1_1 +(18 5) routing sp12_h_r_1 <X> lc_trk_g1_1 +(18 5) routing sp4_h_r_1 <X> lc_trk_g1_1 +(18 5) routing sp4_h_r_17 <X> lc_trk_g1_1 +(18 5) routing sp4_r_v_b_25 <X> lc_trk_g1_1 +(18 5) routing sp4_v_b_9 <X> lc_trk_g1_1 +(18 6) routing bnr_op_5 <X> lc_trk_g1_5 +(18 6) routing lft_op_5 <X> lc_trk_g1_5 +(18 6) routing sp12_h_l_2 <X> lc_trk_g1_5 +(18 6) routing sp4_h_l_0 <X> lc_trk_g1_5 +(18 6) routing sp4_h_l_8 <X> lc_trk_g1_5 +(18 6) routing sp4_v_b_13 <X> lc_trk_g1_5 +(18 6) routing sp4_v_b_5 <X> lc_trk_g1_5 +(18 7) routing bnr_op_5 <X> lc_trk_g1_5 +(18 7) routing sp12_h_l_2 <X> lc_trk_g1_5 +(18 7) routing sp12_h_r_21 <X> lc_trk_g1_5 +(18 7) routing sp4_h_l_8 <X> lc_trk_g1_5 +(18 7) routing sp4_h_r_5 <X> lc_trk_g1_5 +(18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5 +(18 7) routing sp4_v_b_13 <X> lc_trk_g1_5 +(18 8) routing bnl_op_1 <X> lc_trk_g2_1 +(18 8) routing rgt_op_1 <X> lc_trk_g2_1 +(18 8) routing sp12_v_b_1 <X> lc_trk_g2_1 +(18 8) routing sp4_h_l_20 <X> lc_trk_g2_1 +(18 8) routing sp4_h_r_41 <X> lc_trk_g2_1 +(18 8) routing sp4_v_b_25 <X> lc_trk_g2_1 +(18 8) routing sp4_v_b_33 <X> lc_trk_g2_1 +(18 9) routing bnl_op_1 <X> lc_trk_g2_1 +(18 9) routing sp12_v_b_1 <X> lc_trk_g2_1 +(18 9) routing sp12_v_t_14 <X> lc_trk_g2_1 +(18 9) routing sp4_h_r_25 <X> lc_trk_g2_1 +(18 9) routing sp4_h_r_41 <X> lc_trk_g2_1 +(18 9) routing sp4_r_v_b_33 <X> lc_trk_g2_1 +(18 9) routing sp4_v_b_33 <X> lc_trk_g2_1 +(18 9) routing tnl_op_1 <X> lc_trk_g2_1 +(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_t_0 sp4_v_b_13 +(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_t_1 +(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_t_10 +(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_t_11 +(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_l_1 sp4_h_l_0 +(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_r_12 +(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_r_15 +(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3 +(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_b_7 sp4_v_t_2 +(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14 +(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_t_8 sp4_v_t_4 +(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16 +(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_t_6 +(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_b_18 +(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_b_19 sp4_v_t_8 +(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_b_20 +(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_l_7 sp4_h_l_5 +(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_l_8 +(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_l_19 sp4_h_l_11 +(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_l_10 +(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_l_7 +(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_r_14 sp4_h_r_19 +(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_l_15 sp4_h_r_20 +(21 0) routing bnr_op_3 <X> lc_trk_g0_3 +(21 0) routing lft_op_3 <X> lc_trk_g0_3 +(21 0) routing sp12_h_r_3 <X> lc_trk_g0_3 +(21 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(21 0) routing sp4_h_r_19 <X> lc_trk_g0_3 +(21 0) routing sp4_v_b_11 <X> lc_trk_g0_3 +(21 0) routing sp4_v_b_3 <X> lc_trk_g0_3 +(21 1) routing bnr_op_3 <X> lc_trk_g0_3 +(21 1) routing sp12_h_l_16 <X> lc_trk_g0_3 +(21 1) routing sp12_h_r_3 <X> lc_trk_g0_3 +(21 1) routing sp4_h_r_19 <X> lc_trk_g0_3 +(21 1) routing sp4_h_r_3 <X> lc_trk_g0_3 +(21 1) routing sp4_r_v_b_32 <X> lc_trk_g0_3 +(21 1) routing sp4_v_b_11 <X> lc_trk_g0_3 +(21 10) routing bnl_op_7 <X> lc_trk_g2_7 +(21 10) routing rgt_op_7 <X> lc_trk_g2_7 +(21 10) routing sp12_v_b_7 <X> lc_trk_g2_7 +(21 10) routing sp4_h_r_39 <X> lc_trk_g2_7 +(21 10) routing sp4_h_r_47 <X> lc_trk_g2_7 +(21 10) routing sp4_v_b_39 <X> lc_trk_g2_7 +(21 10) routing sp4_v_t_18 <X> lc_trk_g2_7 +(21 11) routing bnl_op_7 <X> lc_trk_g2_7 +(21 11) routing sp12_v_b_23 <X> lc_trk_g2_7 +(21 11) routing sp12_v_b_7 <X> lc_trk_g2_7 +(21 11) routing sp4_h_l_18 <X> lc_trk_g2_7 +(21 11) routing sp4_h_r_47 <X> lc_trk_g2_7 +(21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7 +(21 11) routing sp4_v_b_39 <X> lc_trk_g2_7 +(21 11) routing tnl_op_7 <X> lc_trk_g2_7 +(21 12) routing bnl_op_3 <X> lc_trk_g3_3 +(21 12) routing rgt_op_3 <X> lc_trk_g3_3 +(21 12) routing sp12_v_t_0 <X> lc_trk_g3_3 +(21 12) routing sp4_h_l_22 <X> lc_trk_g3_3 +(21 12) routing sp4_h_l_30 <X> lc_trk_g3_3 +(21 12) routing sp4_v_b_27 <X> lc_trk_g3_3 +(21 12) routing sp4_v_t_22 <X> lc_trk_g3_3 +(21 13) routing bnl_op_3 <X> lc_trk_g3_3 +(21 13) routing sp12_v_b_19 <X> lc_trk_g3_3 +(21 13) routing sp12_v_t_0 <X> lc_trk_g3_3 +(21 13) routing sp4_h_l_14 <X> lc_trk_g3_3 +(21 13) routing sp4_h_l_30 <X> lc_trk_g3_3 +(21 13) routing sp4_r_v_b_43 <X> lc_trk_g3_3 +(21 13) routing sp4_v_t_22 <X> lc_trk_g3_3 +(21 13) routing tnl_op_3 <X> lc_trk_g3_3 +(21 14) routing bnl_op_7 <X> lc_trk_g3_7 +(21 14) routing rgt_op_7 <X> lc_trk_g3_7 +(21 14) routing sp12_v_b_7 <X> lc_trk_g3_7 +(21 14) routing sp4_h_r_39 <X> lc_trk_g3_7 +(21 14) routing sp4_h_r_47 <X> lc_trk_g3_7 +(21 14) routing sp4_v_b_39 <X> lc_trk_g3_7 +(21 14) routing sp4_v_t_18 <X> lc_trk_g3_7 +(21 15) routing bnl_op_7 <X> lc_trk_g3_7 +(21 15) routing sp12_v_b_23 <X> lc_trk_g3_7 +(21 15) routing sp12_v_b_7 <X> lc_trk_g3_7 +(21 15) routing sp4_h_l_18 <X> lc_trk_g3_7 +(21 15) routing sp4_h_r_47 <X> lc_trk_g3_7 +(21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7 +(21 15) routing sp4_v_b_39 <X> lc_trk_g3_7 +(21 15) routing tnl_op_7 <X> lc_trk_g3_7 +(21 2) routing bnr_op_7 <X> lc_trk_g0_7 +(21 2) routing lft_op_7 <X> lc_trk_g0_7 +(21 2) routing sp12_h_r_7 <X> lc_trk_g0_7 +(21 2) routing sp4_h_l_10 <X> lc_trk_g0_7 +(21 2) routing sp4_h_r_15 <X> lc_trk_g0_7 +(21 2) routing sp4_v_b_7 <X> lc_trk_g0_7 +(21 2) routing sp4_v_t_2 <X> lc_trk_g0_7 +(21 3) routing bnr_op_7 <X> lc_trk_g0_7 +(21 3) routing sp12_h_l_20 <X> lc_trk_g0_7 +(21 3) routing sp12_h_r_7 <X> lc_trk_g0_7 +(21 3) routing sp4_h_l_10 <X> lc_trk_g0_7 +(21 3) routing sp4_h_r_7 <X> lc_trk_g0_7 +(21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7 +(21 3) routing sp4_v_t_2 <X> lc_trk_g0_7 +(21 4) routing bnr_op_3 <X> lc_trk_g1_3 +(21 4) routing lft_op_3 <X> lc_trk_g1_3 +(21 4) routing sp12_h_r_3 <X> lc_trk_g1_3 +(21 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(21 4) routing sp4_h_r_19 <X> lc_trk_g1_3 +(21 4) routing sp4_v_b_11 <X> lc_trk_g1_3 +(21 4) routing sp4_v_b_3 <X> lc_trk_g1_3 +(21 5) routing bnr_op_3 <X> lc_trk_g1_3 +(21 5) routing sp12_h_l_16 <X> lc_trk_g1_3 +(21 5) routing sp12_h_r_3 <X> lc_trk_g1_3 +(21 5) routing sp4_h_r_19 <X> lc_trk_g1_3 +(21 5) routing sp4_h_r_3 <X> lc_trk_g1_3 +(21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3 +(21 5) routing sp4_v_b_11 <X> lc_trk_g1_3 +(21 6) routing bnr_op_7 <X> lc_trk_g1_7 +(21 6) routing lft_op_7 <X> lc_trk_g1_7 +(21 6) routing sp12_h_r_7 <X> lc_trk_g1_7 +(21 6) routing sp4_h_l_10 <X> lc_trk_g1_7 +(21 6) routing sp4_h_r_15 <X> lc_trk_g1_7 +(21 6) routing sp4_v_b_7 <X> lc_trk_g1_7 +(21 6) routing sp4_v_t_2 <X> lc_trk_g1_7 +(21 7) routing bnr_op_7 <X> lc_trk_g1_7 +(21 7) routing sp12_h_l_20 <X> lc_trk_g1_7 +(21 7) routing sp12_h_r_7 <X> lc_trk_g1_7 +(21 7) routing sp4_h_l_10 <X> lc_trk_g1_7 +(21 7) routing sp4_h_r_7 <X> lc_trk_g1_7 +(21 7) routing sp4_r_v_b_31 <X> lc_trk_g1_7 +(21 7) routing sp4_v_t_2 <X> lc_trk_g1_7 +(21 8) routing bnl_op_3 <X> lc_trk_g2_3 +(21 8) routing rgt_op_3 <X> lc_trk_g2_3 +(21 8) routing sp12_v_t_0 <X> lc_trk_g2_3 +(21 8) routing sp4_h_l_22 <X> lc_trk_g2_3 +(21 8) routing sp4_h_l_30 <X> lc_trk_g2_3 +(21 8) routing sp4_v_b_27 <X> lc_trk_g2_3 +(21 8) routing sp4_v_t_22 <X> lc_trk_g2_3 +(21 9) routing bnl_op_3 <X> lc_trk_g2_3 +(21 9) routing sp12_v_b_19 <X> lc_trk_g2_3 +(21 9) routing sp12_v_t_0 <X> lc_trk_g2_3 +(21 9) routing sp4_h_l_14 <X> lc_trk_g2_3 +(21 9) routing sp4_h_l_30 <X> lc_trk_g2_3 +(21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3 +(21 9) routing sp4_v_t_22 <X> lc_trk_g2_3 +(21 9) routing tnl_op_3 <X> lc_trk_g2_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_t_6 lc_trk_g0_3 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_1 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_13 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_21 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_35 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_30 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_0 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_8 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_14 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_22 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_30 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_22 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_10 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_17 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_23 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_31 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_26 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_39 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_39 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_13 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_35 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_38 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_30 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_38 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_10 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_t_6 lc_trk_g1_3 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_1 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_17 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_18 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_15 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_10 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_14 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_30 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_27 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_43 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_22 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_17 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_23 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_26 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 +(23 0) routing sp12_h_l_16 <X> lc_trk_g0_3 +(23 0) routing sp12_h_r_11 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_19 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_3 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_11 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_3 <X> lc_trk_g0_3 +(23 0) routing sp4_v_t_6 <X> lc_trk_g0_3 +(23 1) routing sp12_h_l_17 <X> lc_trk_g0_2 +(23 1) routing sp12_h_l_9 <X> lc_trk_g0_2 +(23 1) routing sp4_h_l_7 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_10 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_10 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_18 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_2 <X> lc_trk_g0_2 +(23 10) routing sp12_v_b_23 <X> lc_trk_g2_7 +(23 10) routing sp12_v_t_12 <X> lc_trk_g2_7 +(23 10) routing sp4_h_l_18 <X> lc_trk_g2_7 +(23 10) routing sp4_h_r_39 <X> lc_trk_g2_7 +(23 10) routing sp4_h_r_47 <X> lc_trk_g2_7 +(23 10) routing sp4_v_b_39 <X> lc_trk_g2_7 +(23 10) routing sp4_v_t_18 <X> lc_trk_g2_7 +(23 10) routing sp4_v_t_34 <X> lc_trk_g2_7 +(23 11) routing sp12_v_t_13 <X> lc_trk_g2_6 +(23 11) routing sp12_v_t_21 <X> lc_trk_g2_6 +(23 11) routing sp4_h_l_35 <X> lc_trk_g2_6 +(23 11) routing sp4_h_r_30 <X> lc_trk_g2_6 +(23 11) routing sp4_h_r_38 <X> lc_trk_g2_6 +(23 11) routing sp4_v_b_30 <X> lc_trk_g2_6 +(23 11) routing sp4_v_b_38 <X> lc_trk_g2_6 +(23 11) routing sp4_v_b_46 <X> lc_trk_g2_6 +(23 12) routing sp12_v_b_19 <X> lc_trk_g3_3 +(23 12) routing sp12_v_t_8 <X> lc_trk_g3_3 +(23 12) routing sp4_h_l_14 <X> lc_trk_g3_3 +(23 12) routing sp4_h_l_22 <X> lc_trk_g3_3 +(23 12) routing sp4_h_l_30 <X> lc_trk_g3_3 +(23 12) routing sp4_v_b_27 <X> lc_trk_g3_3 +(23 12) routing sp4_v_b_43 <X> lc_trk_g3_3 +(23 12) routing sp4_v_t_22 <X> lc_trk_g3_3 +(23 13) routing sp12_v_b_10 <X> lc_trk_g3_2 +(23 13) routing sp12_v_t_17 <X> lc_trk_g3_2 +(23 13) routing sp4_h_l_23 <X> lc_trk_g3_2 +(23 13) routing sp4_h_l_31 <X> lc_trk_g3_2 +(23 13) routing sp4_h_r_26 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_15 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_23 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_31 <X> lc_trk_g3_2 +(23 14) routing sp12_v_b_23 <X> lc_trk_g3_7 +(23 14) routing sp12_v_t_12 <X> lc_trk_g3_7 +(23 14) routing sp4_h_l_18 <X> lc_trk_g3_7 +(23 14) routing sp4_h_r_39 <X> lc_trk_g3_7 +(23 14) routing sp4_h_r_47 <X> lc_trk_g3_7 +(23 14) routing sp4_v_b_39 <X> lc_trk_g3_7 +(23 14) routing sp4_v_t_18 <X> lc_trk_g3_7 +(23 14) routing sp4_v_t_34 <X> lc_trk_g3_7 +(23 15) routing sp12_v_t_13 <X> lc_trk_g3_6 +(23 15) routing sp12_v_t_21 <X> lc_trk_g3_6 +(23 15) routing sp4_h_l_35 <X> lc_trk_g3_6 +(23 15) routing sp4_h_r_30 <X> lc_trk_g3_6 +(23 15) routing sp4_h_r_38 <X> lc_trk_g3_6 +(23 15) routing sp4_v_b_30 <X> lc_trk_g3_6 +(23 15) routing sp4_v_b_38 <X> lc_trk_g3_6 +(23 15) routing sp4_v_b_46 <X> lc_trk_g3_6 +(23 2) routing sp12_h_l_12 <X> lc_trk_g0_7 +(23 2) routing sp12_h_l_20 <X> lc_trk_g0_7 +(23 2) routing sp4_h_l_10 <X> lc_trk_g0_7 +(23 2) routing sp4_h_r_15 <X> lc_trk_g0_7 +(23 2) routing sp4_h_r_7 <X> lc_trk_g0_7 +(23 2) routing sp4_v_b_7 <X> lc_trk_g0_7 +(23 2) routing sp4_v_t_10 <X> lc_trk_g0_7 +(23 2) routing sp4_v_t_2 <X> lc_trk_g0_7 +(23 3) routing sp12_h_r_14 <X> lc_trk_g0_6 +(23 3) routing sp12_h_r_22 <X> lc_trk_g0_6 +(23 3) routing sp4_h_l_11 <X> lc_trk_g0_6 +(23 3) routing sp4_h_l_3 <X> lc_trk_g0_6 +(23 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(23 3) routing sp4_v_b_14 <X> lc_trk_g0_6 +(23 3) routing sp4_v_b_6 <X> lc_trk_g0_6 +(23 3) routing sp4_v_t_11 <X> lc_trk_g0_6 +(23 4) routing sp12_h_l_16 <X> lc_trk_g1_3 +(23 4) routing sp12_h_r_11 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_19 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_3 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_11 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_3 <X> lc_trk_g1_3 +(23 4) routing sp4_v_t_6 <X> lc_trk_g1_3 +(23 5) routing sp12_h_l_17 <X> lc_trk_g1_2 +(23 5) routing sp12_h_l_9 <X> lc_trk_g1_2 +(23 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_10 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_18 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_2 <X> lc_trk_g1_2 +(23 6) routing sp12_h_l_12 <X> lc_trk_g1_7 +(23 6) routing sp12_h_l_20 <X> lc_trk_g1_7 +(23 6) routing sp4_h_l_10 <X> lc_trk_g1_7 +(23 6) routing sp4_h_r_15 <X> lc_trk_g1_7 +(23 6) routing sp4_h_r_7 <X> lc_trk_g1_7 +(23 6) routing sp4_v_b_7 <X> lc_trk_g1_7 +(23 6) routing sp4_v_t_10 <X> lc_trk_g1_7 +(23 6) routing sp4_v_t_2 <X> lc_trk_g1_7 +(23 7) routing sp12_h_r_14 <X> lc_trk_g1_6 +(23 7) routing sp12_h_r_22 <X> lc_trk_g1_6 +(23 7) routing sp4_h_l_11 <X> lc_trk_g1_6 +(23 7) routing sp4_h_l_3 <X> lc_trk_g1_6 +(23 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_14 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_6 <X> lc_trk_g1_6 +(23 7) routing sp4_v_t_11 <X> lc_trk_g1_6 +(23 8) routing sp12_v_b_19 <X> lc_trk_g2_3 +(23 8) routing sp12_v_t_8 <X> lc_trk_g2_3 +(23 8) routing sp4_h_l_14 <X> lc_trk_g2_3 +(23 8) routing sp4_h_l_22 <X> lc_trk_g2_3 +(23 8) routing sp4_h_l_30 <X> lc_trk_g2_3 +(23 8) routing sp4_v_b_27 <X> lc_trk_g2_3 +(23 8) routing sp4_v_b_43 <X> lc_trk_g2_3 +(23 8) routing sp4_v_t_22 <X> lc_trk_g2_3 +(23 9) routing sp12_v_b_10 <X> lc_trk_g2_2 +(23 9) routing sp12_v_t_17 <X> lc_trk_g2_2 +(23 9) routing sp4_h_l_23 <X> lc_trk_g2_2 +(23 9) routing sp4_h_l_31 <X> lc_trk_g2_2 +(23 9) routing sp4_h_r_26 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_15 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_23 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_31 <X> lc_trk_g2_2 +(24 0) routing lft_op_3 <X> lc_trk_g0_3 +(24 0) routing sp12_h_r_3 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_19 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_3 <X> lc_trk_g0_3 +(24 0) routing sp4_v_t_6 <X> lc_trk_g0_3 +(24 1) routing lft_op_2 <X> lc_trk_g0_2 +(24 1) routing sp12_h_l_1 <X> lc_trk_g0_2 +(24 1) routing sp4_h_l_7 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_10 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(24 1) routing sp4_v_b_18 <X> lc_trk_g0_2 +(24 10) routing rgt_op_7 <X> lc_trk_g2_7 +(24 10) routing sp12_v_b_7 <X> lc_trk_g2_7 +(24 10) routing sp4_h_l_18 <X> lc_trk_g2_7 +(24 10) routing sp4_h_r_39 <X> lc_trk_g2_7 +(24 10) routing sp4_h_r_47 <X> lc_trk_g2_7 +(24 10) routing sp4_v_t_34 <X> lc_trk_g2_7 +(24 10) routing tnl_op_7 <X> lc_trk_g2_7 +(24 10) routing tnr_op_7 <X> lc_trk_g2_7 +(24 11) routing rgt_op_6 <X> lc_trk_g2_6 +(24 11) routing sp12_v_b_6 <X> lc_trk_g2_6 +(24 11) routing sp4_h_l_35 <X> lc_trk_g2_6 +(24 11) routing sp4_h_r_30 <X> lc_trk_g2_6 +(24 11) routing sp4_h_r_38 <X> lc_trk_g2_6 +(24 11) routing sp4_v_b_46 <X> lc_trk_g2_6 +(24 11) routing tnl_op_6 <X> lc_trk_g2_6 +(24 11) routing tnr_op_6 <X> lc_trk_g2_6 +(24 12) routing rgt_op_3 <X> lc_trk_g3_3 +(24 12) routing sp12_v_t_0 <X> lc_trk_g3_3 +(24 12) routing sp4_h_l_14 <X> lc_trk_g3_3 +(24 12) routing sp4_h_l_22 <X> lc_trk_g3_3 +(24 12) routing sp4_h_l_30 <X> lc_trk_g3_3 +(24 12) routing sp4_v_b_43 <X> lc_trk_g3_3 +(24 12) routing tnl_op_3 <X> lc_trk_g3_3 +(24 12) routing tnr_op_3 <X> lc_trk_g3_3 +(24 13) routing rgt_op_2 <X> lc_trk_g3_2 +(24 13) routing sp12_v_b_2 <X> lc_trk_g3_2 +(24 13) routing sp4_h_l_23 <X> lc_trk_g3_2 +(24 13) routing sp4_h_l_31 <X> lc_trk_g3_2 +(24 13) routing sp4_h_r_26 <X> lc_trk_g3_2 +(24 13) routing sp4_v_t_31 <X> lc_trk_g3_2 +(24 13) routing tnl_op_2 <X> lc_trk_g3_2 +(24 13) routing tnr_op_2 <X> lc_trk_g3_2 +(24 14) routing rgt_op_7 <X> lc_trk_g3_7 +(24 14) routing sp12_v_b_7 <X> lc_trk_g3_7 +(24 14) routing sp4_h_l_18 <X> lc_trk_g3_7 +(24 14) routing sp4_h_r_39 <X> lc_trk_g3_7 +(24 14) routing sp4_h_r_47 <X> lc_trk_g3_7 +(24 14) routing sp4_v_t_34 <X> lc_trk_g3_7 +(24 14) routing tnl_op_7 <X> lc_trk_g3_7 +(24 14) routing tnr_op_7 <X> lc_trk_g3_7 +(24 15) routing rgt_op_6 <X> lc_trk_g3_6 +(24 15) routing sp12_v_b_6 <X> lc_trk_g3_6 +(24 15) routing sp4_h_l_35 <X> lc_trk_g3_6 +(24 15) routing sp4_h_r_30 <X> lc_trk_g3_6 +(24 15) routing sp4_h_r_38 <X> lc_trk_g3_6 +(24 15) routing sp4_v_b_46 <X> lc_trk_g3_6 +(24 15) routing tnl_op_6 <X> lc_trk_g3_6 +(24 15) routing tnr_op_6 <X> lc_trk_g3_6 +(24 2) routing lft_op_7 <X> lc_trk_g0_7 +(24 2) routing sp12_h_r_7 <X> lc_trk_g0_7 +(24 2) routing sp4_h_l_10 <X> lc_trk_g0_7 +(24 2) routing sp4_h_r_15 <X> lc_trk_g0_7 +(24 2) routing sp4_h_r_7 <X> lc_trk_g0_7 +(24 2) routing sp4_v_t_10 <X> lc_trk_g0_7 +(24 3) routing lft_op_6 <X> lc_trk_g0_6 +(24 3) routing sp12_h_l_5 <X> lc_trk_g0_6 +(24 3) routing sp4_h_l_11 <X> lc_trk_g0_6 +(24 3) routing sp4_h_l_3 <X> lc_trk_g0_6 +(24 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(24 3) routing sp4_v_t_11 <X> lc_trk_g0_6 +(24 4) routing lft_op_3 <X> lc_trk_g1_3 +(24 4) routing sp12_h_r_3 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_19 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_3 <X> lc_trk_g1_3 +(24 4) routing sp4_v_t_6 <X> lc_trk_g1_3 +(24 5) routing lft_op_2 <X> lc_trk_g1_2 +(24 5) routing sp12_h_l_1 <X> lc_trk_g1_2 +(24 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(24 5) routing sp4_v_b_18 <X> lc_trk_g1_2 +(24 6) routing lft_op_7 <X> lc_trk_g1_7 +(24 6) routing sp12_h_r_7 <X> lc_trk_g1_7 +(24 6) routing sp4_h_l_10 <X> lc_trk_g1_7 +(24 6) routing sp4_h_r_15 <X> lc_trk_g1_7 +(24 6) routing sp4_h_r_7 <X> lc_trk_g1_7 +(24 6) routing sp4_v_t_10 <X> lc_trk_g1_7 +(24 7) routing lft_op_6 <X> lc_trk_g1_6 +(24 7) routing sp12_h_l_5 <X> lc_trk_g1_6 +(24 7) routing sp4_h_l_11 <X> lc_trk_g1_6 +(24 7) routing sp4_h_l_3 <X> lc_trk_g1_6 +(24 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(24 7) routing sp4_v_t_11 <X> lc_trk_g1_6 +(24 8) routing rgt_op_3 <X> lc_trk_g2_3 +(24 8) routing sp12_v_t_0 <X> lc_trk_g2_3 +(24 8) routing sp4_h_l_14 <X> lc_trk_g2_3 +(24 8) routing sp4_h_l_22 <X> lc_trk_g2_3 +(24 8) routing sp4_h_l_30 <X> lc_trk_g2_3 +(24 8) routing sp4_v_b_43 <X> lc_trk_g2_3 +(24 8) routing tnl_op_3 <X> lc_trk_g2_3 +(24 8) routing tnr_op_3 <X> lc_trk_g2_3 +(24 9) routing rgt_op_2 <X> lc_trk_g2_2 +(24 9) routing sp12_v_b_2 <X> lc_trk_g2_2 +(24 9) routing sp4_h_l_23 <X> lc_trk_g2_2 +(24 9) routing sp4_h_l_31 <X> lc_trk_g2_2 +(24 9) routing sp4_h_r_26 <X> lc_trk_g2_2 +(24 9) routing sp4_v_t_31 <X> lc_trk_g2_2 +(24 9) routing tnl_op_2 <X> lc_trk_g2_2 +(24 9) routing tnr_op_2 <X> lc_trk_g2_2 +(25 0) routing bnr_op_2 <X> lc_trk_g0_2 +(25 0) routing lft_op_2 <X> lc_trk_g0_2 +(25 0) routing sp12_h_l_1 <X> lc_trk_g0_2 +(25 0) routing sp4_h_l_7 <X> lc_trk_g0_2 +(25 0) routing sp4_h_r_10 <X> lc_trk_g0_2 +(25 0) routing sp4_v_b_10 <X> lc_trk_g0_2 +(25 0) routing sp4_v_b_2 <X> lc_trk_g0_2 +(25 1) routing bnr_op_2 <X> lc_trk_g0_2 +(25 1) routing sp12_h_l_1 <X> lc_trk_g0_2 +(25 1) routing sp12_h_l_17 <X> lc_trk_g0_2 +(25 1) routing sp4_h_l_7 <X> lc_trk_g0_2 +(25 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(25 1) routing sp4_r_v_b_33 <X> lc_trk_g0_2 +(25 1) routing sp4_v_b_10 <X> lc_trk_g0_2 +(25 10) routing bnl_op_6 <X> lc_trk_g2_6 +(25 10) routing rgt_op_6 <X> lc_trk_g2_6 +(25 10) routing sp12_v_b_6 <X> lc_trk_g2_6 +(25 10) routing sp4_h_l_35 <X> lc_trk_g2_6 +(25 10) routing sp4_h_r_38 <X> lc_trk_g2_6 +(25 10) routing sp4_v_b_30 <X> lc_trk_g2_6 +(25 10) routing sp4_v_b_38 <X> lc_trk_g2_6 +(25 11) routing bnl_op_6 <X> lc_trk_g2_6 +(25 11) routing sp12_v_b_6 <X> lc_trk_g2_6 +(25 11) routing sp12_v_t_21 <X> lc_trk_g2_6 +(25 11) routing sp4_h_l_35 <X> lc_trk_g2_6 +(25 11) routing sp4_h_r_30 <X> lc_trk_g2_6 +(25 11) routing sp4_r_v_b_38 <X> lc_trk_g2_6 +(25 11) routing sp4_v_b_38 <X> lc_trk_g2_6 +(25 11) routing tnl_op_6 <X> lc_trk_g2_6 +(25 12) routing bnl_op_2 <X> lc_trk_g3_2 +(25 12) routing rgt_op_2 <X> lc_trk_g3_2 +(25 12) routing sp12_v_b_2 <X> lc_trk_g3_2 +(25 12) routing sp4_h_l_23 <X> lc_trk_g3_2 +(25 12) routing sp4_h_l_31 <X> lc_trk_g3_2 +(25 12) routing sp4_v_t_15 <X> lc_trk_g3_2 +(25 12) routing sp4_v_t_23 <X> lc_trk_g3_2 +(25 13) routing bnl_op_2 <X> lc_trk_g3_2 +(25 13) routing sp12_v_b_2 <X> lc_trk_g3_2 +(25 13) routing sp12_v_t_17 <X> lc_trk_g3_2 +(25 13) routing sp4_h_l_31 <X> lc_trk_g3_2 +(25 13) routing sp4_h_r_26 <X> lc_trk_g3_2 +(25 13) routing sp4_r_v_b_42 <X> lc_trk_g3_2 +(25 13) routing sp4_v_t_23 <X> lc_trk_g3_2 +(25 13) routing tnl_op_2 <X> lc_trk_g3_2 +(25 14) routing bnl_op_6 <X> lc_trk_g3_6 +(25 14) routing rgt_op_6 <X> lc_trk_g3_6 +(25 14) routing sp12_v_b_6 <X> lc_trk_g3_6 +(25 14) routing sp4_h_l_35 <X> lc_trk_g3_6 +(25 14) routing sp4_h_r_38 <X> lc_trk_g3_6 +(25 14) routing sp4_v_b_30 <X> lc_trk_g3_6 +(25 14) routing sp4_v_b_38 <X> lc_trk_g3_6 +(25 15) routing bnl_op_6 <X> lc_trk_g3_6 +(25 15) routing sp12_v_b_6 <X> lc_trk_g3_6 +(25 15) routing sp12_v_t_21 <X> lc_trk_g3_6 +(25 15) routing sp4_h_l_35 <X> lc_trk_g3_6 +(25 15) routing sp4_h_r_30 <X> lc_trk_g3_6 +(25 15) routing sp4_r_v_b_46 <X> lc_trk_g3_6 +(25 15) routing sp4_v_b_38 <X> lc_trk_g3_6 +(25 15) routing tnl_op_6 <X> lc_trk_g3_6 +(25 2) routing bnr_op_6 <X> lc_trk_g0_6 +(25 2) routing lft_op_6 <X> lc_trk_g0_6 +(25 2) routing sp12_h_l_5 <X> lc_trk_g0_6 +(25 2) routing sp4_h_l_11 <X> lc_trk_g0_6 +(25 2) routing sp4_h_l_3 <X> lc_trk_g0_6 +(25 2) routing sp4_v_b_14 <X> lc_trk_g0_6 +(25 2) routing sp4_v_b_6 <X> lc_trk_g0_6 +(25 3) routing bnr_op_6 <X> lc_trk_g0_6 +(25 3) routing sp12_h_l_5 <X> lc_trk_g0_6 +(25 3) routing sp12_h_r_22 <X> lc_trk_g0_6 +(25 3) routing sp4_h_l_11 <X> lc_trk_g0_6 +(25 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(25 3) routing sp4_r_v_b_30 <X> lc_trk_g0_6 +(25 3) routing sp4_v_b_14 <X> lc_trk_g0_6 +(25 4) routing bnr_op_2 <X> lc_trk_g1_2 +(25 4) routing lft_op_2 <X> lc_trk_g1_2 +(25 4) routing sp12_h_l_1 <X> lc_trk_g1_2 +(25 4) routing sp4_h_l_7 <X> lc_trk_g1_2 +(25 4) routing sp4_h_r_10 <X> lc_trk_g1_2 +(25 4) routing sp4_v_b_10 <X> lc_trk_g1_2 +(25 4) routing sp4_v_b_2 <X> lc_trk_g1_2 +(25 5) routing bnr_op_2 <X> lc_trk_g1_2 +(25 5) routing sp12_h_l_1 <X> lc_trk_g1_2 +(25 5) routing sp12_h_l_17 <X> lc_trk_g1_2 +(25 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(25 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(25 5) routing sp4_r_v_b_26 <X> lc_trk_g1_2 +(25 5) routing sp4_v_b_10 <X> lc_trk_g1_2 +(25 6) routing bnr_op_6 <X> lc_trk_g1_6 +(25 6) routing lft_op_6 <X> lc_trk_g1_6 +(25 6) routing sp12_h_l_5 <X> lc_trk_g1_6 +(25 6) routing sp4_h_l_11 <X> lc_trk_g1_6 +(25 6) routing sp4_h_l_3 <X> lc_trk_g1_6 +(25 6) routing sp4_v_b_14 <X> lc_trk_g1_6 +(25 6) routing sp4_v_b_6 <X> lc_trk_g1_6 +(25 7) routing bnr_op_6 <X> lc_trk_g1_6 +(25 7) routing sp12_h_l_5 <X> lc_trk_g1_6 +(25 7) routing sp12_h_r_22 <X> lc_trk_g1_6 +(25 7) routing sp4_h_l_11 <X> lc_trk_g1_6 +(25 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6 +(25 7) routing sp4_v_b_14 <X> lc_trk_g1_6 +(25 8) routing bnl_op_2 <X> lc_trk_g2_2 +(25 8) routing rgt_op_2 <X> lc_trk_g2_2 +(25 8) routing sp12_v_b_2 <X> lc_trk_g2_2 +(25 8) routing sp4_h_l_23 <X> lc_trk_g2_2 +(25 8) routing sp4_h_l_31 <X> lc_trk_g2_2 +(25 8) routing sp4_v_t_15 <X> lc_trk_g2_2 +(25 8) routing sp4_v_t_23 <X> lc_trk_g2_2 +(25 9) routing bnl_op_2 <X> lc_trk_g2_2 +(25 9) routing sp12_v_b_2 <X> lc_trk_g2_2 +(25 9) routing sp12_v_t_17 <X> lc_trk_g2_2 +(25 9) routing sp4_h_l_31 <X> lc_trk_g2_2 +(25 9) routing sp4_h_r_26 <X> lc_trk_g2_2 +(25 9) routing sp4_r_v_b_34 <X> lc_trk_g2_2 +(25 9) routing sp4_v_t_23 <X> lc_trk_g2_2 +(25 9) routing tnl_op_2 <X> lc_trk_g2_2 +(26 0) routing lc_trk_g0_4 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g0_6 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_5 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_7 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_4 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_6 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_5 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_2 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_6 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_3 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_7 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_2 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_6 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_3 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(26 2) routing lc_trk_g0_5 <X> wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g0_7 <X> wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g1_4 <X> wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g1_6 <X> wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g2_5 <X> wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g2_7 <X> wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g3_4 <X> wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g3_6 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g0_3 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g0_7 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g1_2 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g1_6 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g2_3 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g2_7 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g3_2 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g3_6 <X> wire_mult/lc_1/in_0 +(26 4) routing lc_trk_g0_4 <X> wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g0_6 <X> wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g1_5 <X> wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g1_7 <X> wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g2_4 <X> wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g2_6 <X> wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g3_5 <X> wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g3_7 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g0_2 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g0_6 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g1_3 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g1_7 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g2_2 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g2_6 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g3_3 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g3_7 <X> wire_mult/lc_2/in_0 +(26 6) routing lc_trk_g0_5 <X> wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g0_7 <X> wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g1_4 <X> wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g1_6 <X> wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g2_5 <X> wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g2_7 <X> wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g3_4 <X> wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g3_6 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g0_3 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g0_7 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g1_2 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g1_6 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g2_3 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g2_7 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g3_2 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g3_6 <X> wire_mult/lc_3/in_0 +(26 8) routing lc_trk_g0_4 <X> wire_mult/lc_4/in_0 +(26 8) routing lc_trk_g0_6 <X> wire_mult/lc_4/in_0 +(26 8) routing lc_trk_g1_5 <X> wire_mult/lc_4/in_0 +(26 8) routing lc_trk_g1_7 <X> wire_mult/lc_4/in_0 +(26 8) routing lc_trk_g2_4 <X> wire_mult/lc_4/in_0 +(26 8) routing lc_trk_g2_6 <X> wire_mult/lc_4/in_0 +(26 8) routing lc_trk_g3_5 <X> wire_mult/lc_4/in_0 +(26 8) routing lc_trk_g3_7 <X> wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g0_2 <X> wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g0_6 <X> wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g1_3 <X> wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g1_7 <X> wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g2_2 <X> wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g2_6 <X> wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g3_3 <X> wire_mult/lc_4/in_0 +(26 9) routing lc_trk_g3_7 <X> wire_mult/lc_4/in_0 +(27 0) routing lc_trk_g1_0 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(27 1) routing lc_trk_g1_1 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_3 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_5 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_7 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_1 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_3 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_5 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(27 10) routing lc_trk_g1_1 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(27 12) routing lc_trk_g1_0 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(27 14) routing lc_trk_g1_1 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(27 2) routing lc_trk_g1_1 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(27 3) routing lc_trk_g1_0 <X> wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g1_2 <X> wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g1_4 <X> wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g1_6 <X> wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_0 <X> wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_2 <X> wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_4 <X> wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_6 <X> wire_mult/lc_1/in_0 +(27 4) routing lc_trk_g1_0 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(27 5) routing lc_trk_g1_1 <X> wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g1_3 <X> wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g1_5 <X> wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g1_7 <X> wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_1 <X> wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_3 <X> wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_5 <X> wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_7 <X> wire_mult/lc_2/in_0 +(27 6) routing lc_trk_g1_1 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(27 7) routing lc_trk_g1_0 <X> wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g1_2 <X> wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g1_4 <X> wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g1_6 <X> wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_0 <X> wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_2 <X> wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_4 <X> wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_6 <X> wire_mult/lc_3/in_0 +(27 8) routing lc_trk_g1_0 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(27 9) routing lc_trk_g1_1 <X> wire_mult/lc_4/in_0 +(27 9) routing lc_trk_g1_3 <X> wire_mult/lc_4/in_0 +(27 9) routing lc_trk_g1_5 <X> wire_mult/lc_4/in_0 +(27 9) routing lc_trk_g1_7 <X> wire_mult/lc_4/in_0 +(27 9) routing lc_trk_g3_1 <X> wire_mult/lc_4/in_0 +(27 9) routing lc_trk_g3_3 <X> wire_mult/lc_4/in_0 +(27 9) routing lc_trk_g3_5 <X> wire_mult/lc_4/in_0 +(27 9) routing lc_trk_g3_7 <X> wire_mult/lc_4/in_0 +(28 0) routing lc_trk_g2_1 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(28 1) routing lc_trk_g2_0 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_2 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_4 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_6 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_1 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_3 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_5 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(28 10) routing lc_trk_g2_0 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(28 12) routing lc_trk_g2_1 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(28 14) routing lc_trk_g2_0 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(28 2) routing lc_trk_g2_0 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(28 3) routing lc_trk_g2_1 <X> wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g2_3 <X> wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g2_5 <X> wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g2_7 <X> wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_0 <X> wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_2 <X> wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_4 <X> wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_6 <X> wire_mult/lc_1/in_0 +(28 4) routing lc_trk_g2_1 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(28 5) routing lc_trk_g2_0 <X> wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g2_2 <X> wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g2_4 <X> wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g2_6 <X> wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_1 <X> wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_3 <X> wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_5 <X> wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_7 <X> wire_mult/lc_2/in_0 +(28 6) routing lc_trk_g2_0 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(28 7) routing lc_trk_g2_1 <X> wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g2_3 <X> wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g2_5 <X> wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g2_7 <X> wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_0 <X> wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_2 <X> wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_4 <X> wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_6 <X> wire_mult/lc_3/in_0 +(28 8) routing lc_trk_g2_1 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(28 9) routing lc_trk_g2_0 <X> wire_mult/lc_4/in_0 +(28 9) routing lc_trk_g2_2 <X> wire_mult/lc_4/in_0 +(28 9) routing lc_trk_g2_4 <X> wire_mult/lc_4/in_0 +(28 9) routing lc_trk_g2_6 <X> wire_mult/lc_4/in_0 +(28 9) routing lc_trk_g3_1 <X> wire_mult/lc_4/in_0 +(28 9) routing lc_trk_g3_3 <X> wire_mult/lc_4/in_0 +(28 9) routing lc_trk_g3_5 <X> wire_mult/lc_4/in_0 +(28 9) routing lc_trk_g3_7 <X> wire_mult/lc_4/in_0 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_6 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_6 wire_mult/lc_0/in_1 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_7 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_7 wire_mult/lc_0/in_0 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_7 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_7 wire_mult/lc_5/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_6 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_6 wire_mult/lc_6/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_7 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_7 wire_mult/lc_7/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_7 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_7 wire_mult/lc_1/in_1 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_1 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_3 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_5 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_7 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_0 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_2 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_4 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_6 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_1 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_3 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_5 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_7 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_0 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_2 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_4 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_6 wire_mult/lc_1/in_0 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_6 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_6 wire_mult/lc_2/in_1 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_0 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_2 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_4 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_6 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_1 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_3 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_5 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_7 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_0 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_2 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_4 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_6 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_1 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_3 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_5 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_7 wire_mult/lc_2/in_0 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_7 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_7 wire_mult/lc_3/in_1 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_1 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_3 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_5 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_7 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_0 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_2 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_4 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_6 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_1 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_3 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_5 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_7 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_0 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_2 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_4 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_6 wire_mult/lc_3/in_0 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_6 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_6 wire_mult/lc_4/in_1 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g0_0 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g0_2 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g0_4 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g0_6 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g1_1 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g1_3 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g1_5 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g1_7 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g2_0 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g2_2 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g2_4 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g2_6 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g3_1 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g3_3 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g3_5 wire_mult/lc_4/in_0 +(29 9) Enable bit of Mux _mult/lcb0_4 => lc_trk_g3_7 wire_mult/lc_4/in_0 +(3 0) routing sp12_h_r_0 <X> sp12_v_b_0 +(3 0) routing sp12_v_t_23 <X> sp12_v_b_0 +(3 1) routing sp12_h_l_23 <X> sp12_v_b_0 +(3 1) routing sp12_h_r_0 <X> sp12_v_b_0 +(3 10) routing sp12_v_t_22 <X> sp12_h_l_22 +(3 11) routing sp12_v_b_1 <X> sp12_h_l_22 +(3 12) routing sp12_v_b_1 <X> sp12_h_r_1 +(3 12) routing sp12_v_t_22 <X> sp12_h_r_1 +(3 13) routing sp12_h_l_22 <X> sp12_h_r_1 +(3 13) routing sp12_v_b_1 <X> sp12_h_r_1 +(3 14) routing sp12_h_r_1 <X> sp12_v_t_22 +(3 14) routing sp12_v_b_1 <X> sp12_v_t_22 +(3 15) routing sp12_h_l_22 <X> sp12_v_t_22 +(3 15) routing sp12_h_r_1 <X> sp12_v_t_22 +(3 2) routing sp12_h_r_0 <X> sp12_h_l_23 +(3 2) routing sp12_v_t_23 <X> sp12_h_l_23 +(3 3) routing sp12_h_r_0 <X> sp12_h_l_23 +(3 3) routing sp12_v_b_0 <X> sp12_h_l_23 +(3 4) routing sp12_v_b_0 <X> sp12_h_r_0 +(3 4) routing sp12_v_t_23 <X> sp12_h_r_0 +(3 5) routing sp12_h_l_23 <X> sp12_h_r_0 +(3 5) routing sp12_v_b_0 <X> sp12_h_r_0 +(3 6) routing sp12_h_r_0 <X> sp12_v_t_23 +(3 6) routing sp12_v_b_0 <X> sp12_v_t_23 +(3 7) routing sp12_h_l_23 <X> sp12_v_t_23 +(3 7) routing sp12_h_r_0 <X> sp12_v_t_23 +(3 8) routing sp12_h_r_1 <X> sp12_v_b_1 +(3 8) routing sp12_v_t_22 <X> sp12_v_b_1 +(3 9) routing sp12_h_l_22 <X> sp12_v_b_1 +(3 9) routing sp12_h_r_1 <X> sp12_v_b_1 +(30 0) routing lc_trk_g0_5 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_3 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(30 10) routing lc_trk_g0_4 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_2 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(30 12) routing lc_trk_g0_5 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_3 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(30 14) routing lc_trk_g0_4 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_2 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(30 2) routing lc_trk_g0_4 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_2 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(30 4) routing lc_trk_g0_5 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_3 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(30 6) routing lc_trk_g0_4 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_2 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(30 8) routing lc_trk_g0_5 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_3 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(31 0) routing lc_trk_g0_5 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_3 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(31 10) routing lc_trk_g0_4 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_2 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(31 12) routing lc_trk_g0_5 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_3 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(31 14) routing lc_trk_g0_4 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_2 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(31 2) routing lc_trk_g0_4 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_2 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(31 4) routing lc_trk_g0_5 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_3 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(31 6) routing lc_trk_g0_4 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_2 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(31 8) routing lc_trk_g0_5 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_3 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_6 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_1 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_6 wire_mult/lc_0/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_7 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_0 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_7 wire_mult/lc_5/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_6 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_1 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_6 wire_mult/lc_6/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_7 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_0 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_7 wire_mult/lc_7/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_7 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_0 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_7 wire_mult/lc_1/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_6 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_1 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_6 wire_mult/lc_2/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_7 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_0 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_7 wire_mult/lc_3/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_6 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_1 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_6 wire_mult/lc_4/in_3 +(33 0) routing lc_trk_g2_1 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(33 10) routing lc_trk_g2_0 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(33 12) routing lc_trk_g2_1 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(33 14) routing lc_trk_g2_0 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(33 2) routing lc_trk_g2_0 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(33 4) routing lc_trk_g2_1 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(33 6) routing lc_trk_g2_0 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(33 8) routing lc_trk_g2_1 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(34 0) routing lc_trk_g1_0 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(34 10) routing lc_trk_g1_1 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(34 12) routing lc_trk_g1_0 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(34 14) routing lc_trk_g1_1 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(34 2) routing lc_trk_g1_1 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(34 4) routing lc_trk_g1_0 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(34 6) routing lc_trk_g1_1 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(34 8) routing lc_trk_g1_0 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(36 0) LC_0 Logic Functioning bit +(36 1) LC_0 Logic Functioning bit +(36 10) LC_5 Logic Functioning bit +(36 11) LC_5 Logic Functioning bit +(36 12) LC_6 Logic Functioning bit +(36 13) LC_6 Logic Functioning bit +(36 14) LC_7 Logic Functioning bit +(36 15) LC_7 Logic Functioning bit +(36 2) LC_1 Logic Functioning bit +(36 3) LC_1 Logic Functioning bit +(36 4) LC_2 Logic Functioning bit +(36 5) LC_2 Logic Functioning bit +(36 6) LC_3 Logic Functioning bit +(36 7) LC_3 Logic Functioning bit +(36 8) LC_4 Logic Functioning bit +(36 9) LC_4 Logic Functioning bit +(37 0) LC_0 Logic Functioning bit +(37 1) LC_0 Logic Functioning bit +(37 10) LC_5 Logic Functioning bit +(37 11) LC_5 Logic Functioning bit +(37 12) LC_6 Logic Functioning bit +(37 13) LC_6 Logic Functioning bit +(37 14) LC_7 Logic Functioning bit +(37 15) LC_7 Logic Functioning bit +(37 2) LC_1 Logic Functioning bit +(37 3) LC_1 Logic Functioning bit +(37 4) LC_2 Logic Functioning bit +(37 5) LC_2 Logic Functioning bit +(37 6) LC_3 Logic Functioning bit +(37 7) LC_3 Logic Functioning bit +(37 8) LC_4 Logic Functioning bit +(37 9) LC_4 Logic Functioning bit +(4 0) routing sp4_h_l_37 <X> sp4_v_b_0 +(4 0) routing sp4_h_l_43 <X> sp4_v_b_0 +(4 0) routing sp4_v_t_37 <X> sp4_v_b_0 +(4 0) routing sp4_v_t_41 <X> sp4_v_b_0 +(4 1) routing sp4_h_l_41 <X> sp4_h_r_0 +(4 1) routing sp4_v_b_6 <X> sp4_h_r_0 +(4 1) routing sp4_v_t_42 <X> sp4_h_r_0 +(4 10) routing sp4_h_r_0 <X> sp4_v_t_43 +(4 10) routing sp4_h_r_6 <X> sp4_v_t_43 +(4 10) routing sp4_v_b_10 <X> sp4_v_t_43 +(4 10) routing sp4_v_b_6 <X> sp4_v_t_43 +(4 11) routing sp4_h_r_10 <X> sp4_h_l_43 +(4 11) routing sp4_v_b_1 <X> sp4_h_l_43 +(4 11) routing sp4_v_t_37 <X> sp4_h_l_43 +(4 12) routing sp4_h_l_38 <X> sp4_v_b_9 +(4 12) routing sp4_h_l_44 <X> sp4_v_b_9 +(4 12) routing sp4_v_t_36 <X> sp4_v_b_9 +(4 12) routing sp4_v_t_44 <X> sp4_v_b_9 +(4 13) routing sp4_v_b_3 <X> sp4_h_r_9 +(4 13) routing sp4_v_t_41 <X> sp4_h_r_9 +(4 14) routing sp4_h_r_3 <X> sp4_v_t_44 +(4 14) routing sp4_h_r_9 <X> sp4_v_t_44 +(4 14) routing sp4_v_b_1 <X> sp4_v_t_44 +(4 14) routing sp4_v_b_9 <X> sp4_v_t_44 +(4 15) routing sp4_h_r_6 <X> sp4_h_l_44 +(4 15) routing sp4_v_b_4 <X> sp4_h_l_44 +(4 15) routing sp4_v_t_38 <X> sp4_h_l_44 +(4 2) routing sp4_h_r_0 <X> sp4_v_t_37 +(4 2) routing sp4_h_r_6 <X> sp4_v_t_37 +(4 2) routing sp4_v_b_0 <X> sp4_v_t_37 +(4 2) routing sp4_v_b_4 <X> sp4_v_t_37 +(4 3) routing sp4_h_r_4 <X> sp4_h_l_37 +(4 3) routing sp4_h_r_9 <X> sp4_h_l_37 +(4 3) routing sp4_v_b_7 <X> sp4_h_l_37 +(4 3) routing sp4_v_t_43 <X> sp4_h_l_37 +(4 4) routing sp4_h_l_38 <X> sp4_v_b_3 +(4 4) routing sp4_h_l_44 <X> sp4_v_b_3 +(4 4) routing sp4_v_t_38 <X> sp4_v_b_3 +(4 4) routing sp4_v_t_42 <X> sp4_v_b_3 +(4 5) routing sp4_h_l_37 <X> sp4_h_r_3 +(4 5) routing sp4_h_l_42 <X> sp4_h_r_3 +(4 5) routing sp4_v_b_9 <X> sp4_h_r_3 +(4 5) routing sp4_v_t_47 <X> sp4_h_r_3 +(4 6) routing sp4_h_r_3 <X> sp4_v_t_38 +(4 6) routing sp4_h_r_9 <X> sp4_v_t_38 +(4 6) routing sp4_v_b_3 <X> sp4_v_t_38 +(4 6) routing sp4_v_b_7 <X> sp4_v_t_38 +(4 7) routing sp4_h_r_0 <X> sp4_h_l_38 +(4 7) routing sp4_v_b_10 <X> sp4_h_l_38 +(4 7) routing sp4_v_t_44 <X> sp4_h_l_38 +(4 8) routing sp4_h_l_37 <X> sp4_v_b_6 +(4 8) routing sp4_h_l_43 <X> sp4_v_b_6 +(4 8) routing sp4_v_t_43 <X> sp4_v_b_6 +(4 8) routing sp4_v_t_47 <X> sp4_v_b_6 +(4 9) routing sp4_h_l_38 <X> sp4_h_r_6 +(4 9) routing sp4_h_l_47 <X> sp4_h_r_6 +(4 9) routing sp4_v_b_0 <X> sp4_h_r_6 +(4 9) routing sp4_v_t_36 <X> sp4_h_r_6 +(42 0) LC_0 Logic Functioning bit +(42 1) LC_0 Logic Functioning bit +(42 10) LC_5 Logic Functioning bit +(42 11) LC_5 Logic Functioning bit +(42 12) LC_6 Logic Functioning bit +(42 13) LC_6 Logic Functioning bit +(42 14) LC_7 Logic Functioning bit +(42 15) LC_7 Logic Functioning bit +(42 2) LC_1 Logic Functioning bit +(42 3) LC_1 Logic Functioning bit +(42 4) LC_2 Logic Functioning bit +(42 5) LC_2 Logic Functioning bit +(42 6) LC_3 Logic Functioning bit +(42 7) LC_3 Logic Functioning bit +(42 8) LC_4 Logic Functioning bit +(42 9) LC_4 Logic Functioning bit +(43 0) LC_0 Logic Functioning bit +(43 1) LC_0 Logic Functioning bit +(43 10) LC_5 Logic Functioning bit +(43 11) LC_5 Logic Functioning bit +(43 12) LC_6 Logic Functioning bit +(43 13) LC_6 Logic Functioning bit +(43 14) LC_7 Logic Functioning bit +(43 15) LC_7 Logic Functioning bit +(43 2) LC_1 Logic Functioning bit +(43 3) LC_1 Logic Functioning bit +(43 4) LC_2 Logic Functioning bit +(43 5) LC_2 Logic Functioning bit +(43 6) LC_3 Logic Functioning bit +(43 7) LC_3 Logic Functioning bit +(43 8) LC_4 Logic Functioning bit +(43 9) LC_4 Logic Functioning bit +(46 0) Enable bit of Mux _out_links/OutMux7_0 => wire_mult/mult/O_0 sp4_h_l_5 +(46 1) Enable bit of Mux _out_links/OutMux6_0 => wire_mult/mult/O_0 sp4_h_r_0 +(46 10) Enable bit of Mux _out_links/OutMux7_5 => wire_mult/mult/O_5 sp4_h_r_26 +(46 11) Enable bit of Mux _out_links/OutMux6_5 => wire_mult/mult/O_5 sp4_h_r_10 +(46 12) Enable bit of Mux _out_links/OutMux7_6 => wire_mult/mult/O_6 sp4_h_l_17 +(46 13) Enable bit of Mux _out_links/OutMux6_6 => wire_mult/mult/O_6 sp4_h_r_12 +(46 14) Enable bit of Mux _out_links/OutMux7_7 => wire_mult/mult/O_7 sp4_h_r_30 +(46 15) Enable bit of Mux _out_links/OutMux6_7 => wire_mult/mult/O_7 sp4_h_l_3 +(46 2) Enable bit of Mux _out_links/OutMux7_1 => wire_mult/mult/O_1 sp4_h_l_7 +(46 3) Enable bit of Mux _out_links/OutMux6_1 => wire_mult/mult/O_1 sp4_h_r_2 +(46 4) Enable bit of Mux _out_links/OutMux7_2 => wire_mult/mult/O_2 sp4_h_r_20 +(46 5) Enable bit of Mux _out_links/OutMux6_2 => wire_mult/mult/O_2 sp4_h_r_4 +(46 6) Enable bit of Mux _out_links/OutMux7_3 => wire_mult/mult/O_3 sp4_h_l_11 +(46 7) Enable bit of Mux _out_links/OutMux6_3 => wire_mult/mult/O_3 sp4_h_r_6 +(46 8) Enable bit of Mux _out_links/OutMux7_4 => wire_mult/mult/O_4 sp4_h_l_13 +(46 9) Enable bit of Mux _out_links/OutMux6_4 => wire_mult/mult/O_4 sp4_h_r_8 +(47 0) Enable bit of Mux _out_links/OutMux5_0 => wire_mult/mult/O_0 sp12_h_l_7 +(47 1) Enable bit of Mux _out_links/OutMux8_0 => wire_mult/mult/O_0 sp4_h_r_32 +(47 10) Enable bit of Mux _out_links/OutMux4_5 => wire_mult/mult/O_5 sp12_h_l_1 +(47 11) Enable bit of Mux _out_links/OutMux8_5 => wire_mult/mult/O_5 sp4_h_l_31 +(47 12) Enable bit of Mux _out_links/OutMux4_6 => wire_mult/mult/O_6 sp12_h_l_3 +(47 13) Enable bit of Mux _out_links/OutMux8_6 => wire_mult/mult/O_6 sp4_h_l_33 +(47 14) Enable bit of Mux _out_links/OutMux4_7 => wire_mult/mult/O_7 sp12_h_l_5 +(47 15) Enable bit of Mux _out_links/OutMux8_7 => wire_mult/mult/O_7 sp4_h_l_35 +(47 2) Enable bit of Mux _out_links/OutMux5_1 => wire_mult/mult/O_1 sp12_h_l_9 +(47 3) Enable bit of Mux _out_links/OutMux8_1 => wire_mult/mult/O_1 sp4_h_l_23 +(47 4) Enable bit of Mux _out_links/OutMux5_2 => wire_mult/mult/O_2 sp12_h_r_12 +(47 5) Enable bit of Mux _out_links/OutMux8_2 => wire_mult/mult/O_2 sp4_h_r_36 +(47 6) Enable bit of Mux _out_links/OutMux5_3 => wire_mult/mult/O_3 sp12_h_r_14 +(47 7) Enable bit of Mux _out_links/OutMux8_3 => wire_mult/mult/O_3 sp4_h_r_38 +(47 8) Enable bit of Mux _out_links/OutMux4_4 => wire_mult/mult/O_4 sp12_h_r_0 +(47 9) Enable bit of Mux _out_links/OutMux8_4 => wire_mult/mult/O_4 sp4_h_l_29 +(48 0) Enable bit of Mux _out_links/OutMux0_0 => wire_mult/mult/O_0 sp4_v_b_0 +(48 1) Enable bit of Mux _out_links/OutMux1_0 => wire_mult/mult/O_0 sp4_v_b_16 +(48 10) Enable bit of Mux _out_links/OutMux5_5 => wire_mult/mult/O_5 sp12_h_l_17 +(48 11) Enable bit of Mux _out_links/OutMux0_5 => wire_mult/mult/O_5 sp4_v_b_10 +(48 12) Enable bit of Mux _out_links/OutMux5_6 => wire_mult/mult/O_6 sp12_h_l_19 +(48 13) Enable bit of Mux _out_links/OutMux0_6 => wire_mult/mult/O_6 sp4_v_t_1 +(48 14) Enable bit of Mux _out_links/OutMux5_7 => wire_mult/mult/O_7 sp12_h_r_22 +(48 15) Enable bit of Mux _out_links/OutMux0_7 => wire_mult/mult/O_7 sp4_v_b_14 +(48 2) Enable bit of Mux _out_links/OutMux0_1 => wire_mult/mult/O_1 sp4_v_b_2 +(48 3) Enable bit of Mux _out_links/OutMux1_1 => wire_mult/mult/O_1 sp4_v_b_18 +(48 4) Enable bit of Mux _out_links/OutMux0_2 => wire_mult/mult/O_2 sp4_v_b_4 +(48 5) Enable bit of Mux _out_links/OutMux1_2 => wire_mult/mult/O_2 sp4_v_b_20 +(48 6) Enable bit of Mux _out_links/OutMux0_3 => wire_mult/mult/O_3 sp4_v_b_6 +(48 7) Enable bit of Mux _out_links/OutMux1_3 => wire_mult/mult/O_3 sp4_v_t_11 +(48 8) Enable bit of Mux _out_links/OutMux5_4 => wire_mult/mult/O_4 sp12_h_l_15 +(48 9) Enable bit of Mux _out_links/OutMux0_4 => wire_mult/mult/O_4 sp4_v_b_8 +(5 0) routing sp4_v_b_0 <X> sp4_h_r_0 +(5 0) routing sp4_v_b_6 <X> sp4_h_r_0 +(5 0) routing sp4_v_t_37 <X> sp4_h_r_0 +(5 1) routing sp4_h_l_37 <X> sp4_v_b_0 +(5 1) routing sp4_h_l_43 <X> sp4_v_b_0 +(5 1) routing sp4_h_r_0 <X> sp4_v_b_0 +(5 1) routing sp4_v_t_44 <X> sp4_v_b_0 +(5 10) routing sp4_v_b_6 <X> sp4_h_l_43 +(5 10) routing sp4_v_t_37 <X> sp4_h_l_43 +(5 10) routing sp4_v_t_43 <X> sp4_h_l_43 +(5 11) routing sp4_h_l_43 <X> sp4_v_t_43 +(5 11) routing sp4_h_r_0 <X> sp4_v_t_43 +(5 11) routing sp4_h_r_6 <X> sp4_v_t_43 +(5 11) routing sp4_v_b_3 <X> sp4_v_t_43 +(5 12) routing sp4_v_b_3 <X> sp4_h_r_9 +(5 12) routing sp4_v_b_9 <X> sp4_h_r_9 +(5 12) routing sp4_v_t_44 <X> sp4_h_r_9 +(5 13) routing sp4_h_l_38 <X> sp4_v_b_9 +(5 13) routing sp4_h_l_44 <X> sp4_v_b_9 +(5 13) routing sp4_h_r_9 <X> sp4_v_b_9 +(5 13) routing sp4_v_t_43 <X> sp4_v_b_9 +(5 14) routing sp4_h_r_6 <X> sp4_h_l_44 +(5 14) routing sp4_v_b_9 <X> sp4_h_l_44 +(5 14) routing sp4_v_t_38 <X> sp4_h_l_44 +(5 14) routing sp4_v_t_44 <X> sp4_h_l_44 +(5 15) routing sp4_h_l_44 <X> sp4_v_t_44 +(5 15) routing sp4_h_r_3 <X> sp4_v_t_44 +(5 15) routing sp4_h_r_9 <X> sp4_v_t_44 +(5 15) routing sp4_v_b_6 <X> sp4_v_t_44 +(5 2) routing sp4_h_r_9 <X> sp4_h_l_37 +(5 2) routing sp4_v_b_0 <X> sp4_h_l_37 +(5 2) routing sp4_v_t_37 <X> sp4_h_l_37 +(5 2) routing sp4_v_t_43 <X> sp4_h_l_37 +(5 3) routing sp4_h_l_37 <X> sp4_v_t_37 +(5 3) routing sp4_h_r_0 <X> sp4_v_t_37 +(5 3) routing sp4_h_r_6 <X> sp4_v_t_37 +(5 3) routing sp4_v_b_9 <X> sp4_v_t_37 +(5 4) routing sp4_h_l_37 <X> sp4_h_r_3 +(5 4) routing sp4_v_b_3 <X> sp4_h_r_3 +(5 4) routing sp4_v_b_9 <X> sp4_h_r_3 +(5 4) routing sp4_v_t_38 <X> sp4_h_r_3 +(5 5) routing sp4_h_l_38 <X> sp4_v_b_3 +(5 5) routing sp4_h_l_44 <X> sp4_v_b_3 +(5 5) routing sp4_h_r_3 <X> sp4_v_b_3 +(5 5) routing sp4_v_t_37 <X> sp4_v_b_3 +(5 6) routing sp4_h_r_0 <X> sp4_h_l_38 +(5 6) routing sp4_v_b_3 <X> sp4_h_l_38 +(5 6) routing sp4_v_t_38 <X> sp4_h_l_38 +(5 6) routing sp4_v_t_44 <X> sp4_h_l_38 +(5 7) routing sp4_h_l_38 <X> sp4_v_t_38 +(5 7) routing sp4_h_r_3 <X> sp4_v_t_38 +(5 7) routing sp4_h_r_9 <X> sp4_v_t_38 +(5 7) routing sp4_v_b_0 <X> sp4_v_t_38 +(5 8) routing sp4_h_l_38 <X> sp4_h_r_6 +(5 8) routing sp4_v_b_0 <X> sp4_h_r_6 +(5 8) routing sp4_v_b_6 <X> sp4_h_r_6 +(5 8) routing sp4_v_t_43 <X> sp4_h_r_6 +(5 9) routing sp4_h_l_37 <X> sp4_v_b_6 +(5 9) routing sp4_h_l_43 <X> sp4_v_b_6 +(5 9) routing sp4_h_r_6 <X> sp4_v_b_6 +(5 9) routing sp4_v_t_38 <X> sp4_v_b_6 +(50 0) Cascade buffer Enable bit: MULT0_LC00_inmux02_5 +(50 10) Cascade buffer Enable bit: MULT0_LC05_inmux02_5 +(50 12) Cascade buffer Enable bit: MULT0_LC06_inmux02_5 +(50 14) Cascade buffer Enable bit: MULT0_LC07_inmux02_5 +(50 2) Cascade buffer Enable bit: MULT0_LC01_inmux02_5 +(50 4) Cascade buffer Enable bit: MULT0_LC02_inmux02_5 +(50 6) Cascade buffer Enable bit: MULT0_LC03_inmux02_5 +(50 8) Cascade buffer Enable bit: MULT0_LC04_inmux02_5 +(51 0) Enable bit of Mux _out_links/OutMux3_0 => wire_mult/mult/O_0 sp12_v_b_0 +(51 1) Enable bit of Mux _out_links/OutMux2_0 => wire_mult/mult/O_0 sp4_v_t_21 +(51 10) Enable bit of Mux _out_links/OutMux2_5 => wire_mult/mult/O_5 sp4_v_t_31 +(51 11) Enable bit of Mux _out_links/OutMux1_5 => wire_mult/mult/O_5 sp4_v_t_15 +(51 12) Enable bit of Mux _out_links/OutMux2_6 => wire_mult/mult/O_6 sp4_v_b_44 +(51 13) Enable bit of Mux _out_links/OutMux1_6 => wire_mult/mult/O_6 sp4_v_b_28 +(51 14) Enable bit of Mux _out_links/OutMux2_7 => wire_mult/mult/O_7 sp4_v_b_46 +(51 15) Enable bit of Mux _out_links/OutMux1_7 => wire_mult/mult/O_7 sp4_v_b_30 +(51 2) Enable bit of Mux _out_links/OutMux3_1 => wire_mult/mult/O_1 sp12_v_b_2 +(51 3) Enable bit of Mux _out_links/OutMux2_1 => wire_mult/mult/O_1 sp4_v_t_23 +(51 4) Enable bit of Mux _out_links/OutMux3_2 => wire_mult/mult/O_2 sp12_v_b_4 +(51 5) Enable bit of Mux _out_links/OutMux2_2 => wire_mult/mult/O_2 sp4_v_b_36 +(51 6) Enable bit of Mux _out_links/OutMux3_3 => wire_mult/mult/O_3 sp12_v_b_6 +(51 7) Enable bit of Mux _out_links/OutMux2_3 => wire_mult/mult/O_3 sp4_v_b_38 +(51 8) Enable bit of Mux _out_links/OutMux2_4 => wire_mult/mult/O_4 sp4_v_t_29 +(51 9) Enable bit of Mux _out_links/OutMux1_4 => wire_mult/mult/O_4 sp4_v_b_24 +(52 0) Enable bit of Mux _out_links/OutMux4_0 => wire_mult/mult/O_0 sp12_v_t_15 +(52 1) Enable bit of Mux _out_links/OutMux9_0 => wire_mult/mult/O_0 sp4_r_v_b_1 +(52 10) Enable bit of Mux _out_links/OutMux3_5 => wire_mult/mult/O_5 sp12_v_b_10 +(52 11) Enable bit of Mux _out_links/OutMux9_5 => wire_mult/mult/O_5 sp4_r_v_b_11 +(52 12) Enable bit of Mux _out_links/OutMux3_6 => wire_mult/mult/O_6 sp12_v_t_11 +(52 13) Enable bit of Mux _out_links/OutMux9_6 => wire_mult/mult/O_6 sp4_r_v_b_13 +(52 14) Enable bit of Mux _out_links/OutMux3_7 => wire_mult/mult/O_7 sp12_v_t_13 +(52 15) Enable bit of Mux _out_links/OutMux9_7 => wire_mult/mult/O_7 sp4_r_v_b_15 +(52 2) Enable bit of Mux _out_links/OutMux4_1 => wire_mult/mult/O_1 sp12_v_t_17 +(52 3) Enable bit of Mux _out_links/OutMux9_1 => wire_mult/mult/O_1 sp4_r_v_b_3 +(52 4) Enable bit of Mux _out_links/OutMux4_2 => wire_mult/mult/O_2 sp12_v_b_20 +(52 5) Enable bit of Mux _out_links/OutMux9_2 => wire_mult/mult/O_2 sp4_r_v_b_5 +(52 6) Enable bit of Mux _out_links/OutMux4_3 => wire_mult/mult/O_3 sp12_v_t_21 +(52 7) Enable bit of Mux _out_links/OutMux9_3 => wire_mult/mult/O_3 sp4_r_v_b_7 +(52 8) Enable bit of Mux _out_links/OutMux3_4 => wire_mult/mult/O_4 sp12_v_b_8 +(52 9) Enable bit of Mux _out_links/OutMux9_4 => wire_mult/mult/O_4 sp4_r_v_b_9 +(53 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_mult/mult/O_0 sp4_r_v_b_17 +(53 1) Enable bit of Mux _out_links/OutMuxb_0 => wire_mult/mult/O_0 sp4_r_v_b_33 +(53 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_mult/mult/O_5 sp4_r_v_b_27 +(53 11) Enable bit of Mux _out_links/OutMuxb_5 => wire_mult/mult/O_5 sp4_r_v_b_43 +(53 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_mult/mult/O_6 sp4_r_v_b_29 +(53 13) Enable bit of Mux _out_links/OutMuxb_6 => wire_mult/mult/O_6 sp4_r_v_b_45 +(53 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_mult/mult/O_7 sp4_r_v_b_31 +(53 15) Enable bit of Mux _out_links/OutMuxb_7 => wire_mult/mult/O_7 sp4_r_v_b_47 +(53 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_mult/mult/O_1 sp4_r_v_b_19 +(53 3) Enable bit of Mux _out_links/OutMuxb_1 => wire_mult/mult/O_1 sp4_r_v_b_35 +(53 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_mult/mult/O_2 sp4_r_v_b_21 +(53 5) Enable bit of Mux _out_links/OutMuxb_2 => wire_mult/mult/O_2 sp4_r_v_b_37 +(53 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_mult/mult/O_3 sp4_r_v_b_23 +(53 7) Enable bit of Mux _out_links/OutMuxb_3 => wire_mult/mult/O_3 sp4_r_v_b_39 +(53 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_mult/mult/O_4 sp4_r_v_b_25 +(53 9) Enable bit of Mux _out_links/OutMuxb_4 => wire_mult/mult/O_4 sp4_r_v_b_41 +(6 0) routing sp4_h_l_43 <X> sp4_v_b_0 +(6 0) routing sp4_h_r_7 <X> sp4_v_b_0 +(6 0) routing sp4_v_t_41 <X> sp4_v_b_0 +(6 0) routing sp4_v_t_44 <X> sp4_v_b_0 +(6 1) routing sp4_h_l_41 <X> sp4_h_r_0 +(6 1) routing sp4_v_b_0 <X> sp4_h_r_0 +(6 1) routing sp4_v_b_6 <X> sp4_h_r_0 +(6 10) routing sp4_h_l_36 <X> sp4_v_t_43 +(6 10) routing sp4_h_r_0 <X> sp4_v_t_43 +(6 10) routing sp4_v_b_10 <X> sp4_v_t_43 +(6 10) routing sp4_v_b_3 <X> sp4_v_t_43 +(6 11) routing sp4_h_r_10 <X> sp4_h_l_43 +(6 11) routing sp4_h_r_6 <X> sp4_h_l_43 +(6 11) routing sp4_v_t_37 <X> sp4_h_l_43 +(6 11) routing sp4_v_t_43 <X> sp4_h_l_43 +(6 12) routing sp4_h_l_38 <X> sp4_v_b_9 +(6 12) routing sp4_h_r_4 <X> sp4_v_b_9 +(6 12) routing sp4_v_t_36 <X> sp4_v_b_9 +(6 12) routing sp4_v_t_43 <X> sp4_v_b_9 +(6 13) routing sp4_h_l_44 <X> sp4_h_r_9 +(6 13) routing sp4_v_b_3 <X> sp4_h_r_9 +(6 13) routing sp4_v_b_9 <X> sp4_h_r_9 +(6 14) routing sp4_h_l_41 <X> sp4_v_t_44 +(6 14) routing sp4_h_r_3 <X> sp4_v_t_44 +(6 14) routing sp4_v_b_1 <X> sp4_v_t_44 +(6 14) routing sp4_v_b_6 <X> sp4_v_t_44 +(6 15) routing sp4_v_t_38 <X> sp4_h_l_44 +(6 15) routing sp4_v_t_44 <X> sp4_h_l_44 +(6 2) routing sp4_h_l_42 <X> sp4_v_t_37 +(6 2) routing sp4_h_r_6 <X> sp4_v_t_37 +(6 2) routing sp4_v_b_4 <X> sp4_v_t_37 +(6 2) routing sp4_v_b_9 <X> sp4_v_t_37 +(6 3) routing sp4_h_r_0 <X> sp4_h_l_37 +(6 3) routing sp4_h_r_4 <X> sp4_h_l_37 +(6 3) routing sp4_v_t_37 <X> sp4_h_l_37 +(6 3) routing sp4_v_t_43 <X> sp4_h_l_37 +(6 4) routing sp4_h_l_44 <X> sp4_v_b_3 +(6 4) routing sp4_h_r_10 <X> sp4_v_b_3 +(6 4) routing sp4_v_t_37 <X> sp4_v_b_3 +(6 4) routing sp4_v_t_42 <X> sp4_v_b_3 +(6 5) routing sp4_h_l_38 <X> sp4_h_r_3 +(6 5) routing sp4_h_l_42 <X> sp4_h_r_3 +(6 5) routing sp4_v_b_3 <X> sp4_h_r_3 +(6 5) routing sp4_v_b_9 <X> sp4_h_r_3 +(6 6) routing sp4_h_l_47 <X> sp4_v_t_38 +(6 6) routing sp4_h_r_9 <X> sp4_v_t_38 +(6 6) routing sp4_v_b_0 <X> sp4_v_t_38 +(6 6) routing sp4_v_b_7 <X> sp4_v_t_38 +(6 7) routing sp4_h_r_3 <X> sp4_h_l_38 +(6 7) routing sp4_v_t_38 <X> sp4_h_l_38 +(6 7) routing sp4_v_t_44 <X> sp4_h_l_38 +(6 8) routing sp4_h_l_37 <X> sp4_v_b_6 +(6 8) routing sp4_h_r_1 <X> sp4_v_b_6 +(6 8) routing sp4_v_t_38 <X> sp4_v_b_6 +(6 8) routing sp4_v_t_47 <X> sp4_v_b_6 +(6 9) routing sp4_h_l_47 <X> sp4_h_r_6 +(6 9) routing sp4_v_b_0 <X> sp4_h_r_6 +(6 9) routing sp4_v_b_6 <X> sp4_h_r_6 +(7 0) MAC16 functional bit: MULT0_bram_cbit_1 +(7 1) MAC16 functional bit: MULT0_bram_cbit_0 +(7 10) Column buffer control bit: MULT0_colbuf_cntl_3 +(7 11) Column buffer control bit: MULT0_colbuf_cntl_2 +(7 12) Column buffer control bit: MULT0_colbuf_cntl_5 +(7 13) Column buffer control bit: MULT0_colbuf_cntl_4 +(7 14) Column buffer control bit: MULT0_colbuf_cntl_7 +(7 15) Column buffer control bit: MULT0_colbuf_cntl_6 +(7 2) MAC16 functional bit: MULT0_bram_cbit_3 +(7 3) MAC16 functional bit: MULT0_bram_cbit_2 +(7 4) MAC16 functional bit: MULT0_bram_cbit_5 +(7 5) MAC16 functional bit: MULT0_bram_cbit_4 +(7 6) MAC16 functional bit: MULT0_bram_cbit_7 +(7 7) MAC16 functional bit: MULT0_bram_cbit_6 +(7 8) Column buffer control bit: MULT0_colbuf_cntl_1 +(7 9) Column buffer control bit: MULT0_colbuf_cntl_0 +(8 0) routing sp4_h_l_40 <X> sp4_h_r_1 +(8 0) routing sp4_v_b_1 <X> sp4_h_r_1 +(8 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(8 1) routing sp4_h_l_36 <X> sp4_v_b_1 +(8 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(8 1) routing sp4_h_r_1 <X> sp4_v_b_1 +(8 1) routing sp4_v_t_47 <X> sp4_v_b_1 +(8 10) routing sp4_h_r_11 <X> sp4_h_l_42 +(8 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(8 10) routing sp4_v_t_42 <X> sp4_h_l_42 +(8 11) routing sp4_h_l_42 <X> sp4_v_t_42 +(8 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(8 11) routing sp4_h_r_7 <X> sp4_v_t_42 +(8 11) routing sp4_v_b_4 <X> sp4_v_t_42 +(8 12) routing sp4_h_l_39 <X> sp4_h_r_10 +(8 12) routing sp4_h_l_47 <X> sp4_h_r_10 +(8 12) routing sp4_v_b_10 <X> sp4_h_r_10 +(8 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(8 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(8 13) routing sp4_h_l_47 <X> sp4_v_b_10 +(8 13) routing sp4_h_r_10 <X> sp4_v_b_10 +(8 13) routing sp4_v_t_42 <X> sp4_v_b_10 +(8 14) routing sp4_h_r_2 <X> sp4_h_l_47 +(8 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(8 14) routing sp4_v_t_47 <X> sp4_h_l_47 +(8 15) routing sp4_h_l_47 <X> sp4_v_t_47 +(8 15) routing sp4_h_r_10 <X> sp4_v_t_47 +(8 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(8 15) routing sp4_v_b_7 <X> sp4_v_t_47 +(8 2) routing sp4_h_r_5 <X> sp4_h_l_36 +(8 2) routing sp4_v_t_36 <X> sp4_h_l_36 +(8 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(8 3) routing sp4_h_l_36 <X> sp4_v_t_36 +(8 3) routing sp4_h_r_1 <X> sp4_v_t_36 +(8 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(8 3) routing sp4_v_b_10 <X> sp4_v_t_36 +(8 4) routing sp4_h_l_41 <X> sp4_h_r_4 +(8 4) routing sp4_h_l_45 <X> sp4_h_r_4 +(8 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(8 4) routing sp4_v_b_4 <X> sp4_h_r_4 +(8 5) routing sp4_h_l_41 <X> sp4_v_b_4 +(8 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(8 5) routing sp4_h_r_4 <X> sp4_v_b_4 +(8 5) routing sp4_v_t_36 <X> sp4_v_b_4 +(8 6) routing sp4_h_r_4 <X> sp4_h_l_41 +(8 6) routing sp4_h_r_8 <X> sp4_h_l_41 +(8 6) routing sp4_v_t_41 <X> sp4_h_l_41 +(8 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(8 7) routing sp4_h_l_41 <X> sp4_v_t_41 +(8 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(8 7) routing sp4_h_r_4 <X> sp4_v_t_41 +(8 7) routing sp4_v_b_1 <X> sp4_v_t_41 +(8 8) routing sp4_h_l_42 <X> sp4_h_r_7 +(8 8) routing sp4_h_l_46 <X> sp4_h_r_7 +(8 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(8 8) routing sp4_v_b_7 <X> sp4_h_r_7 +(8 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(8 9) routing sp4_h_l_42 <X> sp4_v_b_7 +(8 9) routing sp4_h_r_7 <X> sp4_v_b_7 +(8 9) routing sp4_v_t_41 <X> sp4_v_b_7 +(9 0) routing sp4_h_l_47 <X> sp4_h_r_1 +(9 0) routing sp4_v_b_1 <X> sp4_h_r_1 +(9 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(9 0) routing sp4_v_t_36 <X> sp4_h_r_1 +(9 1) routing sp4_h_l_36 <X> sp4_v_b_1 +(9 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(9 1) routing sp4_v_t_36 <X> sp4_v_b_1 +(9 1) routing sp4_v_t_40 <X> sp4_v_b_1 +(9 10) routing sp4_h_r_4 <X> sp4_h_l_42 +(9 10) routing sp4_v_b_7 <X> sp4_h_l_42 +(9 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(9 10) routing sp4_v_t_42 <X> sp4_h_l_42 +(9 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(9 11) routing sp4_h_r_7 <X> sp4_v_t_42 +(9 11) routing sp4_v_b_11 <X> sp4_v_t_42 +(9 11) routing sp4_v_b_7 <X> sp4_v_t_42 +(9 12) routing sp4_h_l_42 <X> sp4_h_r_10 +(9 12) routing sp4_v_b_10 <X> sp4_h_r_10 +(9 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(9 12) routing sp4_v_t_47 <X> sp4_h_r_10 +(9 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(9 13) routing sp4_h_l_47 <X> sp4_v_b_10 +(9 13) routing sp4_v_t_39 <X> sp4_v_b_10 +(9 13) routing sp4_v_t_47 <X> sp4_v_b_10 +(9 14) routing sp4_h_r_7 <X> sp4_h_l_47 +(9 14) routing sp4_v_b_10 <X> sp4_h_l_47 +(9 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(9 14) routing sp4_v_t_47 <X> sp4_h_l_47 +(9 15) routing sp4_h_r_10 <X> sp4_v_t_47 +(9 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(9 15) routing sp4_v_b_10 <X> sp4_v_t_47 +(9 15) routing sp4_v_b_2 <X> sp4_v_t_47 +(9 2) routing sp4_h_r_10 <X> sp4_h_l_36 +(9 2) routing sp4_v_b_1 <X> sp4_h_l_36 +(9 2) routing sp4_v_t_36 <X> sp4_h_l_36 +(9 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(9 3) routing sp4_h_r_1 <X> sp4_v_t_36 +(9 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(9 3) routing sp4_v_b_1 <X> sp4_v_t_36 +(9 3) routing sp4_v_b_5 <X> sp4_v_t_36 +(9 4) routing sp4_h_l_36 <X> sp4_h_r_4 +(9 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(9 4) routing sp4_v_b_4 <X> sp4_h_r_4 +(9 4) routing sp4_v_t_41 <X> sp4_h_r_4 +(9 5) routing sp4_h_l_41 <X> sp4_v_b_4 +(9 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(9 5) routing sp4_v_t_41 <X> sp4_v_b_4 +(9 5) routing sp4_v_t_45 <X> sp4_v_b_4 +(9 6) routing sp4_v_b_4 <X> sp4_h_l_41 +(9 6) routing sp4_v_t_41 <X> sp4_h_l_41 +(9 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(9 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(9 7) routing sp4_h_r_4 <X> sp4_v_t_41 +(9 7) routing sp4_v_b_4 <X> sp4_v_t_41 +(9 7) routing sp4_v_b_8 <X> sp4_v_t_41 +(9 8) routing sp4_h_l_41 <X> sp4_h_r_7 +(9 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(9 8) routing sp4_v_b_7 <X> sp4_h_r_7 +(9 8) routing sp4_v_t_42 <X> sp4_h_r_7 +(9 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(9 9) routing sp4_h_l_42 <X> sp4_v_b_7 +(9 9) routing sp4_v_t_42 <X> sp4_v_b_7 +(9 9) routing sp4_v_t_46 <X> sp4_v_b_7 diff --git a/icefuzz/cached_dsp1_5k.txt b/icefuzz/cached_dsp1_5k.txt index e69de29..c844129 100644 --- a/icefuzz/cached_dsp1_5k.txt +++ b/icefuzz/cached_dsp1_5k.txt @@ -0,0 +1,3033 @@ +(0 10) routing glb_netwk_2 <X> glb2local_2 +(0 10) routing glb_netwk_3 <X> glb2local_2 +(0 10) routing glb_netwk_6 <X> glb2local_2 +(0 10) routing glb_netwk_7 <X> glb2local_2 +(0 11) routing glb_netwk_1 <X> glb2local_2 +(0 11) routing glb_netwk_3 <X> glb2local_2 +(0 11) routing glb_netwk_5 <X> glb2local_2 +(0 11) routing glb_netwk_7 <X> glb2local_2 +(0 12) routing glb_netwk_2 <X> glb2local_3 +(0 12) routing glb_netwk_3 <X> glb2local_3 +(0 12) routing glb_netwk_6 <X> glb2local_3 +(0 12) routing glb_netwk_7 <X> glb2local_3 +(0 13) routing glb_netwk_1 <X> glb2local_3 +(0 13) routing glb_netwk_3 <X> glb2local_3 +(0 13) routing glb_netwk_5 <X> glb2local_3 +(0 13) routing glb_netwk_7 <X> glb2local_3 +(0 14) routing glb_netwk_4 <X> wire_mult/lc_7/s_r +(0 14) routing glb_netwk_6 <X> wire_mult/lc_7/s_r +(0 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/s_r +(0 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/s_r +(0 15) routing glb_netwk_2 <X> wire_mult/lc_7/s_r +(0 15) routing glb_netwk_6 <X> wire_mult/lc_7/s_r +(0 15) routing lc_trk_g1_5 <X> wire_mult/lc_7/s_r +(0 15) routing lc_trk_g3_5 <X> wire_mult/lc_7/s_r +(0 6) routing glb_netwk_3 <X> glb2local_0 +(0 6) routing glb_netwk_6 <X> glb2local_0 +(0 6) routing glb_netwk_7 <X> glb2local_0 +(0 7) routing glb_netwk_1 <X> glb2local_0 +(0 7) routing glb_netwk_3 <X> glb2local_0 +(0 7) routing glb_netwk_5 <X> glb2local_0 +(0 7) routing glb_netwk_7 <X> glb2local_0 +(0 8) routing glb_netwk_3 <X> glb2local_1 +(0 8) routing glb_netwk_6 <X> glb2local_1 +(0 8) routing glb_netwk_7 <X> glb2local_1 +(0 9) routing glb_netwk_1 <X> glb2local_1 +(0 9) routing glb_netwk_3 <X> glb2local_1 +(0 9) routing glb_netwk_5 <X> glb2local_1 +(0 9) routing glb_netwk_7 <X> glb2local_1 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 +(1 11) routing glb_netwk_4 <X> glb2local_2 +(1 11) routing glb_netwk_5 <X> glb2local_2 +(1 11) routing glb_netwk_6 <X> glb2local_2 +(1 11) routing glb_netwk_7 <X> glb2local_2 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 +(1 13) routing glb_netwk_4 <X> glb2local_3 +(1 13) routing glb_netwk_5 <X> glb2local_3 +(1 13) routing glb_netwk_6 <X> glb2local_3 +(1 13) routing glb_netwk_7 <X> glb2local_3 +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g0_4 <X> wire_mult/lc_7/s_r +(1 15) routing lc_trk_g1_5 <X> wire_mult/lc_7/s_r +(1 15) routing lc_trk_g2_4 <X> wire_mult/lc_7/s_r +(1 15) routing lc_trk_g3_5 <X> wire_mult/lc_7/s_r +(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_l_4 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 +(1 7) routing glb_netwk_4 <X> glb2local_0 +(1 7) routing glb_netwk_5 <X> glb2local_0 +(1 7) routing glb_netwk_6 <X> glb2local_0 +(1 7) routing glb_netwk_7 <X> glb2local_0 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 +(1 9) routing glb_netwk_4 <X> glb2local_1 +(1 9) routing glb_netwk_5 <X> glb2local_1 +(1 9) routing glb_netwk_6 <X> glb2local_1 +(1 9) routing glb_netwk_7 <X> glb2local_1 +(10 0) routing sp4_h_l_40 <X> sp4_h_r_1 +(10 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(10 0) routing sp4_v_t_45 <X> sp4_h_r_1 +(10 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(10 1) routing sp4_h_r_8 <X> sp4_v_b_1 +(10 1) routing sp4_v_t_40 <X> sp4_v_b_1 +(10 1) routing sp4_v_t_47 <X> sp4_v_b_1 +(10 10) routing sp4_h_r_4 <X> sp4_h_l_42 +(10 10) routing sp4_v_b_2 <X> sp4_h_l_42 +(10 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(10 11) routing sp4_h_l_39 <X> sp4_v_t_42 +(10 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(10 11) routing sp4_v_b_11 <X> sp4_v_t_42 +(10 11) routing sp4_v_b_4 <X> sp4_v_t_42 +(10 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(10 12) routing sp4_v_t_40 <X> sp4_h_r_10 +(10 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(10 13) routing sp4_h_r_5 <X> sp4_v_b_10 +(10 13) routing sp4_v_t_39 <X> sp4_v_b_10 +(10 13) routing sp4_v_t_42 <X> sp4_v_b_10 +(10 14) routing sp4_h_r_2 <X> sp4_h_l_47 +(10 14) routing sp4_v_b_5 <X> sp4_h_l_47 +(10 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(10 15) routing sp4_h_l_40 <X> sp4_v_t_47 +(10 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(10 15) routing sp4_v_b_2 <X> sp4_v_t_47 +(10 15) routing sp4_v_b_7 <X> sp4_v_t_47 +(10 2) routing sp4_h_r_10 <X> sp4_h_l_36 +(10 2) routing sp4_v_b_8 <X> sp4_h_l_36 +(10 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(10 3) routing sp4_h_l_45 <X> sp4_v_t_36 +(10 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(10 3) routing sp4_v_b_10 <X> sp4_v_t_36 +(10 3) routing sp4_v_b_5 <X> sp4_v_t_36 +(10 4) routing sp4_h_l_45 <X> sp4_h_r_4 +(10 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(10 4) routing sp4_v_t_46 <X> sp4_h_r_4 +(10 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(10 5) routing sp4_h_r_11 <X> sp4_v_b_4 +(10 5) routing sp4_v_t_36 <X> sp4_v_b_4 +(10 5) routing sp4_v_t_45 <X> sp4_v_b_4 +(10 6) routing sp4_h_r_8 <X> sp4_h_l_41 +(10 6) routing sp4_v_b_11 <X> sp4_h_l_41 +(10 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(10 7) routing sp4_h_l_46 <X> sp4_v_t_41 +(10 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(10 7) routing sp4_v_b_1 <X> sp4_v_t_41 +(10 7) routing sp4_v_b_8 <X> sp4_v_t_41 +(10 8) routing sp4_h_l_41 <X> sp4_h_r_7 +(10 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(10 8) routing sp4_v_t_39 <X> sp4_h_r_7 +(10 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(10 9) routing sp4_h_r_2 <X> sp4_v_b_7 +(10 9) routing sp4_v_t_41 <X> sp4_v_b_7 +(10 9) routing sp4_v_t_46 <X> sp4_v_b_7 +(11 0) routing sp4_h_l_45 <X> sp4_v_b_2 +(11 0) routing sp4_h_r_9 <X> sp4_v_b_2 +(11 0) routing sp4_v_t_43 <X> sp4_v_b_2 +(11 0) routing sp4_v_t_46 <X> sp4_v_b_2 +(11 1) routing sp4_v_b_2 <X> sp4_h_r_2 +(11 1) routing sp4_v_b_8 <X> sp4_h_r_2 +(11 10) routing sp4_h_l_38 <X> sp4_v_t_45 +(11 10) routing sp4_h_r_2 <X> sp4_v_t_45 +(11 10) routing sp4_v_b_0 <X> sp4_v_t_45 +(11 10) routing sp4_v_b_5 <X> sp4_v_t_45 +(11 11) routing sp4_h_r_0 <X> sp4_h_l_45 +(11 11) routing sp4_h_r_8 <X> sp4_h_l_45 +(11 11) routing sp4_v_t_39 <X> sp4_h_l_45 +(11 11) routing sp4_v_t_45 <X> sp4_h_l_45 +(11 12) routing sp4_h_l_40 <X> sp4_v_b_11 +(11 12) routing sp4_h_r_6 <X> sp4_v_b_11 +(11 12) routing sp4_v_t_38 <X> sp4_v_b_11 +(11 12) routing sp4_v_t_45 <X> sp4_v_b_11 +(11 13) routing sp4_v_b_11 <X> sp4_h_r_11 +(11 13) routing sp4_v_b_5 <X> sp4_h_r_11 +(11 14) routing sp4_h_l_43 <X> sp4_v_t_46 +(11 14) routing sp4_h_r_5 <X> sp4_v_t_46 +(11 14) routing sp4_v_b_3 <X> sp4_v_t_46 +(11 14) routing sp4_v_b_8 <X> sp4_v_t_46 +(11 15) routing sp4_h_r_3 <X> sp4_h_l_46 +(11 15) routing sp4_v_t_40 <X> sp4_h_l_46 +(11 15) routing sp4_v_t_46 <X> sp4_h_l_46 +(11 2) routing sp4_h_l_44 <X> sp4_v_t_39 +(11 2) routing sp4_h_r_8 <X> sp4_v_t_39 +(11 2) routing sp4_v_b_11 <X> sp4_v_t_39 +(11 2) routing sp4_v_b_6 <X> sp4_v_t_39 +(11 3) routing sp4_h_r_2 <X> sp4_h_l_39 +(11 3) routing sp4_h_r_6 <X> sp4_h_l_39 +(11 3) routing sp4_v_t_39 <X> sp4_h_l_39 +(11 3) routing sp4_v_t_45 <X> sp4_h_l_39 +(11 4) routing sp4_h_l_46 <X> sp4_v_b_5 +(11 4) routing sp4_h_r_0 <X> sp4_v_b_5 +(11 4) routing sp4_v_t_39 <X> sp4_v_b_5 +(11 4) routing sp4_v_t_44 <X> sp4_v_b_5 +(11 5) routing sp4_v_b_11 <X> sp4_h_r_5 +(11 5) routing sp4_v_b_5 <X> sp4_h_r_5 +(11 6) routing sp4_h_l_37 <X> sp4_v_t_40 +(11 6) routing sp4_h_r_11 <X> sp4_v_t_40 +(11 6) routing sp4_v_b_2 <X> sp4_v_t_40 +(11 6) routing sp4_v_b_9 <X> sp4_v_t_40 +(11 7) routing sp4_v_t_40 <X> sp4_h_l_40 +(11 7) routing sp4_v_t_46 <X> sp4_h_l_40 +(11 8) routing sp4_h_l_39 <X> sp4_v_b_8 +(11 8) routing sp4_h_r_3 <X> sp4_v_b_8 +(11 8) routing sp4_v_t_37 <X> sp4_v_b_8 +(11 8) routing sp4_v_t_40 <X> sp4_v_b_8 +(11 9) routing sp4_h_l_37 <X> sp4_h_r_8 +(11 9) routing sp4_v_b_2 <X> sp4_h_r_8 +(11 9) routing sp4_v_b_8 <X> sp4_h_r_8 +(12 0) routing sp4_v_b_2 <X> sp4_h_r_2 +(12 0) routing sp4_v_b_8 <X> sp4_h_r_2 +(12 0) routing sp4_v_t_39 <X> sp4_h_r_2 +(12 1) routing sp4_h_l_39 <X> sp4_v_b_2 +(12 1) routing sp4_h_l_45 <X> sp4_v_b_2 +(12 1) routing sp4_h_r_2 <X> sp4_v_b_2 +(12 1) routing sp4_v_t_46 <X> sp4_v_b_2 +(12 10) routing sp4_v_b_8 <X> sp4_h_l_45 +(12 10) routing sp4_v_t_39 <X> sp4_h_l_45 +(12 10) routing sp4_v_t_45 <X> sp4_h_l_45 +(12 11) routing sp4_h_l_45 <X> sp4_v_t_45 +(12 11) routing sp4_h_r_2 <X> sp4_v_t_45 +(12 11) routing sp4_h_r_8 <X> sp4_v_t_45 +(12 11) routing sp4_v_b_5 <X> sp4_v_t_45 +(12 12) routing sp4_v_b_11 <X> sp4_h_r_11 +(12 12) routing sp4_v_b_5 <X> sp4_h_r_11 +(12 12) routing sp4_v_t_46 <X> sp4_h_r_11 +(12 13) routing sp4_h_l_40 <X> sp4_v_b_11 +(12 13) routing sp4_h_l_46 <X> sp4_v_b_11 +(12 13) routing sp4_h_r_11 <X> sp4_v_b_11 +(12 13) routing sp4_v_t_45 <X> sp4_v_b_11 +(12 14) routing sp4_h_r_8 <X> sp4_h_l_46 +(12 14) routing sp4_v_b_11 <X> sp4_h_l_46 +(12 14) routing sp4_v_t_40 <X> sp4_h_l_46 +(12 14) routing sp4_v_t_46 <X> sp4_h_l_46 +(12 15) routing sp4_h_l_46 <X> sp4_v_t_46 +(12 15) routing sp4_h_r_11 <X> sp4_v_t_46 +(12 15) routing sp4_h_r_5 <X> sp4_v_t_46 +(12 15) routing sp4_v_b_8 <X> sp4_v_t_46 +(12 2) routing sp4_h_r_11 <X> sp4_h_l_39 +(12 2) routing sp4_v_b_2 <X> sp4_h_l_39 +(12 2) routing sp4_v_t_39 <X> sp4_h_l_39 +(12 2) routing sp4_v_t_45 <X> sp4_h_l_39 +(12 3) routing sp4_h_l_39 <X> sp4_v_t_39 +(12 3) routing sp4_h_r_2 <X> sp4_v_t_39 +(12 3) routing sp4_h_r_8 <X> sp4_v_t_39 +(12 3) routing sp4_v_b_11 <X> sp4_v_t_39 +(12 4) routing sp4_v_b_11 <X> sp4_h_r_5 +(12 4) routing sp4_v_b_5 <X> sp4_h_r_5 +(12 4) routing sp4_v_t_40 <X> sp4_h_r_5 +(12 5) routing sp4_h_l_40 <X> sp4_v_b_5 +(12 5) routing sp4_h_l_46 <X> sp4_v_b_5 +(12 5) routing sp4_h_r_5 <X> sp4_v_b_5 +(12 5) routing sp4_v_t_39 <X> sp4_v_b_5 +(12 6) routing sp4_h_r_2 <X> sp4_h_l_40 +(12 6) routing sp4_v_b_5 <X> sp4_h_l_40 +(12 6) routing sp4_v_t_40 <X> sp4_h_l_40 +(12 6) routing sp4_v_t_46 <X> sp4_h_l_40 +(12 7) routing sp4_h_l_40 <X> sp4_v_t_40 +(12 7) routing sp4_h_r_11 <X> sp4_v_t_40 +(12 7) routing sp4_h_r_5 <X> sp4_v_t_40 +(12 7) routing sp4_v_b_2 <X> sp4_v_t_40 +(12 8) routing sp4_h_l_40 <X> sp4_h_r_8 +(12 8) routing sp4_v_b_2 <X> sp4_h_r_8 +(12 8) routing sp4_v_b_8 <X> sp4_h_r_8 +(12 8) routing sp4_v_t_45 <X> sp4_h_r_8 +(12 9) routing sp4_h_l_39 <X> sp4_v_b_8 +(12 9) routing sp4_h_l_45 <X> sp4_v_b_8 +(12 9) routing sp4_h_r_8 <X> sp4_v_b_8 +(12 9) routing sp4_v_t_40 <X> sp4_v_b_8 +(13 0) routing sp4_h_l_39 <X> sp4_v_b_2 +(13 0) routing sp4_h_l_45 <X> sp4_v_b_2 +(13 0) routing sp4_v_t_39 <X> sp4_v_b_2 +(13 0) routing sp4_v_t_43 <X> sp4_v_b_2 +(13 1) routing sp4_v_b_8 <X> sp4_h_r_2 +(13 1) routing sp4_v_t_44 <X> sp4_h_r_2 +(13 10) routing sp4_h_r_2 <X> sp4_v_t_45 +(13 10) routing sp4_h_r_8 <X> sp4_v_t_45 +(13 10) routing sp4_v_b_0 <X> sp4_v_t_45 +(13 10) routing sp4_v_b_8 <X> sp4_v_t_45 +(13 11) routing sp4_h_r_0 <X> sp4_h_l_45 +(13 11) routing sp4_v_b_3 <X> sp4_h_l_45 +(13 11) routing sp4_v_t_39 <X> sp4_h_l_45 +(13 12) routing sp4_h_l_40 <X> sp4_v_b_11 +(13 12) routing sp4_h_l_46 <X> sp4_v_b_11 +(13 12) routing sp4_v_t_38 <X> sp4_v_b_11 +(13 12) routing sp4_v_t_46 <X> sp4_v_b_11 +(13 13) routing sp4_v_b_5 <X> sp4_h_r_11 +(13 13) routing sp4_v_t_43 <X> sp4_h_r_11 +(13 14) routing sp4_h_r_11 <X> sp4_v_t_46 +(13 14) routing sp4_h_r_5 <X> sp4_v_t_46 +(13 14) routing sp4_v_b_11 <X> sp4_v_t_46 +(13 14) routing sp4_v_b_3 <X> sp4_v_t_46 +(13 15) routing sp4_h_r_3 <X> sp4_h_l_46 +(13 15) routing sp4_h_r_8 <X> sp4_h_l_46 +(13 15) routing sp4_v_b_6 <X> sp4_h_l_46 +(13 15) routing sp4_v_t_40 <X> sp4_h_l_46 +(13 2) routing sp4_h_r_2 <X> sp4_v_t_39 +(13 2) routing sp4_h_r_8 <X> sp4_v_t_39 +(13 2) routing sp4_v_b_2 <X> sp4_v_t_39 +(13 2) routing sp4_v_b_6 <X> sp4_v_t_39 +(13 3) routing sp4_h_r_11 <X> sp4_h_l_39 +(13 3) routing sp4_h_r_6 <X> sp4_h_l_39 +(13 3) routing sp4_v_b_9 <X> sp4_h_l_39 +(13 3) routing sp4_v_t_45 <X> sp4_h_l_39 +(13 4) routing sp4_h_l_40 <X> sp4_v_b_5 +(13 4) routing sp4_h_l_46 <X> sp4_v_b_5 +(13 4) routing sp4_v_t_40 <X> sp4_v_b_5 +(13 4) routing sp4_v_t_44 <X> sp4_v_b_5 +(13 5) routing sp4_v_b_11 <X> sp4_h_r_5 +(13 5) routing sp4_v_t_37 <X> sp4_h_r_5 +(13 6) routing sp4_h_r_11 <X> sp4_v_t_40 +(13 6) routing sp4_h_r_5 <X> sp4_v_t_40 +(13 6) routing sp4_v_b_5 <X> sp4_v_t_40 +(13 6) routing sp4_v_b_9 <X> sp4_v_t_40 +(13 7) routing sp4_h_r_2 <X> sp4_h_l_40 +(13 7) routing sp4_v_b_0 <X> sp4_h_l_40 +(13 7) routing sp4_v_t_46 <X> sp4_h_l_40 +(13 8) routing sp4_h_l_39 <X> sp4_v_b_8 +(13 8) routing sp4_h_l_45 <X> sp4_v_b_8 +(13 8) routing sp4_v_t_37 <X> sp4_v_b_8 +(13 8) routing sp4_v_t_45 <X> sp4_v_b_8 +(13 9) routing sp4_h_l_37 <X> sp4_h_r_8 +(13 9) routing sp4_h_l_40 <X> sp4_h_r_8 +(13 9) routing sp4_v_b_2 <X> sp4_h_r_8 +(13 9) routing sp4_v_t_38 <X> sp4_h_r_8 +(14 0) routing bnr_op_0 <X> lc_trk_g0_0 +(14 0) routing lft_op_0 <X> lc_trk_g0_0 +(14 0) routing sp12_h_r_0 <X> lc_trk_g0_0 +(14 0) routing sp4_h_r_16 <X> lc_trk_g0_0 +(14 0) routing sp4_h_r_8 <X> lc_trk_g0_0 +(14 0) routing sp4_v_b_0 <X> lc_trk_g0_0 +(14 0) routing sp4_v_b_8 <X> lc_trk_g0_0 +(14 1) routing bnr_op_0 <X> lc_trk_g0_0 +(14 1) routing sp12_h_l_15 <X> lc_trk_g0_0 +(14 1) routing sp12_h_r_0 <X> lc_trk_g0_0 +(14 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(14 1) routing sp4_h_r_16 <X> lc_trk_g0_0 +(14 1) routing sp4_r_v_b_35 <X> lc_trk_g0_0 +(14 1) routing sp4_v_b_8 <X> lc_trk_g0_0 +(14 10) routing bnl_op_4 <X> lc_trk_g2_4 +(14 10) routing rgt_op_4 <X> lc_trk_g2_4 +(14 10) routing sp12_v_t_3 <X> lc_trk_g2_4 +(14 10) routing sp4_h_r_36 <X> lc_trk_g2_4 +(14 10) routing sp4_h_r_44 <X> lc_trk_g2_4 +(14 10) routing sp4_v_t_17 <X> lc_trk_g2_4 +(14 10) routing sp4_v_t_25 <X> lc_trk_g2_4 +(14 11) routing bnl_op_4 <X> lc_trk_g2_4 +(14 11) routing sp12_v_t_19 <X> lc_trk_g2_4 +(14 11) routing sp12_v_t_3 <X> lc_trk_g2_4 +(14 11) routing sp4_h_l_17 <X> lc_trk_g2_4 +(14 11) routing sp4_h_r_44 <X> lc_trk_g2_4 +(14 11) routing sp4_r_v_b_36 <X> lc_trk_g2_4 +(14 11) routing sp4_v_t_25 <X> lc_trk_g2_4 +(14 11) routing tnl_op_4 <X> lc_trk_g2_4 +(14 12) routing bnl_op_0 <X> lc_trk_g3_0 +(14 12) routing rgt_op_0 <X> lc_trk_g3_0 +(14 12) routing sp12_v_b_0 <X> lc_trk_g3_0 +(14 12) routing sp4_h_l_21 <X> lc_trk_g3_0 +(14 12) routing sp4_h_r_40 <X> lc_trk_g3_0 +(14 12) routing sp4_v_b_24 <X> lc_trk_g3_0 +(14 12) routing sp4_v_t_21 <X> lc_trk_g3_0 +(14 13) routing bnl_op_0 <X> lc_trk_g3_0 +(14 13) routing sp12_v_b_0 <X> lc_trk_g3_0 +(14 13) routing sp12_v_t_15 <X> lc_trk_g3_0 +(14 13) routing sp4_h_r_24 <X> lc_trk_g3_0 +(14 13) routing sp4_h_r_40 <X> lc_trk_g3_0 +(14 13) routing sp4_r_v_b_40 <X> lc_trk_g3_0 +(14 13) routing sp4_v_t_21 <X> lc_trk_g3_0 +(14 13) routing tnl_op_0 <X> lc_trk_g3_0 +(14 14) routing bnl_op_4 <X> lc_trk_g3_4 +(14 14) routing rgt_op_4 <X> lc_trk_g3_4 +(14 14) routing sp12_v_t_3 <X> lc_trk_g3_4 +(14 14) routing sp4_h_r_36 <X> lc_trk_g3_4 +(14 14) routing sp4_h_r_44 <X> lc_trk_g3_4 +(14 14) routing sp4_v_t_17 <X> lc_trk_g3_4 +(14 14) routing sp4_v_t_25 <X> lc_trk_g3_4 +(14 15) routing bnl_op_4 <X> lc_trk_g3_4 +(14 15) routing sp12_v_t_19 <X> lc_trk_g3_4 +(14 15) routing sp12_v_t_3 <X> lc_trk_g3_4 +(14 15) routing sp4_h_l_17 <X> lc_trk_g3_4 +(14 15) routing sp4_h_r_44 <X> lc_trk_g3_4 +(14 15) routing sp4_r_v_b_44 <X> lc_trk_g3_4 +(14 15) routing sp4_v_t_25 <X> lc_trk_g3_4 +(14 15) routing tnl_op_4 <X> lc_trk_g3_4 +(14 2) routing bnr_op_4 <X> lc_trk_g0_4 +(14 2) routing lft_op_4 <X> lc_trk_g0_4 +(14 2) routing sp12_h_l_3 <X> lc_trk_g0_4 +(14 2) routing sp4_h_l_9 <X> lc_trk_g0_4 +(14 2) routing sp4_h_r_12 <X> lc_trk_g0_4 +(14 2) routing sp4_v_b_12 <X> lc_trk_g0_4 +(14 2) routing sp4_v_b_4 <X> lc_trk_g0_4 +(14 3) routing bnr_op_4 <X> lc_trk_g0_4 +(14 3) routing sp12_h_l_19 <X> lc_trk_g0_4 +(14 3) routing sp12_h_l_3 <X> lc_trk_g0_4 +(14 3) routing sp4_h_l_9 <X> lc_trk_g0_4 +(14 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(14 3) routing sp4_r_v_b_28 <X> lc_trk_g0_4 +(14 3) routing sp4_v_b_12 <X> lc_trk_g0_4 +(14 4) routing bnr_op_0 <X> lc_trk_g1_0 +(14 4) routing lft_op_0 <X> lc_trk_g1_0 +(14 4) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 4) routing sp4_h_r_16 <X> lc_trk_g1_0 +(14 4) routing sp4_h_r_8 <X> lc_trk_g1_0 +(14 4) routing sp4_v_b_0 <X> lc_trk_g1_0 +(14 4) routing sp4_v_b_8 <X> lc_trk_g1_0 +(14 5) routing bnr_op_0 <X> lc_trk_g1_0 +(14 5) routing sp12_h_l_15 <X> lc_trk_g1_0 +(14 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp4_h_r_16 <X> lc_trk_g1_0 +(14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0 +(14 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(14 6) routing bnr_op_4 <X> lc_trk_g1_4 +(14 6) routing lft_op_4 <X> lc_trk_g1_4 +(14 6) routing sp12_h_l_3 <X> lc_trk_g1_4 +(14 6) routing sp4_h_l_9 <X> lc_trk_g1_4 +(14 6) routing sp4_h_r_12 <X> lc_trk_g1_4 +(14 6) routing sp4_v_b_12 <X> lc_trk_g1_4 +(14 6) routing sp4_v_b_4 <X> lc_trk_g1_4 +(14 7) routing bnr_op_4 <X> lc_trk_g1_4 +(14 7) routing sp12_h_l_19 <X> lc_trk_g1_4 +(14 7) routing sp12_h_l_3 <X> lc_trk_g1_4 +(14 7) routing sp4_h_l_9 <X> lc_trk_g1_4 +(14 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4 +(14 7) routing sp4_v_b_12 <X> lc_trk_g1_4 +(14 8) routing bnl_op_0 <X> lc_trk_g2_0 +(14 8) routing rgt_op_0 <X> lc_trk_g2_0 +(14 8) routing sp12_v_b_0 <X> lc_trk_g2_0 +(14 8) routing sp4_h_l_21 <X> lc_trk_g2_0 +(14 8) routing sp4_h_r_40 <X> lc_trk_g2_0 +(14 8) routing sp4_v_b_24 <X> lc_trk_g2_0 +(14 8) routing sp4_v_t_21 <X> lc_trk_g2_0 +(14 9) routing bnl_op_0 <X> lc_trk_g2_0 +(14 9) routing sp12_v_b_0 <X> lc_trk_g2_0 +(14 9) routing sp12_v_t_15 <X> lc_trk_g2_0 +(14 9) routing sp4_h_r_24 <X> lc_trk_g2_0 +(14 9) routing sp4_h_r_40 <X> lc_trk_g2_0 +(14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0 +(14 9) routing sp4_v_t_21 <X> lc_trk_g2_0 +(14 9) routing tnl_op_0 <X> lc_trk_g2_0 +(15 0) routing lft_op_1 <X> lc_trk_g0_1 +(15 0) routing sp12_h_r_1 <X> lc_trk_g0_1 +(15 0) routing sp4_h_l_4 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_1 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(15 0) routing sp4_v_b_17 <X> lc_trk_g0_1 +(15 1) routing lft_op_0 <X> lc_trk_g0_0 +(15 1) routing sp12_h_r_0 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_16 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_8 <X> lc_trk_g0_0 +(15 1) routing sp4_v_b_16 <X> lc_trk_g0_0 +(15 10) routing rgt_op_5 <X> lc_trk_g2_5 +(15 10) routing sp12_v_b_5 <X> lc_trk_g2_5 +(15 10) routing sp4_h_l_16 <X> lc_trk_g2_5 +(15 10) routing sp4_h_l_32 <X> lc_trk_g2_5 +(15 10) routing sp4_h_r_37 <X> lc_trk_g2_5 +(15 10) routing sp4_v_b_45 <X> lc_trk_g2_5 +(15 10) routing tnl_op_5 <X> lc_trk_g2_5 +(15 10) routing tnr_op_5 <X> lc_trk_g2_5 +(15 11) routing rgt_op_4 <X> lc_trk_g2_4 +(15 11) routing sp12_v_t_3 <X> lc_trk_g2_4 +(15 11) routing sp4_h_l_17 <X> lc_trk_g2_4 +(15 11) routing sp4_h_r_36 <X> lc_trk_g2_4 +(15 11) routing sp4_h_r_44 <X> lc_trk_g2_4 +(15 11) routing sp4_v_t_33 <X> lc_trk_g2_4 +(15 11) routing tnl_op_4 <X> lc_trk_g2_4 +(15 12) routing rgt_op_1 <X> lc_trk_g3_1 +(15 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(15 12) routing sp4_h_l_28 <X> lc_trk_g3_1 +(15 12) routing sp4_h_r_25 <X> lc_trk_g3_1 +(15 12) routing sp4_h_r_33 <X> lc_trk_g3_1 +(15 12) routing sp4_v_t_28 <X> lc_trk_g3_1 +(15 12) routing tnl_op_1 <X> lc_trk_g3_1 +(15 12) routing tnr_op_1 <X> lc_trk_g3_1 +(15 13) routing rgt_op_0 <X> lc_trk_g3_0 +(15 13) routing sp12_v_b_0 <X> lc_trk_g3_0 +(15 13) routing sp4_h_l_21 <X> lc_trk_g3_0 +(15 13) routing sp4_h_r_24 <X> lc_trk_g3_0 +(15 13) routing sp4_h_r_40 <X> lc_trk_g3_0 +(15 13) routing sp4_v_t_29 <X> lc_trk_g3_0 +(15 13) routing tnl_op_0 <X> lc_trk_g3_0 +(15 13) routing tnr_op_0 <X> lc_trk_g3_0 +(15 14) routing rgt_op_5 <X> lc_trk_g3_5 +(15 14) routing sp12_v_b_5 <X> lc_trk_g3_5 +(15 14) routing sp4_h_l_16 <X> lc_trk_g3_5 +(15 14) routing sp4_h_l_32 <X> lc_trk_g3_5 +(15 14) routing sp4_h_r_37 <X> lc_trk_g3_5 +(15 14) routing sp4_v_b_45 <X> lc_trk_g3_5 +(15 14) routing tnl_op_5 <X> lc_trk_g3_5 +(15 14) routing tnr_op_5 <X> lc_trk_g3_5 +(15 15) routing rgt_op_4 <X> lc_trk_g3_4 +(15 15) routing sp12_v_t_3 <X> lc_trk_g3_4 +(15 15) routing sp4_h_l_17 <X> lc_trk_g3_4 +(15 15) routing sp4_h_r_36 <X> lc_trk_g3_4 +(15 15) routing sp4_h_r_44 <X> lc_trk_g3_4 +(15 15) routing sp4_v_t_33 <X> lc_trk_g3_4 +(15 15) routing tnl_op_4 <X> lc_trk_g3_4 +(15 15) routing tnr_op_4 <X> lc_trk_g3_4 +(15 2) routing lft_op_5 <X> lc_trk_g0_5 +(15 2) routing sp12_h_r_5 <X> lc_trk_g0_5 +(15 2) routing sp4_h_l_0 <X> lc_trk_g0_5 +(15 2) routing sp4_h_r_21 <X> lc_trk_g0_5 +(15 2) routing sp4_h_r_5 <X> lc_trk_g0_5 +(15 2) routing sp4_v_b_21 <X> lc_trk_g0_5 +(15 3) routing lft_op_4 <X> lc_trk_g0_4 +(15 3) routing sp12_h_l_3 <X> lc_trk_g0_4 +(15 3) routing sp4_h_l_9 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_12 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(15 3) routing sp4_v_t_9 <X> lc_trk_g0_4 +(15 4) routing lft_op_1 <X> lc_trk_g1_1 +(15 4) routing sp12_h_r_1 <X> lc_trk_g1_1 +(15 4) routing sp4_h_l_4 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_1 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(15 4) routing sp4_v_b_17 <X> lc_trk_g1_1 +(15 5) routing lft_op_0 <X> lc_trk_g1_0 +(15 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_16 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_8 <X> lc_trk_g1_0 +(15 5) routing sp4_v_b_16 <X> lc_trk_g1_0 +(15 6) routing lft_op_5 <X> lc_trk_g1_5 +(15 6) routing sp12_h_r_5 <X> lc_trk_g1_5 +(15 6) routing sp4_h_l_0 <X> lc_trk_g1_5 +(15 6) routing sp4_h_r_21 <X> lc_trk_g1_5 +(15 6) routing sp4_h_r_5 <X> lc_trk_g1_5 +(15 6) routing sp4_v_b_21 <X> lc_trk_g1_5 +(15 7) routing lft_op_4 <X> lc_trk_g1_4 +(15 7) routing sp12_h_l_3 <X> lc_trk_g1_4 +(15 7) routing sp4_h_l_9 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_12 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(15 7) routing sp4_v_t_9 <X> lc_trk_g1_4 +(15 8) routing rgt_op_1 <X> lc_trk_g2_1 +(15 8) routing sp12_v_b_1 <X> lc_trk_g2_1 +(15 8) routing sp4_h_l_28 <X> lc_trk_g2_1 +(15 8) routing sp4_h_r_25 <X> lc_trk_g2_1 +(15 8) routing sp4_h_r_33 <X> lc_trk_g2_1 +(15 8) routing sp4_v_t_28 <X> lc_trk_g2_1 +(15 8) routing tnl_op_1 <X> lc_trk_g2_1 +(15 8) routing tnr_op_1 <X> lc_trk_g2_1 +(15 9) routing rgt_op_0 <X> lc_trk_g2_0 +(15 9) routing sp12_v_b_0 <X> lc_trk_g2_0 +(15 9) routing sp4_h_l_21 <X> lc_trk_g2_0 +(15 9) routing sp4_h_r_24 <X> lc_trk_g2_0 +(15 9) routing sp4_h_r_40 <X> lc_trk_g2_0 +(15 9) routing sp4_v_t_29 <X> lc_trk_g2_0 +(15 9) routing tnl_op_0 <X> lc_trk_g2_0 +(15 9) routing tnr_op_0 <X> lc_trk_g2_0 +(16 0) routing sp12_h_r_17 <X> lc_trk_g0_1 +(16 0) routing sp12_h_r_9 <X> lc_trk_g0_1 +(16 0) routing sp4_h_l_4 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_1 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_1 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_17 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_9 <X> lc_trk_g0_1 +(16 1) routing sp12_h_l_15 <X> lc_trk_g0_0 +(16 1) routing sp12_h_r_8 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_16 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_8 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_0 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_16 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_8 <X> lc_trk_g0_0 +(16 10) routing sp12_v_b_21 <X> lc_trk_g2_5 +(16 10) routing sp12_v_t_10 <X> lc_trk_g2_5 +(16 10) routing sp4_h_l_16 <X> lc_trk_g2_5 +(16 10) routing sp4_h_l_32 <X> lc_trk_g2_5 +(16 10) routing sp4_h_r_37 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_29 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_37 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_45 <X> lc_trk_g2_5 +(16 11) routing sp12_v_b_12 <X> lc_trk_g2_4 +(16 11) routing sp12_v_t_19 <X> lc_trk_g2_4 +(16 11) routing sp4_h_l_17 <X> lc_trk_g2_4 +(16 11) routing sp4_h_r_36 <X> lc_trk_g2_4 +(16 11) routing sp4_h_r_44 <X> lc_trk_g2_4 +(16 11) routing sp4_v_t_17 <X> lc_trk_g2_4 +(16 11) routing sp4_v_t_25 <X> lc_trk_g2_4 +(16 11) routing sp4_v_t_33 <X> lc_trk_g2_4 +(16 12) routing sp12_v_b_9 <X> lc_trk_g3_1 +(16 12) routing sp12_v_t_14 <X> lc_trk_g3_1 +(16 12) routing sp4_h_l_28 <X> lc_trk_g3_1 +(16 12) routing sp4_h_r_25 <X> lc_trk_g3_1 +(16 12) routing sp4_h_r_33 <X> lc_trk_g3_1 +(16 12) routing sp4_v_t_12 <X> lc_trk_g3_1 +(16 12) routing sp4_v_t_20 <X> lc_trk_g3_1 +(16 12) routing sp4_v_t_28 <X> lc_trk_g3_1 +(16 13) routing sp12_v_b_8 <X> lc_trk_g3_0 +(16 13) routing sp12_v_t_15 <X> lc_trk_g3_0 +(16 13) routing sp4_h_l_21 <X> lc_trk_g3_0 +(16 13) routing sp4_h_r_24 <X> lc_trk_g3_0 +(16 13) routing sp4_h_r_40 <X> lc_trk_g3_0 +(16 13) routing sp4_v_b_24 <X> lc_trk_g3_0 +(16 13) routing sp4_v_t_21 <X> lc_trk_g3_0 +(16 13) routing sp4_v_t_29 <X> lc_trk_g3_0 +(16 14) routing sp12_v_b_21 <X> lc_trk_g3_5 +(16 14) routing sp12_v_t_10 <X> lc_trk_g3_5 +(16 14) routing sp4_h_l_16 <X> lc_trk_g3_5 +(16 14) routing sp4_h_l_32 <X> lc_trk_g3_5 +(16 14) routing sp4_h_r_37 <X> lc_trk_g3_5 +(16 14) routing sp4_v_b_29 <X> lc_trk_g3_5 +(16 14) routing sp4_v_b_37 <X> lc_trk_g3_5 +(16 14) routing sp4_v_b_45 <X> lc_trk_g3_5 +(16 15) routing sp12_v_b_12 <X> lc_trk_g3_4 +(16 15) routing sp12_v_t_19 <X> lc_trk_g3_4 +(16 15) routing sp4_h_l_17 <X> lc_trk_g3_4 +(16 15) routing sp4_h_r_36 <X> lc_trk_g3_4 +(16 15) routing sp4_h_r_44 <X> lc_trk_g3_4 +(16 15) routing sp4_v_t_17 <X> lc_trk_g3_4 +(16 15) routing sp4_v_t_25 <X> lc_trk_g3_4 +(16 15) routing sp4_v_t_33 <X> lc_trk_g3_4 +(16 2) routing sp12_h_l_10 <X> lc_trk_g0_5 +(16 2) routing sp12_h_l_18 <X> lc_trk_g0_5 +(16 2) routing sp4_h_l_0 <X> lc_trk_g0_5 +(16 2) routing sp4_h_r_21 <X> lc_trk_g0_5 +(16 2) routing sp4_h_r_5 <X> lc_trk_g0_5 +(16 2) routing sp4_v_b_13 <X> lc_trk_g0_5 +(16 2) routing sp4_v_b_21 <X> lc_trk_g0_5 +(16 2) routing sp4_v_b_5 <X> lc_trk_g0_5 +(16 3) routing sp12_h_l_11 <X> lc_trk_g0_4 +(16 3) routing sp12_h_l_19 <X> lc_trk_g0_4 +(16 3) routing sp4_h_l_9 <X> lc_trk_g0_4 +(16 3) routing sp4_h_r_12 <X> lc_trk_g0_4 +(16 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(16 3) routing sp4_v_b_12 <X> lc_trk_g0_4 +(16 3) routing sp4_v_b_4 <X> lc_trk_g0_4 +(16 3) routing sp4_v_t_9 <X> lc_trk_g0_4 +(16 4) routing sp12_h_r_17 <X> lc_trk_g1_1 +(16 4) routing sp12_h_r_9 <X> lc_trk_g1_1 +(16 4) routing sp4_h_l_4 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_1 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_1 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_17 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_9 <X> lc_trk_g1_1 +(16 5) routing sp12_h_l_15 <X> lc_trk_g1_0 +(16 5) routing sp12_h_r_8 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_16 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_8 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_0 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_16 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(16 6) routing sp12_h_l_10 <X> lc_trk_g1_5 +(16 6) routing sp12_h_l_18 <X> lc_trk_g1_5 +(16 6) routing sp4_h_l_0 <X> lc_trk_g1_5 +(16 6) routing sp4_h_r_21 <X> lc_trk_g1_5 +(16 6) routing sp4_h_r_5 <X> lc_trk_g1_5 +(16 6) routing sp4_v_b_13 <X> lc_trk_g1_5 +(16 6) routing sp4_v_b_21 <X> lc_trk_g1_5 +(16 6) routing sp4_v_b_5 <X> lc_trk_g1_5 +(16 7) routing sp12_h_l_11 <X> lc_trk_g1_4 +(16 7) routing sp12_h_l_19 <X> lc_trk_g1_4 +(16 7) routing sp4_h_l_9 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_12 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(16 7) routing sp4_v_b_12 <X> lc_trk_g1_4 +(16 7) routing sp4_v_b_4 <X> lc_trk_g1_4 +(16 7) routing sp4_v_t_9 <X> lc_trk_g1_4 +(16 8) routing sp12_v_b_9 <X> lc_trk_g2_1 +(16 8) routing sp12_v_t_14 <X> lc_trk_g2_1 +(16 8) routing sp4_h_l_28 <X> lc_trk_g2_1 +(16 8) routing sp4_h_r_25 <X> lc_trk_g2_1 +(16 8) routing sp4_h_r_33 <X> lc_trk_g2_1 +(16 8) routing sp4_v_t_12 <X> lc_trk_g2_1 +(16 8) routing sp4_v_t_20 <X> lc_trk_g2_1 +(16 8) routing sp4_v_t_28 <X> lc_trk_g2_1 +(16 9) routing sp12_v_b_8 <X> lc_trk_g2_0 +(16 9) routing sp12_v_t_15 <X> lc_trk_g2_0 +(16 9) routing sp4_h_l_21 <X> lc_trk_g2_0 +(16 9) routing sp4_h_r_24 <X> lc_trk_g2_0 +(16 9) routing sp4_h_r_40 <X> lc_trk_g2_0 +(16 9) routing sp4_v_b_24 <X> lc_trk_g2_0 +(16 9) routing sp4_v_t_21 <X> lc_trk_g2_0 +(16 9) routing sp4_v_t_29 <X> lc_trk_g2_0 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_l_4 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_32 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_19 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_17 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_33 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_33 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_12 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_28 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_8 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_15 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_24 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_24 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_21 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_29 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_32 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_37 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_19 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_33 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_0 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_21 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_11 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_19 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_9 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_9 lc_trk_g0_4 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_l_4 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_0 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_21 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_11 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_19 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_9 lc_trk_g1_4 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_12 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_28 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_15 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_21 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_24 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_29 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 +(18 0) routing bnr_op_1 <X> lc_trk_g0_1 +(18 0) routing lft_op_1 <X> lc_trk_g0_1 +(18 0) routing sp12_h_r_1 <X> lc_trk_g0_1 +(18 0) routing sp4_h_l_4 <X> lc_trk_g0_1 +(18 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(18 0) routing sp4_v_b_1 <X> lc_trk_g0_1 +(18 0) routing sp4_v_b_9 <X> lc_trk_g0_1 +(18 1) routing bnr_op_1 <X> lc_trk_g0_1 +(18 1) routing sp12_h_r_1 <X> lc_trk_g0_1 +(18 1) routing sp12_h_r_17 <X> lc_trk_g0_1 +(18 1) routing sp4_h_l_4 <X> lc_trk_g0_1 +(18 1) routing sp4_h_r_1 <X> lc_trk_g0_1 +(18 1) routing sp4_r_v_b_34 <X> lc_trk_g0_1 +(18 1) routing sp4_v_b_9 <X> lc_trk_g0_1 +(18 10) routing bnl_op_5 <X> lc_trk_g2_5 +(18 10) routing rgt_op_5 <X> lc_trk_g2_5 +(18 10) routing sp12_v_b_5 <X> lc_trk_g2_5 +(18 10) routing sp4_h_l_32 <X> lc_trk_g2_5 +(18 10) routing sp4_h_r_37 <X> lc_trk_g2_5 +(18 10) routing sp4_v_b_29 <X> lc_trk_g2_5 +(18 10) routing sp4_v_b_37 <X> lc_trk_g2_5 +(18 11) routing bnl_op_5 <X> lc_trk_g2_5 +(18 11) routing sp12_v_b_21 <X> lc_trk_g2_5 +(18 11) routing sp12_v_b_5 <X> lc_trk_g2_5 +(18 11) routing sp4_h_l_16 <X> lc_trk_g2_5 +(18 11) routing sp4_h_l_32 <X> lc_trk_g2_5 +(18 11) routing sp4_r_v_b_37 <X> lc_trk_g2_5 +(18 11) routing sp4_v_b_37 <X> lc_trk_g2_5 +(18 11) routing tnl_op_5 <X> lc_trk_g2_5 +(18 12) routing bnl_op_1 <X> lc_trk_g3_1 +(18 12) routing rgt_op_1 <X> lc_trk_g3_1 +(18 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(18 12) routing sp4_h_l_28 <X> lc_trk_g3_1 +(18 12) routing sp4_h_r_33 <X> lc_trk_g3_1 +(18 12) routing sp4_v_t_12 <X> lc_trk_g3_1 +(18 12) routing sp4_v_t_20 <X> lc_trk_g3_1 +(18 13) routing bnl_op_1 <X> lc_trk_g3_1 +(18 13) routing sp12_v_b_1 <X> lc_trk_g3_1 +(18 13) routing sp12_v_t_14 <X> lc_trk_g3_1 +(18 13) routing sp4_h_l_28 <X> lc_trk_g3_1 +(18 13) routing sp4_h_r_25 <X> lc_trk_g3_1 +(18 13) routing sp4_r_v_b_41 <X> lc_trk_g3_1 +(18 13) routing sp4_v_t_20 <X> lc_trk_g3_1 +(18 13) routing tnl_op_1 <X> lc_trk_g3_1 +(18 14) routing bnl_op_5 <X> lc_trk_g3_5 +(18 14) routing rgt_op_5 <X> lc_trk_g3_5 +(18 14) routing sp12_v_b_5 <X> lc_trk_g3_5 +(18 14) routing sp4_h_l_32 <X> lc_trk_g3_5 +(18 14) routing sp4_h_r_37 <X> lc_trk_g3_5 +(18 14) routing sp4_v_b_29 <X> lc_trk_g3_5 +(18 14) routing sp4_v_b_37 <X> lc_trk_g3_5 +(18 15) routing bnl_op_5 <X> lc_trk_g3_5 +(18 15) routing sp12_v_b_21 <X> lc_trk_g3_5 +(18 15) routing sp12_v_b_5 <X> lc_trk_g3_5 +(18 15) routing sp4_h_l_16 <X> lc_trk_g3_5 +(18 15) routing sp4_h_l_32 <X> lc_trk_g3_5 +(18 15) routing sp4_r_v_b_45 <X> lc_trk_g3_5 +(18 15) routing sp4_v_b_37 <X> lc_trk_g3_5 +(18 15) routing tnl_op_5 <X> lc_trk_g3_5 +(18 2) routing bnr_op_5 <X> lc_trk_g0_5 +(18 2) routing lft_op_5 <X> lc_trk_g0_5 +(18 2) routing sp12_h_r_5 <X> lc_trk_g0_5 +(18 2) routing sp4_h_l_0 <X> lc_trk_g0_5 +(18 2) routing sp4_h_r_21 <X> lc_trk_g0_5 +(18 2) routing sp4_v_b_13 <X> lc_trk_g0_5 +(18 2) routing sp4_v_b_5 <X> lc_trk_g0_5 +(18 3) routing bnr_op_5 <X> lc_trk_g0_5 +(18 3) routing sp12_h_l_18 <X> lc_trk_g0_5 +(18 3) routing sp12_h_r_5 <X> lc_trk_g0_5 +(18 3) routing sp4_h_r_21 <X> lc_trk_g0_5 +(18 3) routing sp4_h_r_5 <X> lc_trk_g0_5 +(18 3) routing sp4_r_v_b_29 <X> lc_trk_g0_5 +(18 3) routing sp4_v_b_13 <X> lc_trk_g0_5 +(18 4) routing bnr_op_1 <X> lc_trk_g1_1 +(18 4) routing lft_op_1 <X> lc_trk_g1_1 +(18 4) routing sp12_h_r_1 <X> lc_trk_g1_1 +(18 4) routing sp4_h_l_4 <X> lc_trk_g1_1 +(18 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(18 4) routing sp4_v_b_1 <X> lc_trk_g1_1 +(18 4) routing sp4_v_b_9 <X> lc_trk_g1_1 +(18 5) routing bnr_op_1 <X> lc_trk_g1_1 +(18 5) routing sp12_h_r_1 <X> lc_trk_g1_1 +(18 5) routing sp12_h_r_17 <X> lc_trk_g1_1 +(18 5) routing sp4_h_l_4 <X> lc_trk_g1_1 +(18 5) routing sp4_h_r_1 <X> lc_trk_g1_1 +(18 5) routing sp4_r_v_b_25 <X> lc_trk_g1_1 +(18 5) routing sp4_v_b_9 <X> lc_trk_g1_1 +(18 6) routing bnr_op_5 <X> lc_trk_g1_5 +(18 6) routing lft_op_5 <X> lc_trk_g1_5 +(18 6) routing sp12_h_r_5 <X> lc_trk_g1_5 +(18 6) routing sp4_h_l_0 <X> lc_trk_g1_5 +(18 6) routing sp4_h_r_21 <X> lc_trk_g1_5 +(18 6) routing sp4_v_b_13 <X> lc_trk_g1_5 +(18 6) routing sp4_v_b_5 <X> lc_trk_g1_5 +(18 7) routing bnr_op_5 <X> lc_trk_g1_5 +(18 7) routing sp12_h_l_18 <X> lc_trk_g1_5 +(18 7) routing sp12_h_r_5 <X> lc_trk_g1_5 +(18 7) routing sp4_h_r_21 <X> lc_trk_g1_5 +(18 7) routing sp4_h_r_5 <X> lc_trk_g1_5 +(18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5 +(18 7) routing sp4_v_b_13 <X> lc_trk_g1_5 +(18 8) routing bnl_op_1 <X> lc_trk_g2_1 +(18 8) routing rgt_op_1 <X> lc_trk_g2_1 +(18 8) routing sp12_v_b_1 <X> lc_trk_g2_1 +(18 8) routing sp4_h_l_28 <X> lc_trk_g2_1 +(18 8) routing sp4_h_r_33 <X> lc_trk_g2_1 +(18 8) routing sp4_v_t_12 <X> lc_trk_g2_1 +(18 8) routing sp4_v_t_20 <X> lc_trk_g2_1 +(18 9) routing bnl_op_1 <X> lc_trk_g2_1 +(18 9) routing sp12_v_b_1 <X> lc_trk_g2_1 +(18 9) routing sp12_v_t_14 <X> lc_trk_g2_1 +(18 9) routing sp4_h_l_28 <X> lc_trk_g2_1 +(18 9) routing sp4_h_r_25 <X> lc_trk_g2_1 +(18 9) routing sp4_r_v_b_33 <X> lc_trk_g2_1 +(18 9) routing sp4_v_t_20 <X> lc_trk_g2_1 +(18 9) routing tnl_op_1 <X> lc_trk_g2_1 +(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_b_3 sp4_v_b_13 +(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_b_12 +(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_t_10 +(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_t_11 +(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_r_2 sp4_h_l_0 +(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_r_12 +(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_l_2 +(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3 +(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_t_4 sp4_v_t_2 +(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_t_3 +(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_b_11 sp4_v_b_17 +(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16 +(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_b_15 sp4_v_b_19 +(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_t_7 +(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_b_19 sp4_v_b_21 +(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_t_9 +(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_r_16 +(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_r_18 sp4_h_r_21 +(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_l_19 sp4_h_l_11 +(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_l_10 +(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_l_11 sp4_h_l_7 +(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_l_13 sp4_h_r_19 +(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_l_15 sp4_h_l_9 +(21 0) routing bnr_op_3 <X> lc_trk_g0_3 +(21 0) routing lft_op_3 <X> lc_trk_g0_3 +(21 0) routing sp12_h_l_0 <X> lc_trk_g0_3 +(21 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(21 0) routing sp4_h_r_19 <X> lc_trk_g0_3 +(21 0) routing sp4_v_b_11 <X> lc_trk_g0_3 +(21 0) routing sp4_v_b_3 <X> lc_trk_g0_3 +(21 1) routing bnr_op_3 <X> lc_trk_g0_3 +(21 1) routing sp12_h_l_0 <X> lc_trk_g0_3 +(21 1) routing sp12_h_l_16 <X> lc_trk_g0_3 +(21 1) routing sp4_h_r_19 <X> lc_trk_g0_3 +(21 1) routing sp4_h_r_3 <X> lc_trk_g0_3 +(21 1) routing sp4_r_v_b_32 <X> lc_trk_g0_3 +(21 1) routing sp4_v_b_11 <X> lc_trk_g0_3 +(21 10) routing bnl_op_7 <X> lc_trk_g2_7 +(21 10) routing rgt_op_7 <X> lc_trk_g2_7 +(21 10) routing sp12_v_t_4 <X> lc_trk_g2_7 +(21 10) routing sp4_h_l_34 <X> lc_trk_g2_7 +(21 10) routing sp4_h_r_39 <X> lc_trk_g2_7 +(21 10) routing sp4_v_b_31 <X> lc_trk_g2_7 +(21 10) routing sp4_v_t_26 <X> lc_trk_g2_7 +(21 11) routing bnl_op_7 <X> lc_trk_g2_7 +(21 11) routing sp12_v_b_23 <X> lc_trk_g2_7 +(21 11) routing sp12_v_t_4 <X> lc_trk_g2_7 +(21 11) routing sp4_h_l_34 <X> lc_trk_g2_7 +(21 11) routing sp4_h_r_31 <X> lc_trk_g2_7 +(21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7 +(21 11) routing sp4_v_t_26 <X> lc_trk_g2_7 +(21 11) routing tnl_op_7 <X> lc_trk_g2_7 +(21 12) routing bnl_op_3 <X> lc_trk_g3_3 +(21 12) routing rgt_op_3 <X> lc_trk_g3_3 +(21 12) routing sp12_v_b_3 <X> lc_trk_g3_3 +(21 12) routing sp4_h_l_22 <X> lc_trk_g3_3 +(21 12) routing sp4_h_r_43 <X> lc_trk_g3_3 +(21 12) routing sp4_v_b_35 <X> lc_trk_g3_3 +(21 12) routing sp4_v_t_14 <X> lc_trk_g3_3 +(21 13) routing bnl_op_3 <X> lc_trk_g3_3 +(21 13) routing sp12_v_b_19 <X> lc_trk_g3_3 +(21 13) routing sp12_v_b_3 <X> lc_trk_g3_3 +(21 13) routing sp4_h_r_27 <X> lc_trk_g3_3 +(21 13) routing sp4_h_r_43 <X> lc_trk_g3_3 +(21 13) routing sp4_r_v_b_43 <X> lc_trk_g3_3 +(21 13) routing sp4_v_b_35 <X> lc_trk_g3_3 +(21 13) routing tnl_op_3 <X> lc_trk_g3_3 +(21 14) routing bnl_op_7 <X> lc_trk_g3_7 +(21 14) routing rgt_op_7 <X> lc_trk_g3_7 +(21 14) routing sp12_v_t_4 <X> lc_trk_g3_7 +(21 14) routing sp4_h_l_34 <X> lc_trk_g3_7 +(21 14) routing sp4_h_r_39 <X> lc_trk_g3_7 +(21 14) routing sp4_v_b_31 <X> lc_trk_g3_7 +(21 14) routing sp4_v_t_26 <X> lc_trk_g3_7 +(21 15) routing bnl_op_7 <X> lc_trk_g3_7 +(21 15) routing sp12_v_b_23 <X> lc_trk_g3_7 +(21 15) routing sp12_v_t_4 <X> lc_trk_g3_7 +(21 15) routing sp4_h_l_34 <X> lc_trk_g3_7 +(21 15) routing sp4_h_r_31 <X> lc_trk_g3_7 +(21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7 +(21 15) routing sp4_v_t_26 <X> lc_trk_g3_7 +(21 15) routing tnl_op_7 <X> lc_trk_g3_7 +(21 2) routing bnr_op_7 <X> lc_trk_g0_7 +(21 2) routing lft_op_7 <X> lc_trk_g0_7 +(21 2) routing sp12_h_l_4 <X> lc_trk_g0_7 +(21 2) routing sp4_h_l_10 <X> lc_trk_g0_7 +(21 2) routing sp4_h_l_2 <X> lc_trk_g0_7 +(21 2) routing sp4_v_b_7 <X> lc_trk_g0_7 +(21 2) routing sp4_v_t_2 <X> lc_trk_g0_7 +(21 3) routing bnr_op_7 <X> lc_trk_g0_7 +(21 3) routing sp12_h_l_20 <X> lc_trk_g0_7 +(21 3) routing sp12_h_l_4 <X> lc_trk_g0_7 +(21 3) routing sp4_h_l_10 <X> lc_trk_g0_7 +(21 3) routing sp4_h_r_7 <X> lc_trk_g0_7 +(21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7 +(21 3) routing sp4_v_t_2 <X> lc_trk_g0_7 +(21 4) routing bnr_op_3 <X> lc_trk_g1_3 +(21 4) routing lft_op_3 <X> lc_trk_g1_3 +(21 4) routing sp12_h_l_0 <X> lc_trk_g1_3 +(21 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(21 4) routing sp4_h_r_19 <X> lc_trk_g1_3 +(21 4) routing sp4_v_b_11 <X> lc_trk_g1_3 +(21 4) routing sp4_v_b_3 <X> lc_trk_g1_3 +(21 5) routing bnr_op_3 <X> lc_trk_g1_3 +(21 5) routing sp12_h_l_0 <X> lc_trk_g1_3 +(21 5) routing sp12_h_l_16 <X> lc_trk_g1_3 +(21 5) routing sp4_h_r_19 <X> lc_trk_g1_3 +(21 5) routing sp4_h_r_3 <X> lc_trk_g1_3 +(21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3 +(21 5) routing sp4_v_b_11 <X> lc_trk_g1_3 +(21 6) routing bnr_op_7 <X> lc_trk_g1_7 +(21 6) routing lft_op_7 <X> lc_trk_g1_7 +(21 6) routing sp12_h_l_4 <X> lc_trk_g1_7 +(21 6) routing sp4_h_l_10 <X> lc_trk_g1_7 +(21 6) routing sp4_h_l_2 <X> lc_trk_g1_7 +(21 6) routing sp4_v_b_7 <X> lc_trk_g1_7 +(21 6) routing sp4_v_t_2 <X> lc_trk_g1_7 +(21 7) routing bnr_op_7 <X> lc_trk_g1_7 +(21 7) routing sp12_h_l_20 <X> lc_trk_g1_7 +(21 7) routing sp12_h_l_4 <X> lc_trk_g1_7 +(21 7) routing sp4_h_l_10 <X> lc_trk_g1_7 +(21 7) routing sp4_h_r_7 <X> lc_trk_g1_7 +(21 7) routing sp4_r_v_b_31 <X> lc_trk_g1_7 +(21 7) routing sp4_v_t_2 <X> lc_trk_g1_7 +(21 8) routing bnl_op_3 <X> lc_trk_g2_3 +(21 8) routing rgt_op_3 <X> lc_trk_g2_3 +(21 8) routing sp12_v_b_3 <X> lc_trk_g2_3 +(21 8) routing sp4_h_l_22 <X> lc_trk_g2_3 +(21 8) routing sp4_h_r_43 <X> lc_trk_g2_3 +(21 8) routing sp4_v_b_35 <X> lc_trk_g2_3 +(21 8) routing sp4_v_t_14 <X> lc_trk_g2_3 +(21 9) routing bnl_op_3 <X> lc_trk_g2_3 +(21 9) routing sp12_v_b_19 <X> lc_trk_g2_3 +(21 9) routing sp12_v_b_3 <X> lc_trk_g2_3 +(21 9) routing sp4_h_r_27 <X> lc_trk_g2_3 +(21 9) routing sp4_h_r_43 <X> lc_trk_g2_3 +(21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3 +(21 9) routing sp4_v_b_35 <X> lc_trk_g2_3 +(21 9) routing tnl_op_3 <X> lc_trk_g2_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_15 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_31 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_13 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_21 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_30 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_35 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_11 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_22 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_14 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_30 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_17 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_9 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_31 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_26 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_26 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_15 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_34 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_39 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_31 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_13 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_30 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_38 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_35 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_10 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_13 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_3 lc_trk_g0_6 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_18 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_10 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_13 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_3 lc_trk_g1_6 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_14 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_30 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_17 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_9 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_26 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_42 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 +(23 0) routing sp12_h_l_16 <X> lc_trk_g0_3 +(23 0) routing sp12_h_r_11 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_19 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_3 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_11 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_19 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_3 <X> lc_trk_g0_3 +(23 1) routing sp12_h_l_9 <X> lc_trk_g0_2 +(23 1) routing sp12_h_r_18 <X> lc_trk_g0_2 +(23 1) routing sp4_h_l_7 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_10 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_10 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_2 <X> lc_trk_g0_2 +(23 1) routing sp4_v_t_7 <X> lc_trk_g0_2 +(23 10) routing sp12_v_b_15 <X> lc_trk_g2_7 +(23 10) routing sp12_v_b_23 <X> lc_trk_g2_7 +(23 10) routing sp4_h_l_34 <X> lc_trk_g2_7 +(23 10) routing sp4_h_r_31 <X> lc_trk_g2_7 +(23 10) routing sp4_h_r_39 <X> lc_trk_g2_7 +(23 10) routing sp4_v_b_31 <X> lc_trk_g2_7 +(23 10) routing sp4_v_t_26 <X> lc_trk_g2_7 +(23 10) routing sp4_v_t_34 <X> lc_trk_g2_7 +(23 11) routing sp12_v_t_13 <X> lc_trk_g2_6 +(23 11) routing sp12_v_t_21 <X> lc_trk_g2_6 +(23 11) routing sp4_h_l_27 <X> lc_trk_g2_6 +(23 11) routing sp4_h_r_30 <X> lc_trk_g2_6 +(23 11) routing sp4_h_r_46 <X> lc_trk_g2_6 +(23 11) routing sp4_v_b_30 <X> lc_trk_g2_6 +(23 11) routing sp4_v_b_38 <X> lc_trk_g2_6 +(23 11) routing sp4_v_t_35 <X> lc_trk_g2_6 +(23 12) routing sp12_v_b_11 <X> lc_trk_g3_3 +(23 12) routing sp12_v_b_19 <X> lc_trk_g3_3 +(23 12) routing sp4_h_l_22 <X> lc_trk_g3_3 +(23 12) routing sp4_h_r_27 <X> lc_trk_g3_3 +(23 12) routing sp4_h_r_43 <X> lc_trk_g3_3 +(23 12) routing sp4_v_b_35 <X> lc_trk_g3_3 +(23 12) routing sp4_v_t_14 <X> lc_trk_g3_3 +(23 12) routing sp4_v_t_30 <X> lc_trk_g3_3 +(23 13) routing sp12_v_t_17 <X> lc_trk_g3_2 +(23 13) routing sp12_v_t_9 <X> lc_trk_g3_2 +(23 13) routing sp4_h_l_31 <X> lc_trk_g3_2 +(23 13) routing sp4_h_r_26 <X> lc_trk_g3_2 +(23 13) routing sp4_h_r_34 <X> lc_trk_g3_2 +(23 13) routing sp4_v_b_26 <X> lc_trk_g3_2 +(23 13) routing sp4_v_b_42 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_23 <X> lc_trk_g3_2 +(23 14) routing sp12_v_b_15 <X> lc_trk_g3_7 +(23 14) routing sp12_v_b_23 <X> lc_trk_g3_7 +(23 14) routing sp4_h_l_34 <X> lc_trk_g3_7 +(23 14) routing sp4_h_r_31 <X> lc_trk_g3_7 +(23 14) routing sp4_h_r_39 <X> lc_trk_g3_7 +(23 14) routing sp4_v_b_31 <X> lc_trk_g3_7 +(23 14) routing sp4_v_t_26 <X> lc_trk_g3_7 +(23 14) routing sp4_v_t_34 <X> lc_trk_g3_7 +(23 15) routing sp12_v_t_13 <X> lc_trk_g3_6 +(23 15) routing sp12_v_t_21 <X> lc_trk_g3_6 +(23 15) routing sp4_h_l_27 <X> lc_trk_g3_6 +(23 15) routing sp4_h_r_30 <X> lc_trk_g3_6 +(23 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(23 15) routing sp4_v_b_30 <X> lc_trk_g3_6 +(23 15) routing sp4_v_b_38 <X> lc_trk_g3_6 +(23 15) routing sp4_v_t_35 <X> lc_trk_g3_6 +(23 2) routing sp12_h_l_12 <X> lc_trk_g0_7 +(23 2) routing sp12_h_l_20 <X> lc_trk_g0_7 +(23 2) routing sp4_h_l_10 <X> lc_trk_g0_7 +(23 2) routing sp4_h_l_2 <X> lc_trk_g0_7 +(23 2) routing sp4_h_r_7 <X> lc_trk_g0_7 +(23 2) routing sp4_v_b_7 <X> lc_trk_g0_7 +(23 2) routing sp4_v_t_10 <X> lc_trk_g0_7 +(23 2) routing sp4_v_t_2 <X> lc_trk_g0_7 +(23 3) routing sp12_h_l_13 <X> lc_trk_g0_6 +(23 3) routing sp12_h_r_22 <X> lc_trk_g0_6 +(23 3) routing sp4_h_l_11 <X> lc_trk_g0_6 +(23 3) routing sp4_h_l_3 <X> lc_trk_g0_6 +(23 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(23 3) routing sp4_v_b_6 <X> lc_trk_g0_6 +(23 3) routing sp4_v_t_11 <X> lc_trk_g0_6 +(23 3) routing sp4_v_t_3 <X> lc_trk_g0_6 +(23 4) routing sp12_h_l_16 <X> lc_trk_g1_3 +(23 4) routing sp12_h_r_11 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_19 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_3 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_11 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_19 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_3 <X> lc_trk_g1_3 +(23 5) routing sp12_h_l_9 <X> lc_trk_g1_2 +(23 5) routing sp12_h_r_18 <X> lc_trk_g1_2 +(23 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_10 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_2 <X> lc_trk_g1_2 +(23 5) routing sp4_v_t_7 <X> lc_trk_g1_2 +(23 6) routing sp12_h_l_12 <X> lc_trk_g1_7 +(23 6) routing sp12_h_l_20 <X> lc_trk_g1_7 +(23 6) routing sp4_h_l_10 <X> lc_trk_g1_7 +(23 6) routing sp4_h_l_2 <X> lc_trk_g1_7 +(23 6) routing sp4_h_r_7 <X> lc_trk_g1_7 +(23 6) routing sp4_v_b_7 <X> lc_trk_g1_7 +(23 6) routing sp4_v_t_10 <X> lc_trk_g1_7 +(23 6) routing sp4_v_t_2 <X> lc_trk_g1_7 +(23 7) routing sp12_h_l_13 <X> lc_trk_g1_6 +(23 7) routing sp12_h_r_22 <X> lc_trk_g1_6 +(23 7) routing sp4_h_l_11 <X> lc_trk_g1_6 +(23 7) routing sp4_h_l_3 <X> lc_trk_g1_6 +(23 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_6 <X> lc_trk_g1_6 +(23 7) routing sp4_v_t_11 <X> lc_trk_g1_6 +(23 7) routing sp4_v_t_3 <X> lc_trk_g1_6 +(23 8) routing sp12_v_b_11 <X> lc_trk_g2_3 +(23 8) routing sp12_v_b_19 <X> lc_trk_g2_3 +(23 8) routing sp4_h_l_22 <X> lc_trk_g2_3 +(23 8) routing sp4_h_r_27 <X> lc_trk_g2_3 +(23 8) routing sp4_h_r_43 <X> lc_trk_g2_3 +(23 8) routing sp4_v_b_35 <X> lc_trk_g2_3 +(23 8) routing sp4_v_t_14 <X> lc_trk_g2_3 +(23 8) routing sp4_v_t_30 <X> lc_trk_g2_3 +(23 9) routing sp12_v_t_17 <X> lc_trk_g2_2 +(23 9) routing sp12_v_t_9 <X> lc_trk_g2_2 +(23 9) routing sp4_h_l_31 <X> lc_trk_g2_2 +(23 9) routing sp4_h_r_26 <X> lc_trk_g2_2 +(23 9) routing sp4_h_r_34 <X> lc_trk_g2_2 +(23 9) routing sp4_v_b_26 <X> lc_trk_g2_2 +(23 9) routing sp4_v_b_42 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_23 <X> lc_trk_g2_2 +(24 0) routing lft_op_3 <X> lc_trk_g0_3 +(24 0) routing sp12_h_l_0 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_19 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_3 <X> lc_trk_g0_3 +(24 0) routing sp4_v_b_19 <X> lc_trk_g0_3 +(24 1) routing sp12_h_r_2 <X> lc_trk_g0_2 +(24 1) routing sp4_h_l_7 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_10 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(24 1) routing sp4_v_t_7 <X> lc_trk_g0_2 +(24 10) routing rgt_op_7 <X> lc_trk_g2_7 +(24 10) routing sp12_v_t_4 <X> lc_trk_g2_7 +(24 10) routing sp4_h_l_34 <X> lc_trk_g2_7 +(24 10) routing sp4_h_r_31 <X> lc_trk_g2_7 +(24 10) routing sp4_h_r_39 <X> lc_trk_g2_7 +(24 10) routing sp4_v_t_34 <X> lc_trk_g2_7 +(24 10) routing tnl_op_7 <X> lc_trk_g2_7 +(24 10) routing tnr_op_7 <X> lc_trk_g2_7 +(24 11) routing rgt_op_6 <X> lc_trk_g2_6 +(24 11) routing sp12_v_b_6 <X> lc_trk_g2_6 +(24 11) routing sp4_h_l_27 <X> lc_trk_g2_6 +(24 11) routing sp4_h_r_30 <X> lc_trk_g2_6 +(24 11) routing sp4_h_r_46 <X> lc_trk_g2_6 +(24 11) routing sp4_v_t_35 <X> lc_trk_g2_6 +(24 11) routing tnl_op_6 <X> lc_trk_g2_6 +(24 11) routing tnr_op_6 <X> lc_trk_g2_6 +(24 12) routing rgt_op_3 <X> lc_trk_g3_3 +(24 12) routing sp12_v_b_3 <X> lc_trk_g3_3 +(24 12) routing sp4_h_l_22 <X> lc_trk_g3_3 +(24 12) routing sp4_h_r_27 <X> lc_trk_g3_3 +(24 12) routing sp4_h_r_43 <X> lc_trk_g3_3 +(24 12) routing sp4_v_t_30 <X> lc_trk_g3_3 +(24 12) routing tnl_op_3 <X> lc_trk_g3_3 +(24 12) routing tnr_op_3 <X> lc_trk_g3_3 +(24 13) routing rgt_op_2 <X> lc_trk_g3_2 +(24 13) routing sp12_v_b_2 <X> lc_trk_g3_2 +(24 13) routing sp4_h_l_31 <X> lc_trk_g3_2 +(24 13) routing sp4_h_r_26 <X> lc_trk_g3_2 +(24 13) routing sp4_h_r_34 <X> lc_trk_g3_2 +(24 13) routing sp4_v_b_42 <X> lc_trk_g3_2 +(24 13) routing tnl_op_2 <X> lc_trk_g3_2 +(24 13) routing tnr_op_2 <X> lc_trk_g3_2 +(24 14) routing rgt_op_7 <X> lc_trk_g3_7 +(24 14) routing sp12_v_t_4 <X> lc_trk_g3_7 +(24 14) routing sp4_h_l_34 <X> lc_trk_g3_7 +(24 14) routing sp4_h_r_31 <X> lc_trk_g3_7 +(24 14) routing sp4_h_r_39 <X> lc_trk_g3_7 +(24 14) routing sp4_v_t_34 <X> lc_trk_g3_7 +(24 14) routing tnl_op_7 <X> lc_trk_g3_7 +(24 14) routing tnr_op_7 <X> lc_trk_g3_7 +(24 15) routing rgt_op_6 <X> lc_trk_g3_6 +(24 15) routing sp12_v_b_6 <X> lc_trk_g3_6 +(24 15) routing sp4_h_l_27 <X> lc_trk_g3_6 +(24 15) routing sp4_h_r_30 <X> lc_trk_g3_6 +(24 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(24 15) routing sp4_v_t_35 <X> lc_trk_g3_6 +(24 15) routing tnl_op_6 <X> lc_trk_g3_6 +(24 15) routing tnr_op_6 <X> lc_trk_g3_6 +(24 2) routing lft_op_7 <X> lc_trk_g0_7 +(24 2) routing sp12_h_l_4 <X> lc_trk_g0_7 +(24 2) routing sp4_h_l_10 <X> lc_trk_g0_7 +(24 2) routing sp4_h_l_2 <X> lc_trk_g0_7 +(24 2) routing sp4_h_r_7 <X> lc_trk_g0_7 +(24 2) routing sp4_v_t_10 <X> lc_trk_g0_7 +(24 3) routing lft_op_6 <X> lc_trk_g0_6 +(24 3) routing sp12_h_l_5 <X> lc_trk_g0_6 +(24 3) routing sp4_h_l_11 <X> lc_trk_g0_6 +(24 3) routing sp4_h_l_3 <X> lc_trk_g0_6 +(24 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(24 3) routing sp4_v_t_11 <X> lc_trk_g0_6 +(24 4) routing lft_op_3 <X> lc_trk_g1_3 +(24 4) routing sp12_h_l_0 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_19 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_3 <X> lc_trk_g1_3 +(24 4) routing sp4_v_b_19 <X> lc_trk_g1_3 +(24 5) routing lft_op_2 <X> lc_trk_g1_2 +(24 5) routing sp12_h_r_2 <X> lc_trk_g1_2 +(24 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(24 5) routing sp4_v_t_7 <X> lc_trk_g1_2 +(24 6) routing lft_op_7 <X> lc_trk_g1_7 +(24 6) routing sp12_h_l_4 <X> lc_trk_g1_7 +(24 6) routing sp4_h_l_10 <X> lc_trk_g1_7 +(24 6) routing sp4_h_l_2 <X> lc_trk_g1_7 +(24 6) routing sp4_h_r_7 <X> lc_trk_g1_7 +(24 6) routing sp4_v_t_10 <X> lc_trk_g1_7 +(24 7) routing lft_op_6 <X> lc_trk_g1_6 +(24 7) routing sp12_h_l_5 <X> lc_trk_g1_6 +(24 7) routing sp4_h_l_11 <X> lc_trk_g1_6 +(24 7) routing sp4_h_l_3 <X> lc_trk_g1_6 +(24 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(24 7) routing sp4_v_t_11 <X> lc_trk_g1_6 +(24 8) routing rgt_op_3 <X> lc_trk_g2_3 +(24 8) routing sp12_v_b_3 <X> lc_trk_g2_3 +(24 8) routing sp4_h_l_22 <X> lc_trk_g2_3 +(24 8) routing sp4_h_r_27 <X> lc_trk_g2_3 +(24 8) routing sp4_h_r_43 <X> lc_trk_g2_3 +(24 8) routing sp4_v_t_30 <X> lc_trk_g2_3 +(24 8) routing tnl_op_3 <X> lc_trk_g2_3 +(24 8) routing tnr_op_3 <X> lc_trk_g2_3 +(24 9) routing rgt_op_2 <X> lc_trk_g2_2 +(24 9) routing sp12_v_b_2 <X> lc_trk_g2_2 +(24 9) routing sp4_h_l_31 <X> lc_trk_g2_2 +(24 9) routing sp4_h_r_26 <X> lc_trk_g2_2 +(24 9) routing sp4_h_r_34 <X> lc_trk_g2_2 +(24 9) routing sp4_v_b_42 <X> lc_trk_g2_2 +(24 9) routing tnl_op_2 <X> lc_trk_g2_2 +(24 9) routing tnr_op_2 <X> lc_trk_g2_2 +(25 0) routing bnr_op_2 <X> lc_trk_g0_2 +(25 0) routing sp12_h_r_2 <X> lc_trk_g0_2 +(25 0) routing sp4_h_l_7 <X> lc_trk_g0_2 +(25 0) routing sp4_h_r_10 <X> lc_trk_g0_2 +(25 0) routing sp4_v_b_10 <X> lc_trk_g0_2 +(25 0) routing sp4_v_b_2 <X> lc_trk_g0_2 +(25 1) routing bnr_op_2 <X> lc_trk_g0_2 +(25 1) routing sp12_h_r_18 <X> lc_trk_g0_2 +(25 1) routing sp12_h_r_2 <X> lc_trk_g0_2 +(25 1) routing sp4_h_l_7 <X> lc_trk_g0_2 +(25 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(25 1) routing sp4_r_v_b_33 <X> lc_trk_g0_2 +(25 1) routing sp4_v_b_10 <X> lc_trk_g0_2 +(25 10) routing bnl_op_6 <X> lc_trk_g2_6 +(25 10) routing rgt_op_6 <X> lc_trk_g2_6 +(25 10) routing sp12_v_b_6 <X> lc_trk_g2_6 +(25 10) routing sp4_h_l_27 <X> lc_trk_g2_6 +(25 10) routing sp4_h_r_46 <X> lc_trk_g2_6 +(25 10) routing sp4_v_b_30 <X> lc_trk_g2_6 +(25 10) routing sp4_v_b_38 <X> lc_trk_g2_6 +(25 11) routing bnl_op_6 <X> lc_trk_g2_6 +(25 11) routing sp12_v_b_6 <X> lc_trk_g2_6 +(25 11) routing sp12_v_t_21 <X> lc_trk_g2_6 +(25 11) routing sp4_h_r_30 <X> lc_trk_g2_6 +(25 11) routing sp4_h_r_46 <X> lc_trk_g2_6 +(25 11) routing sp4_r_v_b_38 <X> lc_trk_g2_6 +(25 11) routing sp4_v_b_38 <X> lc_trk_g2_6 +(25 11) routing tnl_op_6 <X> lc_trk_g2_6 +(25 12) routing bnl_op_2 <X> lc_trk_g3_2 +(25 12) routing rgt_op_2 <X> lc_trk_g3_2 +(25 12) routing sp12_v_b_2 <X> lc_trk_g3_2 +(25 12) routing sp4_h_l_31 <X> lc_trk_g3_2 +(25 12) routing sp4_h_r_34 <X> lc_trk_g3_2 +(25 12) routing sp4_v_b_26 <X> lc_trk_g3_2 +(25 12) routing sp4_v_t_23 <X> lc_trk_g3_2 +(25 13) routing bnl_op_2 <X> lc_trk_g3_2 +(25 13) routing sp12_v_b_2 <X> lc_trk_g3_2 +(25 13) routing sp12_v_t_17 <X> lc_trk_g3_2 +(25 13) routing sp4_h_l_31 <X> lc_trk_g3_2 +(25 13) routing sp4_h_r_26 <X> lc_trk_g3_2 +(25 13) routing sp4_r_v_b_42 <X> lc_trk_g3_2 +(25 13) routing sp4_v_t_23 <X> lc_trk_g3_2 +(25 13) routing tnl_op_2 <X> lc_trk_g3_2 +(25 14) routing bnl_op_6 <X> lc_trk_g3_6 +(25 14) routing rgt_op_6 <X> lc_trk_g3_6 +(25 14) routing sp12_v_b_6 <X> lc_trk_g3_6 +(25 14) routing sp4_h_l_27 <X> lc_trk_g3_6 +(25 14) routing sp4_h_r_46 <X> lc_trk_g3_6 +(25 14) routing sp4_v_b_30 <X> lc_trk_g3_6 +(25 14) routing sp4_v_b_38 <X> lc_trk_g3_6 +(25 15) routing bnl_op_6 <X> lc_trk_g3_6 +(25 15) routing sp12_v_b_6 <X> lc_trk_g3_6 +(25 15) routing sp12_v_t_21 <X> lc_trk_g3_6 +(25 15) routing sp4_h_r_30 <X> lc_trk_g3_6 +(25 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(25 15) routing sp4_r_v_b_46 <X> lc_trk_g3_6 +(25 15) routing sp4_v_b_38 <X> lc_trk_g3_6 +(25 15) routing tnl_op_6 <X> lc_trk_g3_6 +(25 2) routing bnr_op_6 <X> lc_trk_g0_6 +(25 2) routing lft_op_6 <X> lc_trk_g0_6 +(25 2) routing sp12_h_l_5 <X> lc_trk_g0_6 +(25 2) routing sp4_h_l_11 <X> lc_trk_g0_6 +(25 2) routing sp4_h_l_3 <X> lc_trk_g0_6 +(25 2) routing sp4_v_b_6 <X> lc_trk_g0_6 +(25 2) routing sp4_v_t_3 <X> lc_trk_g0_6 +(25 3) routing bnr_op_6 <X> lc_trk_g0_6 +(25 3) routing sp12_h_l_5 <X> lc_trk_g0_6 +(25 3) routing sp12_h_r_22 <X> lc_trk_g0_6 +(25 3) routing sp4_h_l_11 <X> lc_trk_g0_6 +(25 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(25 3) routing sp4_r_v_b_30 <X> lc_trk_g0_6 +(25 3) routing sp4_v_t_3 <X> lc_trk_g0_6 +(25 4) routing bnr_op_2 <X> lc_trk_g1_2 +(25 4) routing lft_op_2 <X> lc_trk_g1_2 +(25 4) routing sp12_h_r_2 <X> lc_trk_g1_2 +(25 4) routing sp4_h_l_7 <X> lc_trk_g1_2 +(25 4) routing sp4_h_r_10 <X> lc_trk_g1_2 +(25 4) routing sp4_v_b_10 <X> lc_trk_g1_2 +(25 4) routing sp4_v_b_2 <X> lc_trk_g1_2 +(25 5) routing bnr_op_2 <X> lc_trk_g1_2 +(25 5) routing sp12_h_r_18 <X> lc_trk_g1_2 +(25 5) routing sp12_h_r_2 <X> lc_trk_g1_2 +(25 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(25 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(25 5) routing sp4_r_v_b_26 <X> lc_trk_g1_2 +(25 5) routing sp4_v_b_10 <X> lc_trk_g1_2 +(25 6) routing bnr_op_6 <X> lc_trk_g1_6 +(25 6) routing lft_op_6 <X> lc_trk_g1_6 +(25 6) routing sp12_h_l_5 <X> lc_trk_g1_6 +(25 6) routing sp4_h_l_11 <X> lc_trk_g1_6 +(25 6) routing sp4_h_l_3 <X> lc_trk_g1_6 +(25 6) routing sp4_v_b_6 <X> lc_trk_g1_6 +(25 6) routing sp4_v_t_3 <X> lc_trk_g1_6 +(25 7) routing bnr_op_6 <X> lc_trk_g1_6 +(25 7) routing sp12_h_l_5 <X> lc_trk_g1_6 +(25 7) routing sp12_h_r_22 <X> lc_trk_g1_6 +(25 7) routing sp4_h_l_11 <X> lc_trk_g1_6 +(25 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6 +(25 7) routing sp4_v_t_3 <X> lc_trk_g1_6 +(25 8) routing bnl_op_2 <X> lc_trk_g2_2 +(25 8) routing rgt_op_2 <X> lc_trk_g2_2 +(25 8) routing sp12_v_b_2 <X> lc_trk_g2_2 +(25 8) routing sp4_h_l_31 <X> lc_trk_g2_2 +(25 8) routing sp4_h_r_34 <X> lc_trk_g2_2 +(25 8) routing sp4_v_b_26 <X> lc_trk_g2_2 +(25 8) routing sp4_v_t_23 <X> lc_trk_g2_2 +(25 9) routing bnl_op_2 <X> lc_trk_g2_2 +(25 9) routing sp12_v_b_2 <X> lc_trk_g2_2 +(25 9) routing sp12_v_t_17 <X> lc_trk_g2_2 +(25 9) routing sp4_h_l_31 <X> lc_trk_g2_2 +(25 9) routing sp4_h_r_26 <X> lc_trk_g2_2 +(25 9) routing sp4_r_v_b_34 <X> lc_trk_g2_2 +(25 9) routing sp4_v_t_23 <X> lc_trk_g2_2 +(25 9) routing tnl_op_2 <X> lc_trk_g2_2 +(26 0) routing lc_trk_g0_4 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g0_6 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_5 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_7 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_4 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_6 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_5 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_2 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_6 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_3 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_7 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_2 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_6 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_3 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(27 0) routing lc_trk_g1_0 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(27 1) routing lc_trk_g1_1 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_3 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_5 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_7 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_1 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_3 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_5 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(27 10) routing lc_trk_g1_1 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(27 12) routing lc_trk_g1_0 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(27 14) routing lc_trk_g1_1 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(27 2) routing lc_trk_g1_1 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(27 4) routing lc_trk_g1_0 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(27 6) routing lc_trk_g1_1 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(27 8) routing lc_trk_g1_0 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(28 0) routing lc_trk_g2_1 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(28 1) routing lc_trk_g2_0 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_2 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_4 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_6 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_1 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_3 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_5 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(28 10) routing lc_trk_g2_0 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(28 12) routing lc_trk_g2_1 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(28 14) routing lc_trk_g2_0 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(28 2) routing lc_trk_g2_0 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(28 4) routing lc_trk_g2_1 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(28 6) routing lc_trk_g2_0 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(28 8) routing lc_trk_g2_1 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_6 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_6 wire_mult/lc_0/in_1 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_7 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_7 wire_mult/lc_0/in_0 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_7 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_7 wire_mult/lc_5/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_6 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_6 wire_mult/lc_6/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_7 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_7 wire_mult/lc_7/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_7 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_7 wire_mult/lc_1/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_6 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_6 wire_mult/lc_2/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_7 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_7 wire_mult/lc_3/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_6 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_6 wire_mult/lc_4/in_1 +(3 0) routing sp12_h_r_0 <X> sp12_v_b_0 +(3 0) routing sp12_v_t_23 <X> sp12_v_b_0 +(3 1) routing sp12_h_l_23 <X> sp12_v_b_0 +(3 1) routing sp12_h_r_0 <X> sp12_v_b_0 +(3 10) routing sp12_v_t_22 <X> sp12_h_l_22 +(3 11) routing sp12_v_b_1 <X> sp12_h_l_22 +(3 12) routing sp12_v_b_1 <X> sp12_h_r_1 +(3 12) routing sp12_v_t_22 <X> sp12_h_r_1 +(3 13) routing sp12_v_b_1 <X> sp12_h_r_1 +(3 14) routing sp12_h_r_1 <X> sp12_v_t_22 +(3 14) routing sp12_v_b_1 <X> sp12_v_t_22 +(3 15) routing sp12_h_l_22 <X> sp12_v_t_22 +(3 15) routing sp12_h_r_1 <X> sp12_v_t_22 +(3 2) routing sp12_h_r_0 <X> sp12_h_l_23 +(3 2) routing sp12_v_t_23 <X> sp12_h_l_23 +(3 3) routing sp12_h_r_0 <X> sp12_h_l_23 +(3 3) routing sp12_v_b_0 <X> sp12_h_l_23 +(3 4) routing sp12_v_b_0 <X> sp12_h_r_0 +(3 4) routing sp12_v_t_23 <X> sp12_h_r_0 +(3 5) routing sp12_h_l_23 <X> sp12_h_r_0 +(3 5) routing sp12_v_b_0 <X> sp12_h_r_0 +(3 6) routing sp12_h_r_0 <X> sp12_v_t_23 +(3 6) routing sp12_v_b_0 <X> sp12_v_t_23 +(3 7) routing sp12_h_l_23 <X> sp12_v_t_23 +(3 7) routing sp12_h_r_0 <X> sp12_v_t_23 +(3 8) routing sp12_h_r_1 <X> sp12_v_b_1 +(3 8) routing sp12_v_t_22 <X> sp12_v_b_1 +(3 9) routing sp12_h_l_22 <X> sp12_v_b_1 +(3 9) routing sp12_h_r_1 <X> sp12_v_b_1 +(30 0) routing lc_trk_g0_5 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_3 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(30 10) routing lc_trk_g0_4 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_2 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(30 12) routing lc_trk_g0_5 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_3 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(30 14) routing lc_trk_g0_4 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_2 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(30 2) routing lc_trk_g0_4 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_2 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(30 4) routing lc_trk_g0_5 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_3 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(30 6) routing lc_trk_g0_4 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_2 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(30 8) routing lc_trk_g0_5 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_3 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(31 0) routing lc_trk_g0_5 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_3 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(31 10) routing lc_trk_g0_4 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_2 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(31 12) routing lc_trk_g0_5 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_3 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(31 14) routing lc_trk_g0_4 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_2 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(31 2) routing lc_trk_g0_4 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_2 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(31 4) routing lc_trk_g0_5 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_3 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(31 6) routing lc_trk_g0_4 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_2 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(31 8) routing lc_trk_g0_5 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_3 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_6 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_1 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_6 wire_mult/lc_0/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_7 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_0 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_7 wire_mult/lc_5/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_6 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_1 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_6 wire_mult/lc_6/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_7 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_0 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_7 wire_mult/lc_7/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_7 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_0 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_7 wire_mult/lc_1/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_6 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_1 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_6 wire_mult/lc_2/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_7 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_0 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_7 wire_mult/lc_3/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_6 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_1 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_6 wire_mult/lc_4/in_3 +(33 0) routing lc_trk_g2_1 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(33 10) routing lc_trk_g2_0 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(33 12) routing lc_trk_g2_1 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(33 14) routing lc_trk_g2_0 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(33 2) routing lc_trk_g2_0 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(33 4) routing lc_trk_g2_1 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(33 6) routing lc_trk_g2_0 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(33 8) routing lc_trk_g2_1 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(34 0) routing lc_trk_g1_0 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(34 10) routing lc_trk_g1_1 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(34 12) routing lc_trk_g1_0 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(34 14) routing lc_trk_g1_1 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(34 2) routing lc_trk_g1_1 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(34 4) routing lc_trk_g1_0 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(34 6) routing lc_trk_g1_1 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(34 8) routing lc_trk_g1_0 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(36 0) LC_0 Logic Functioning bit +(36 1) LC_0 Logic Functioning bit +(36 10) LC_5 Logic Functioning bit +(36 11) LC_5 Logic Functioning bit +(36 12) LC_6 Logic Functioning bit +(36 13) LC_6 Logic Functioning bit +(36 14) LC_7 Logic Functioning bit +(36 15) LC_7 Logic Functioning bit +(36 2) LC_1 Logic Functioning bit +(36 3) LC_1 Logic Functioning bit +(36 4) LC_2 Logic Functioning bit +(36 5) LC_2 Logic Functioning bit +(36 6) LC_3 Logic Functioning bit +(36 7) LC_3 Logic Functioning bit +(36 8) LC_4 Logic Functioning bit +(36 9) LC_4 Logic Functioning bit +(37 0) LC_0 Logic Functioning bit +(37 1) LC_0 Logic Functioning bit +(37 10) LC_5 Logic Functioning bit +(37 11) LC_5 Logic Functioning bit +(37 12) LC_6 Logic Functioning bit +(37 13) LC_6 Logic Functioning bit +(37 14) LC_7 Logic Functioning bit +(37 15) LC_7 Logic Functioning bit +(37 2) LC_1 Logic Functioning bit +(37 3) LC_1 Logic Functioning bit +(37 4) LC_2 Logic Functioning bit +(37 5) LC_2 Logic Functioning bit +(37 6) LC_3 Logic Functioning bit +(37 7) LC_3 Logic Functioning bit +(37 8) LC_4 Logic Functioning bit +(37 9) LC_4 Logic Functioning bit +(4 0) routing sp4_h_l_37 <X> sp4_v_b_0 +(4 0) routing sp4_h_l_43 <X> sp4_v_b_0 +(4 0) routing sp4_v_t_37 <X> sp4_v_b_0 +(4 0) routing sp4_v_t_41 <X> sp4_v_b_0 +(4 1) routing sp4_h_l_41 <X> sp4_h_r_0 +(4 1) routing sp4_h_l_44 <X> sp4_h_r_0 +(4 1) routing sp4_v_b_6 <X> sp4_h_r_0 +(4 1) routing sp4_v_t_42 <X> sp4_h_r_0 +(4 10) routing sp4_h_r_0 <X> sp4_v_t_43 +(4 10) routing sp4_h_r_6 <X> sp4_v_t_43 +(4 10) routing sp4_v_b_10 <X> sp4_v_t_43 +(4 10) routing sp4_v_b_6 <X> sp4_v_t_43 +(4 11) routing sp4_h_r_10 <X> sp4_h_l_43 +(4 11) routing sp4_v_b_1 <X> sp4_h_l_43 +(4 11) routing sp4_v_t_37 <X> sp4_h_l_43 +(4 12) routing sp4_h_l_38 <X> sp4_v_b_9 +(4 12) routing sp4_h_l_44 <X> sp4_v_b_9 +(4 12) routing sp4_v_t_36 <X> sp4_v_b_9 +(4 12) routing sp4_v_t_44 <X> sp4_v_b_9 +(4 13) routing sp4_h_l_36 <X> sp4_h_r_9 +(4 13) routing sp4_v_b_3 <X> sp4_h_r_9 +(4 13) routing sp4_v_t_41 <X> sp4_h_r_9 +(4 14) routing sp4_h_r_3 <X> sp4_v_t_44 +(4 14) routing sp4_h_r_9 <X> sp4_v_t_44 +(4 14) routing sp4_v_b_1 <X> sp4_v_t_44 +(4 14) routing sp4_v_b_9 <X> sp4_v_t_44 +(4 15) routing sp4_h_r_6 <X> sp4_h_l_44 +(4 15) routing sp4_v_b_4 <X> sp4_h_l_44 +(4 15) routing sp4_v_t_38 <X> sp4_h_l_44 +(4 2) routing sp4_h_r_0 <X> sp4_v_t_37 +(4 2) routing sp4_h_r_6 <X> sp4_v_t_37 +(4 2) routing sp4_v_b_0 <X> sp4_v_t_37 +(4 2) routing sp4_v_b_4 <X> sp4_v_t_37 +(4 3) routing sp4_h_r_4 <X> sp4_h_l_37 +(4 3) routing sp4_h_r_9 <X> sp4_h_l_37 +(4 3) routing sp4_v_b_7 <X> sp4_h_l_37 +(4 3) routing sp4_v_t_43 <X> sp4_h_l_37 +(4 4) routing sp4_h_l_38 <X> sp4_v_b_3 +(4 4) routing sp4_h_l_44 <X> sp4_v_b_3 +(4 4) routing sp4_v_t_38 <X> sp4_v_b_3 +(4 4) routing sp4_v_t_42 <X> sp4_v_b_3 +(4 5) routing sp4_v_b_9 <X> sp4_h_r_3 +(4 5) routing sp4_v_t_47 <X> sp4_h_r_3 +(4 6) routing sp4_h_r_3 <X> sp4_v_t_38 +(4 6) routing sp4_h_r_9 <X> sp4_v_t_38 +(4 6) routing sp4_v_b_3 <X> sp4_v_t_38 +(4 6) routing sp4_v_b_7 <X> sp4_v_t_38 +(4 7) routing sp4_h_r_0 <X> sp4_h_l_38 +(4 7) routing sp4_v_b_10 <X> sp4_h_l_38 +(4 7) routing sp4_v_t_44 <X> sp4_h_l_38 +(4 8) routing sp4_h_l_37 <X> sp4_v_b_6 +(4 8) routing sp4_h_l_43 <X> sp4_v_b_6 +(4 8) routing sp4_v_t_43 <X> sp4_v_b_6 +(4 8) routing sp4_v_t_47 <X> sp4_v_b_6 +(4 9) routing sp4_h_l_47 <X> sp4_h_r_6 +(4 9) routing sp4_v_b_0 <X> sp4_h_r_6 +(4 9) routing sp4_v_t_36 <X> sp4_h_r_6 +(42 0) LC_0 Logic Functioning bit +(42 1) LC_0 Logic Functioning bit +(42 10) LC_5 Logic Functioning bit +(42 11) LC_5 Logic Functioning bit +(42 12) LC_6 Logic Functioning bit +(42 13) LC_6 Logic Functioning bit +(42 14) LC_7 Logic Functioning bit +(42 15) LC_7 Logic Functioning bit +(42 2) LC_1 Logic Functioning bit +(42 3) LC_1 Logic Functioning bit +(42 4) LC_2 Logic Functioning bit +(42 5) LC_2 Logic Functioning bit +(42 6) LC_3 Logic Functioning bit +(42 7) LC_3 Logic Functioning bit +(42 8) LC_4 Logic Functioning bit +(42 9) LC_4 Logic Functioning bit +(43 0) LC_0 Logic Functioning bit +(43 1) LC_0 Logic Functioning bit +(43 10) LC_5 Logic Functioning bit +(43 11) LC_5 Logic Functioning bit +(43 12) LC_6 Logic Functioning bit +(43 13) LC_6 Logic Functioning bit +(43 14) LC_7 Logic Functioning bit +(43 15) LC_7 Logic Functioning bit +(43 2) LC_1 Logic Functioning bit +(43 3) LC_1 Logic Functioning bit +(43 4) LC_2 Logic Functioning bit +(43 5) LC_2 Logic Functioning bit +(43 6) LC_3 Logic Functioning bit +(43 7) LC_3 Logic Functioning bit +(43 8) LC_4 Logic Functioning bit +(43 9) LC_4 Logic Functioning bit +(46 0) Enable bit of Mux _out_links/OutMux7_0 => wire_mult/mult/O_8 sp4_h_r_16 +(46 1) Enable bit of Mux _out_links/OutMux6_0 => wire_mult/mult/O_8 sp4_h_r_0 +(46 10) Enable bit of Mux _out_links/OutMux7_5 => wire_mult/mult/O_13 sp4_h_r_26 +(46 11) Enable bit of Mux _out_links/OutMux6_5 => wire_mult/mult/O_13 sp4_h_r_10 +(46 12) Enable bit of Mux _out_links/OutMux7_6 => wire_mult/mult/O_14 sp4_h_l_17 +(46 13) Enable bit of Mux _out_links/OutMux6_6 => wire_mult/mult/O_14 sp4_h_r_12 +(46 14) Enable bit of Mux _out_links/OutMux7_7 => wire_mult/mult/O_15 sp4_h_r_30 +(46 15) Enable bit of Mux _out_links/OutMux6_7 => wire_mult/mult/O_15 sp4_h_l_3 +(46 2) Enable bit of Mux _out_links/OutMux7_1 => wire_mult/mult/O_9 sp4_h_l_7 +(46 3) Enable bit of Mux _out_links/OutMux6_1 => wire_mult/mult/O_9 sp4_h_r_2 +(46 4) Enable bit of Mux _out_links/OutMux7_2 => wire_mult/mult/O_10 sp4_h_l_9 +(46 5) Enable bit of Mux _out_links/OutMux6_2 => wire_mult/mult/O_10 sp4_h_r_4 +(46 6) Enable bit of Mux _out_links/OutMux7_3 => wire_mult/mult/O_11 sp4_h_l_11 +(46 7) Enable bit of Mux _out_links/OutMux6_3 => wire_mult/mult/O_11 sp4_h_r_6 +(46 8) Enable bit of Mux _out_links/OutMux7_4 => wire_mult/mult/O_12 sp4_h_r_24 +(46 9) Enable bit of Mux _out_links/OutMux6_4 => wire_mult/mult/O_12 sp4_h_r_8 +(47 0) Enable bit of Mux _out_links/OutMux5_0 => wire_mult/mult/O_8 sp12_h_r_8 +(47 1) Enable bit of Mux _out_links/OutMux8_0 => wire_mult/mult/O_8 sp4_h_l_21 +(47 10) Enable bit of Mux _out_links/OutMux4_5 => wire_mult/mult/O_13 sp12_h_r_2 +(47 11) Enable bit of Mux _out_links/OutMux8_5 => wire_mult/mult/O_13 sp4_h_l_31 +(47 12) Enable bit of Mux _out_links/OutMux4_6 => wire_mult/mult/O_14 sp12_h_l_3 +(47 13) Enable bit of Mux _out_links/OutMux8_6 => wire_mult/mult/O_14 sp4_h_r_44 +(47 14) Enable bit of Mux _out_links/OutMux4_7 => wire_mult/mult/O_15 sp12_h_l_5 +(47 15) Enable bit of Mux _out_links/OutMux8_7 => wire_mult/mult/O_15 sp4_h_r_46 +(47 2) Enable bit of Mux _out_links/OutMux5_1 => wire_mult/mult/O_9 sp12_h_l_9 +(47 3) Enable bit of Mux _out_links/OutMux8_1 => wire_mult/mult/O_9 sp4_h_r_34 +(47 4) Enable bit of Mux _out_links/OutMux5_2 => wire_mult/mult/O_10 sp12_h_l_11 +(47 5) Enable bit of Mux _out_links/OutMux8_2 => wire_mult/mult/O_10 sp4_h_r_36 +(47 6) Enable bit of Mux _out_links/OutMux5_3 => wire_mult/mult/O_11 sp12_h_l_13 +(47 7) Enable bit of Mux _out_links/OutMux8_3 => wire_mult/mult/O_11 sp4_h_l_27 +(47 8) Enable bit of Mux _out_links/OutMux4_4 => wire_mult/mult/O_12 sp12_h_r_0 +(47 9) Enable bit of Mux _out_links/OutMux8_4 => wire_mult/mult/O_12 sp4_h_r_40 +(48 0) Enable bit of Mux _out_links/OutMux0_0 => wire_mult/mult/O_8 sp4_v_b_0 +(48 1) Enable bit of Mux _out_links/OutMux1_0 => wire_mult/mult/O_8 sp4_v_b_16 +(48 10) Enable bit of Mux _out_links/OutMux5_5 => wire_mult/mult/O_13 sp12_h_r_18 +(48 11) Enable bit of Mux _out_links/OutMux0_5 => wire_mult/mult/O_13 sp4_v_b_10 +(48 12) Enable bit of Mux _out_links/OutMux5_6 => wire_mult/mult/O_14 sp12_h_l_19 +(48 13) Enable bit of Mux _out_links/OutMux0_6 => wire_mult/mult/O_14 sp4_v_b_12 +(48 14) Enable bit of Mux _out_links/OutMux5_7 => wire_mult/mult/O_15 sp12_h_r_22 +(48 15) Enable bit of Mux _out_links/OutMux0_7 => wire_mult/mult/O_15 sp4_v_t_3 +(48 2) Enable bit of Mux _out_links/OutMux0_1 => wire_mult/mult/O_9 sp4_v_b_2 +(48 3) Enable bit of Mux _out_links/OutMux1_1 => wire_mult/mult/O_9 sp4_v_t_7 +(48 4) Enable bit of Mux _out_links/OutMux0_2 => wire_mult/mult/O_10 sp4_v_b_4 +(48 5) Enable bit of Mux _out_links/OutMux1_2 => wire_mult/mult/O_10 sp4_v_t_9 +(48 6) Enable bit of Mux _out_links/OutMux0_3 => wire_mult/mult/O_11 sp4_v_b_6 +(48 7) Enable bit of Mux _out_links/OutMux1_3 => wire_mult/mult/O_11 sp4_v_t_11 +(48 8) Enable bit of Mux _out_links/OutMux5_4 => wire_mult/mult/O_12 sp12_h_l_15 +(48 9) Enable bit of Mux _out_links/OutMux0_4 => wire_mult/mult/O_12 sp4_v_b_8 +(5 0) routing sp4_h_l_44 <X> sp4_h_r_0 +(5 0) routing sp4_v_b_0 <X> sp4_h_r_0 +(5 0) routing sp4_v_b_6 <X> sp4_h_r_0 +(5 0) routing sp4_v_t_37 <X> sp4_h_r_0 +(5 1) routing sp4_h_l_37 <X> sp4_v_b_0 +(5 1) routing sp4_h_l_43 <X> sp4_v_b_0 +(5 1) routing sp4_h_r_0 <X> sp4_v_b_0 +(5 1) routing sp4_v_t_44 <X> sp4_v_b_0 +(5 10) routing sp4_v_b_6 <X> sp4_h_l_43 +(5 10) routing sp4_v_t_37 <X> sp4_h_l_43 +(5 10) routing sp4_v_t_43 <X> sp4_h_l_43 +(5 11) routing sp4_h_l_43 <X> sp4_v_t_43 +(5 11) routing sp4_h_r_0 <X> sp4_v_t_43 +(5 11) routing sp4_h_r_6 <X> sp4_v_t_43 +(5 11) routing sp4_v_b_3 <X> sp4_v_t_43 +(5 12) routing sp4_v_b_3 <X> sp4_h_r_9 +(5 12) routing sp4_v_b_9 <X> sp4_h_r_9 +(5 12) routing sp4_v_t_44 <X> sp4_h_r_9 +(5 13) routing sp4_h_l_38 <X> sp4_v_b_9 +(5 13) routing sp4_h_l_44 <X> sp4_v_b_9 +(5 13) routing sp4_h_r_9 <X> sp4_v_b_9 +(5 13) routing sp4_v_t_43 <X> sp4_v_b_9 +(5 14) routing sp4_h_r_6 <X> sp4_h_l_44 +(5 14) routing sp4_v_b_9 <X> sp4_h_l_44 +(5 14) routing sp4_v_t_38 <X> sp4_h_l_44 +(5 14) routing sp4_v_t_44 <X> sp4_h_l_44 +(5 15) routing sp4_h_l_44 <X> sp4_v_t_44 +(5 15) routing sp4_h_r_3 <X> sp4_v_t_44 +(5 15) routing sp4_h_r_9 <X> sp4_v_t_44 +(5 15) routing sp4_v_b_6 <X> sp4_v_t_44 +(5 2) routing sp4_h_r_9 <X> sp4_h_l_37 +(5 2) routing sp4_v_b_0 <X> sp4_h_l_37 +(5 2) routing sp4_v_t_37 <X> sp4_h_l_37 +(5 2) routing sp4_v_t_43 <X> sp4_h_l_37 +(5 3) routing sp4_h_l_37 <X> sp4_v_t_37 +(5 3) routing sp4_h_r_0 <X> sp4_v_t_37 +(5 3) routing sp4_h_r_6 <X> sp4_v_t_37 +(5 3) routing sp4_v_b_9 <X> sp4_v_t_37 +(5 4) routing sp4_v_b_3 <X> sp4_h_r_3 +(5 4) routing sp4_v_b_9 <X> sp4_h_r_3 +(5 4) routing sp4_v_t_38 <X> sp4_h_r_3 +(5 5) routing sp4_h_l_38 <X> sp4_v_b_3 +(5 5) routing sp4_h_l_44 <X> sp4_v_b_3 +(5 5) routing sp4_h_r_3 <X> sp4_v_b_3 +(5 5) routing sp4_v_t_37 <X> sp4_v_b_3 +(5 6) routing sp4_h_r_0 <X> sp4_h_l_38 +(5 6) routing sp4_v_b_3 <X> sp4_h_l_38 +(5 6) routing sp4_v_t_38 <X> sp4_h_l_38 +(5 6) routing sp4_v_t_44 <X> sp4_h_l_38 +(5 7) routing sp4_h_l_38 <X> sp4_v_t_38 +(5 7) routing sp4_h_r_3 <X> sp4_v_t_38 +(5 7) routing sp4_h_r_9 <X> sp4_v_t_38 +(5 7) routing sp4_v_b_0 <X> sp4_v_t_38 +(5 8) routing sp4_v_b_0 <X> sp4_h_r_6 +(5 8) routing sp4_v_b_6 <X> sp4_h_r_6 +(5 8) routing sp4_v_t_43 <X> sp4_h_r_6 +(5 9) routing sp4_h_l_37 <X> sp4_v_b_6 +(5 9) routing sp4_h_l_43 <X> sp4_v_b_6 +(5 9) routing sp4_h_r_6 <X> sp4_v_b_6 +(5 9) routing sp4_v_t_38 <X> sp4_v_b_6 +(50 0) Cascade buffer Enable bit: MULT1_LC00_inmux02_5 +(50 10) Cascade buffer Enable bit: MULT1_LC05_inmux02_5 +(50 12) Cascade buffer Enable bit: MULT1_LC06_inmux02_5 +(50 14) Cascade buffer Enable bit: MULT1_LC07_inmux02_5 +(50 2) Cascade buffer Enable bit: MULT1_LC01_inmux02_5 +(50 4) Cascade buffer Enable bit: MULT1_LC02_inmux02_5 +(50 6) Cascade buffer Enable bit: MULT1_LC03_inmux02_5 +(50 8) Cascade buffer Enable bit: MULT1_LC04_inmux02_5 +(51 0) Enable bit of Mux _out_links/OutMux3_0 => wire_mult/mult/O_8 sp12_v_b_0 +(51 1) Enable bit of Mux _out_links/OutMux2_0 => wire_mult/mult/O_8 sp4_v_t_21 +(51 10) Enable bit of Mux _out_links/OutMux2_5 => wire_mult/mult/O_13 sp4_v_b_42 +(51 11) Enable bit of Mux _out_links/OutMux1_5 => wire_mult/mult/O_13 sp4_v_b_26 +(51 12) Enable bit of Mux _out_links/OutMux2_6 => wire_mult/mult/O_14 sp4_v_t_33 +(51 13) Enable bit of Mux _out_links/OutMux1_6 => wire_mult/mult/O_14 sp4_v_t_17 +(51 14) Enable bit of Mux _out_links/OutMux2_7 => wire_mult/mult/O_15 sp4_v_t_35 +(51 15) Enable bit of Mux _out_links/OutMux1_7 => wire_mult/mult/O_15 sp4_v_b_30 +(51 2) Enable bit of Mux _out_links/OutMux3_1 => wire_mult/mult/O_9 sp12_v_b_2 +(51 3) Enable bit of Mux _out_links/OutMux2_1 => wire_mult/mult/O_9 sp4_v_t_23 +(51 4) Enable bit of Mux _out_links/OutMux3_2 => wire_mult/mult/O_10 sp12_v_t_3 +(51 5) Enable bit of Mux _out_links/OutMux2_2 => wire_mult/mult/O_10 sp4_v_t_25 +(51 6) Enable bit of Mux _out_links/OutMux3_3 => wire_mult/mult/O_11 sp12_v_b_6 +(51 7) Enable bit of Mux _out_links/OutMux2_3 => wire_mult/mult/O_11 sp4_v_b_38 +(51 8) Enable bit of Mux _out_links/OutMux2_4 => wire_mult/mult/O_12 sp4_v_t_29 +(51 9) Enable bit of Mux _out_links/OutMux1_4 => wire_mult/mult/O_12 sp4_v_b_24 +(52 0) Enable bit of Mux _out_links/OutMux4_0 => wire_mult/mult/O_8 sp12_v_t_15 +(52 1) Enable bit of Mux _out_links/OutMux9_0 => wire_mult/mult/O_8 sp4_r_v_b_1 +(52 10) Enable bit of Mux _out_links/OutMux3_5 => wire_mult/mult/O_13 sp12_v_t_9 +(52 11) Enable bit of Mux _out_links/OutMux9_5 => wire_mult/mult/O_13 sp4_r_v_b_11 +(52 12) Enable bit of Mux _out_links/OutMux3_6 => wire_mult/mult/O_14 sp12_v_b_12 +(52 13) Enable bit of Mux _out_links/OutMux9_6 => wire_mult/mult/O_14 sp4_r_v_b_13 +(52 14) Enable bit of Mux _out_links/OutMux3_7 => wire_mult/mult/O_15 sp12_v_t_13 +(52 15) Enable bit of Mux _out_links/OutMux9_7 => wire_mult/mult/O_15 sp4_r_v_b_15 +(52 2) Enable bit of Mux _out_links/OutMux4_1 => wire_mult/mult/O_9 sp12_v_t_17 +(52 3) Enable bit of Mux _out_links/OutMux9_1 => wire_mult/mult/O_9 sp4_r_v_b_3 +(52 4) Enable bit of Mux _out_links/OutMux4_2 => wire_mult/mult/O_10 sp12_v_t_19 +(52 5) Enable bit of Mux _out_links/OutMux9_2 => wire_mult/mult/O_10 sp4_r_v_b_5 +(52 6) Enable bit of Mux _out_links/OutMux4_3 => wire_mult/mult/O_11 sp12_v_t_21 +(52 7) Enable bit of Mux _out_links/OutMux9_3 => wire_mult/mult/O_11 sp4_r_v_b_7 +(52 8) Enable bit of Mux _out_links/OutMux3_4 => wire_mult/mult/O_12 sp12_v_b_8 +(52 9) Enable bit of Mux _out_links/OutMux9_4 => wire_mult/mult/O_12 sp4_r_v_b_9 +(53 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_mult/mult/O_8 sp4_r_v_b_17 +(53 1) Enable bit of Mux _out_links/OutMuxb_0 => wire_mult/mult/O_8 sp4_r_v_b_33 +(53 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_mult/mult/O_13 sp4_r_v_b_27 +(53 11) Enable bit of Mux _out_links/OutMuxb_5 => wire_mult/mult/O_13 sp4_r_v_b_43 +(53 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_mult/mult/O_14 sp4_r_v_b_29 +(53 13) Enable bit of Mux _out_links/OutMuxb_6 => wire_mult/mult/O_14 sp4_r_v_b_45 +(53 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_mult/mult/O_15 sp4_r_v_b_31 +(53 15) Enable bit of Mux _out_links/OutMuxb_7 => wire_mult/mult/O_15 sp4_r_v_b_47 +(53 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_mult/mult/O_9 sp4_r_v_b_19 +(53 3) Enable bit of Mux _out_links/OutMuxb_1 => wire_mult/mult/O_9 sp4_r_v_b_35 +(53 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_mult/mult/O_10 sp4_r_v_b_21 +(53 5) Enable bit of Mux _out_links/OutMuxb_2 => wire_mult/mult/O_10 sp4_r_v_b_37 +(53 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_mult/mult/O_11 sp4_r_v_b_23 +(53 7) Enable bit of Mux _out_links/OutMuxb_3 => wire_mult/mult/O_11 sp4_r_v_b_39 +(53 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_mult/mult/O_12 sp4_r_v_b_25 +(53 9) Enable bit of Mux _out_links/OutMuxb_4 => wire_mult/mult/O_12 sp4_r_v_b_41 +(6 0) routing sp4_h_l_43 <X> sp4_v_b_0 +(6 0) routing sp4_h_r_7 <X> sp4_v_b_0 +(6 0) routing sp4_v_t_41 <X> sp4_v_b_0 +(6 0) routing sp4_v_t_44 <X> sp4_v_b_0 +(6 1) routing sp4_h_l_37 <X> sp4_h_r_0 +(6 1) routing sp4_h_l_41 <X> sp4_h_r_0 +(6 1) routing sp4_v_b_0 <X> sp4_h_r_0 +(6 1) routing sp4_v_b_6 <X> sp4_h_r_0 +(6 10) routing sp4_h_l_36 <X> sp4_v_t_43 +(6 10) routing sp4_h_r_0 <X> sp4_v_t_43 +(6 10) routing sp4_v_b_10 <X> sp4_v_t_43 +(6 10) routing sp4_v_b_3 <X> sp4_v_t_43 +(6 11) routing sp4_h_r_10 <X> sp4_h_l_43 +(6 11) routing sp4_h_r_6 <X> sp4_h_l_43 +(6 11) routing sp4_v_t_37 <X> sp4_h_l_43 +(6 11) routing sp4_v_t_43 <X> sp4_h_l_43 +(6 12) routing sp4_h_l_38 <X> sp4_v_b_9 +(6 12) routing sp4_h_r_4 <X> sp4_v_b_9 +(6 12) routing sp4_v_t_36 <X> sp4_v_b_9 +(6 12) routing sp4_v_t_43 <X> sp4_v_b_9 +(6 13) routing sp4_h_l_36 <X> sp4_h_r_9 +(6 13) routing sp4_v_b_3 <X> sp4_h_r_9 +(6 13) routing sp4_v_b_9 <X> sp4_h_r_9 +(6 14) routing sp4_h_l_41 <X> sp4_v_t_44 +(6 14) routing sp4_h_r_3 <X> sp4_v_t_44 +(6 14) routing sp4_v_b_1 <X> sp4_v_t_44 +(6 14) routing sp4_v_b_6 <X> sp4_v_t_44 +(6 15) routing sp4_h_r_9 <X> sp4_h_l_44 +(6 15) routing sp4_v_t_38 <X> sp4_h_l_44 +(6 15) routing sp4_v_t_44 <X> sp4_h_l_44 +(6 2) routing sp4_h_l_42 <X> sp4_v_t_37 +(6 2) routing sp4_h_r_6 <X> sp4_v_t_37 +(6 2) routing sp4_v_b_4 <X> sp4_v_t_37 +(6 2) routing sp4_v_b_9 <X> sp4_v_t_37 +(6 3) routing sp4_h_r_0 <X> sp4_h_l_37 +(6 3) routing sp4_h_r_4 <X> sp4_h_l_37 +(6 3) routing sp4_v_t_37 <X> sp4_h_l_37 +(6 3) routing sp4_v_t_43 <X> sp4_h_l_37 +(6 4) routing sp4_h_l_44 <X> sp4_v_b_3 +(6 4) routing sp4_h_r_10 <X> sp4_v_b_3 +(6 4) routing sp4_v_t_37 <X> sp4_v_b_3 +(6 4) routing sp4_v_t_42 <X> sp4_v_b_3 +(6 5) routing sp4_v_b_3 <X> sp4_h_r_3 +(6 5) routing sp4_v_b_9 <X> sp4_h_r_3 +(6 6) routing sp4_h_l_47 <X> sp4_v_t_38 +(6 6) routing sp4_h_r_9 <X> sp4_v_t_38 +(6 6) routing sp4_v_b_0 <X> sp4_v_t_38 +(6 6) routing sp4_v_b_7 <X> sp4_v_t_38 +(6 7) routing sp4_v_t_38 <X> sp4_h_l_38 +(6 7) routing sp4_v_t_44 <X> sp4_h_l_38 +(6 8) routing sp4_h_l_37 <X> sp4_v_b_6 +(6 8) routing sp4_h_r_1 <X> sp4_v_b_6 +(6 8) routing sp4_v_t_38 <X> sp4_v_b_6 +(6 8) routing sp4_v_t_47 <X> sp4_v_b_6 +(6 9) routing sp4_h_l_43 <X> sp4_h_r_6 +(6 9) routing sp4_h_l_47 <X> sp4_h_r_6 +(6 9) routing sp4_v_b_0 <X> sp4_h_r_6 +(6 9) routing sp4_v_b_6 <X> sp4_h_r_6 +(7 0) MAC16 functional bit: MULT1_bram_cbit_1 +(7 1) MAC16 functional bit: MULT1_bram_cbit_0 +(7 2) Hard IP config bit: MULT1_bram_cbit_3 +(7 2) MAC16 functional bit: MULT1_bram_cbit_3 +(7 3) MAC16 functional bit: MULT1_bram_cbit_2 +(7 5) Hard IP config bit: MULT1_bram_cbit_4 +(7 5) MAC16 functional bit: MULT1_bram_cbit_4 +(7 6) MAC16 functional bit: MULT1_bram_cbit_7 +(7 7) MAC16 functional bit: MULT1_bram_cbit_6 +(8 0) routing sp4_h_l_40 <X> sp4_h_r_1 +(8 0) routing sp4_v_b_1 <X> sp4_h_r_1 +(8 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(8 1) routing sp4_h_l_36 <X> sp4_v_b_1 +(8 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(8 1) routing sp4_h_r_1 <X> sp4_v_b_1 +(8 1) routing sp4_v_t_47 <X> sp4_v_b_1 +(8 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(8 10) routing sp4_v_t_42 <X> sp4_h_l_42 +(8 11) routing sp4_h_l_42 <X> sp4_v_t_42 +(8 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(8 11) routing sp4_h_r_7 <X> sp4_v_t_42 +(8 11) routing sp4_v_b_4 <X> sp4_v_t_42 +(8 12) routing sp4_v_b_10 <X> sp4_h_r_10 +(8 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(8 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(8 13) routing sp4_h_l_47 <X> sp4_v_b_10 +(8 13) routing sp4_h_r_10 <X> sp4_v_b_10 +(8 13) routing sp4_v_t_42 <X> sp4_v_b_10 +(8 14) routing sp4_h_r_10 <X> sp4_h_l_47 +(8 14) routing sp4_h_r_2 <X> sp4_h_l_47 +(8 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(8 15) routing sp4_h_l_47 <X> sp4_v_t_47 +(8 15) routing sp4_h_r_10 <X> sp4_v_t_47 +(8 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(8 15) routing sp4_v_b_7 <X> sp4_v_t_47 +(8 2) routing sp4_v_t_36 <X> sp4_h_l_36 +(8 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(8 3) routing sp4_h_l_36 <X> sp4_v_t_36 +(8 3) routing sp4_h_r_1 <X> sp4_v_t_36 +(8 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(8 3) routing sp4_v_b_10 <X> sp4_v_t_36 +(8 4) routing sp4_h_l_45 <X> sp4_h_r_4 +(8 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(8 4) routing sp4_v_b_4 <X> sp4_h_r_4 +(8 5) routing sp4_h_l_41 <X> sp4_v_b_4 +(8 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(8 5) routing sp4_h_r_4 <X> sp4_v_b_4 +(8 5) routing sp4_v_t_36 <X> sp4_v_b_4 +(8 6) routing sp4_h_r_4 <X> sp4_h_l_41 +(8 6) routing sp4_h_r_8 <X> sp4_h_l_41 +(8 6) routing sp4_v_t_41 <X> sp4_h_l_41 +(8 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(8 7) routing sp4_h_l_41 <X> sp4_v_t_41 +(8 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(8 7) routing sp4_h_r_4 <X> sp4_v_t_41 +(8 7) routing sp4_v_b_1 <X> sp4_v_t_41 +(8 8) routing sp4_h_l_42 <X> sp4_h_r_7 +(8 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(8 8) routing sp4_v_b_7 <X> sp4_h_r_7 +(8 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(8 9) routing sp4_h_l_42 <X> sp4_v_b_7 +(8 9) routing sp4_h_r_7 <X> sp4_v_b_7 +(8 9) routing sp4_v_t_41 <X> sp4_v_b_7 +(9 0) routing sp4_v_b_1 <X> sp4_h_r_1 +(9 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(9 0) routing sp4_v_t_36 <X> sp4_h_r_1 +(9 1) routing sp4_h_l_36 <X> sp4_v_b_1 +(9 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(9 1) routing sp4_v_t_36 <X> sp4_v_b_1 +(9 1) routing sp4_v_t_40 <X> sp4_v_b_1 +(9 10) routing sp4_h_r_4 <X> sp4_h_l_42 +(9 10) routing sp4_v_b_7 <X> sp4_h_l_42 +(9 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(9 10) routing sp4_v_t_42 <X> sp4_h_l_42 +(9 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(9 11) routing sp4_h_r_7 <X> sp4_v_t_42 +(9 11) routing sp4_v_b_11 <X> sp4_v_t_42 +(9 11) routing sp4_v_b_7 <X> sp4_v_t_42 +(9 12) routing sp4_v_b_10 <X> sp4_h_r_10 +(9 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(9 12) routing sp4_v_t_47 <X> sp4_h_r_10 +(9 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(9 13) routing sp4_h_l_47 <X> sp4_v_b_10 +(9 13) routing sp4_v_t_39 <X> sp4_v_b_10 +(9 13) routing sp4_v_t_47 <X> sp4_v_b_10 +(9 14) routing sp4_v_b_10 <X> sp4_h_l_47 +(9 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(9 15) routing sp4_h_r_10 <X> sp4_v_t_47 +(9 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(9 15) routing sp4_v_b_10 <X> sp4_v_t_47 +(9 15) routing sp4_v_b_2 <X> sp4_v_t_47 +(9 2) routing sp4_h_r_10 <X> sp4_h_l_36 +(9 2) routing sp4_v_b_1 <X> sp4_h_l_36 +(9 2) routing sp4_v_t_36 <X> sp4_h_l_36 +(9 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(9 3) routing sp4_h_r_1 <X> sp4_v_t_36 +(9 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(9 3) routing sp4_v_b_1 <X> sp4_v_t_36 +(9 3) routing sp4_v_b_5 <X> sp4_v_t_36 +(9 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(9 4) routing sp4_v_b_4 <X> sp4_h_r_4 +(9 4) routing sp4_v_t_41 <X> sp4_h_r_4 +(9 5) routing sp4_h_l_41 <X> sp4_v_b_4 +(9 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(9 5) routing sp4_v_t_41 <X> sp4_v_b_4 +(9 5) routing sp4_v_t_45 <X> sp4_v_b_4 +(9 6) routing sp4_v_b_4 <X> sp4_h_l_41 +(9 6) routing sp4_v_t_41 <X> sp4_h_l_41 +(9 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(9 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(9 7) routing sp4_h_r_4 <X> sp4_v_t_41 +(9 7) routing sp4_v_b_4 <X> sp4_v_t_41 +(9 7) routing sp4_v_b_8 <X> sp4_v_t_41 +(9 8) routing sp4_h_l_41 <X> sp4_h_r_7 +(9 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(9 8) routing sp4_v_b_7 <X> sp4_h_r_7 +(9 8) routing sp4_v_t_42 <X> sp4_h_r_7 +(9 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(9 9) routing sp4_h_l_42 <X> sp4_v_b_7 +(9 9) routing sp4_v_t_42 <X> sp4_v_b_7 +(9 9) routing sp4_v_t_46 <X> sp4_v_b_7 diff --git a/icefuzz/cached_dsp2_5k.txt b/icefuzz/cached_dsp2_5k.txt index e69de29..1904fae 100644 --- a/icefuzz/cached_dsp2_5k.txt +++ b/icefuzz/cached_dsp2_5k.txt @@ -0,0 +1,3057 @@ +(0 0) Negative Clock bit +(0 10) routing glb_netwk_2 <X> glb2local_2 +(0 10) routing glb_netwk_3 <X> glb2local_2 +(0 10) routing glb_netwk_6 <X> glb2local_2 +(0 10) routing glb_netwk_7 <X> glb2local_2 +(0 11) routing glb_netwk_1 <X> glb2local_2 +(0 11) routing glb_netwk_3 <X> glb2local_2 +(0 11) routing glb_netwk_5 <X> glb2local_2 +(0 11) routing glb_netwk_7 <X> glb2local_2 +(0 12) routing glb_netwk_2 <X> glb2local_3 +(0 12) routing glb_netwk_3 <X> glb2local_3 +(0 12) routing glb_netwk_6 <X> glb2local_3 +(0 12) routing glb_netwk_7 <X> glb2local_3 +(0 13) routing glb_netwk_1 <X> glb2local_3 +(0 13) routing glb_netwk_3 <X> glb2local_3 +(0 13) routing glb_netwk_5 <X> glb2local_3 +(0 13) routing glb_netwk_7 <X> glb2local_3 +(0 14) routing glb_netwk_4 <X> wire_mult/lc_7/s_r +(0 14) routing glb_netwk_6 <X> wire_mult/lc_7/s_r +(0 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/s_r +(0 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/s_r +(0 15) routing glb_netwk_2 <X> wire_mult/lc_7/s_r +(0 15) routing glb_netwk_6 <X> wire_mult/lc_7/s_r +(0 15) routing lc_trk_g1_5 <X> wire_mult/lc_7/s_r +(0 15) routing lc_trk_g3_5 <X> wire_mult/lc_7/s_r +(0 2) routing glb_netwk_2 <X> wire_mult/lc_7/clk +(0 2) routing glb_netwk_3 <X> wire_mult/lc_7/clk +(0 2) routing glb_netwk_6 <X> wire_mult/lc_7/clk +(0 2) routing glb_netwk_7 <X> wire_mult/lc_7/clk +(0 2) routing lc_trk_g2_0 <X> wire_mult/lc_7/clk +(0 2) routing lc_trk_g3_1 <X> wire_mult/lc_7/clk +(0 3) routing glb_netwk_1 <X> wire_mult/lc_7/clk +(0 3) routing glb_netwk_3 <X> wire_mult/lc_7/clk +(0 3) routing glb_netwk_5 <X> wire_mult/lc_7/clk +(0 3) routing glb_netwk_7 <X> wire_mult/lc_7/clk +(0 3) routing lc_trk_g1_1 <X> wire_mult/lc_7/clk +(0 3) routing lc_trk_g3_1 <X> wire_mult/lc_7/clk +(0 4) routing lc_trk_g2_2 <X> wire_mult/lc_7/cen +(0 4) routing lc_trk_g3_3 <X> wire_mult/lc_7/cen +(0 5) routing lc_trk_g1_3 <X> wire_mult/lc_7/cen +(0 5) routing lc_trk_g3_3 <X> wire_mult/lc_7/cen +(0 6) routing glb_netwk_2 <X> glb2local_0 +(0 6) routing glb_netwk_3 <X> glb2local_0 +(0 6) routing glb_netwk_6 <X> glb2local_0 +(0 6) routing glb_netwk_7 <X> glb2local_0 +(0 7) routing glb_netwk_1 <X> glb2local_0 +(0 7) routing glb_netwk_3 <X> glb2local_0 +(0 7) routing glb_netwk_5 <X> glb2local_0 +(0 7) routing glb_netwk_7 <X> glb2local_0 +(0 8) routing glb_netwk_2 <X> glb2local_1 +(0 8) routing glb_netwk_3 <X> glb2local_1 +(0 8) routing glb_netwk_6 <X> glb2local_1 +(0 8) routing glb_netwk_7 <X> glb2local_1 +(0 9) routing glb_netwk_1 <X> glb2local_1 +(0 9) routing glb_netwk_3 <X> glb2local_1 +(0 9) routing glb_netwk_5 <X> glb2local_1 +(0 9) routing glb_netwk_7 <X> glb2local_1 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 +(1 11) routing glb_netwk_4 <X> glb2local_2 +(1 11) routing glb_netwk_5 <X> glb2local_2 +(1 11) routing glb_netwk_6 <X> glb2local_2 +(1 11) routing glb_netwk_7 <X> glb2local_2 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 +(1 13) routing glb_netwk_4 <X> glb2local_3 +(1 13) routing glb_netwk_5 <X> glb2local_3 +(1 13) routing glb_netwk_6 <X> glb2local_3 +(1 13) routing glb_netwk_7 <X> glb2local_3 +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g0_4 <X> wire_mult/lc_7/s_r +(1 15) routing lc_trk_g1_5 <X> wire_mult/lc_7/s_r +(1 15) routing lc_trk_g2_4 <X> wire_mult/lc_7/s_r +(1 15) routing lc_trk_g3_5 <X> wire_mult/lc_7/s_r +(1 2) routing glb_netwk_4 <X> wire_mult/lc_7/clk +(1 2) routing glb_netwk_5 <X> wire_mult/lc_7/clk +(1 2) routing glb_netwk_6 <X> wire_mult/lc_7/clk +(1 2) routing glb_netwk_7 <X> wire_mult/lc_7/clk +(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_mult/lc_7/cen +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_mult/lc_7/cen +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_mult/lc_7/cen +(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_mult/lc_7/cen +(1 5) routing lc_trk_g0_2 <X> wire_mult/lc_7/cen +(1 5) routing lc_trk_g1_3 <X> wire_mult/lc_7/cen +(1 5) routing lc_trk_g2_2 <X> wire_mult/lc_7/cen +(1 5) routing lc_trk_g3_3 <X> wire_mult/lc_7/cen +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 +(1 7) routing glb_netwk_4 <X> glb2local_0 +(1 7) routing glb_netwk_5 <X> glb2local_0 +(1 7) routing glb_netwk_6 <X> glb2local_0 +(1 7) routing glb_netwk_7 <X> glb2local_0 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 +(1 9) routing glb_netwk_4 <X> glb2local_1 +(1 9) routing glb_netwk_5 <X> glb2local_1 +(1 9) routing glb_netwk_6 <X> glb2local_1 +(1 9) routing glb_netwk_7 <X> glb2local_1 +(10 0) routing sp4_h_l_40 <X> sp4_h_r_1 +(10 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(10 0) routing sp4_v_t_45 <X> sp4_h_r_1 +(10 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(10 1) routing sp4_h_r_8 <X> sp4_v_b_1 +(10 1) routing sp4_v_t_40 <X> sp4_v_b_1 +(10 1) routing sp4_v_t_47 <X> sp4_v_b_1 +(10 10) routing sp4_h_r_4 <X> sp4_h_l_42 +(10 10) routing sp4_v_b_2 <X> sp4_h_l_42 +(10 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(10 11) routing sp4_h_l_39 <X> sp4_v_t_42 +(10 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(10 11) routing sp4_v_b_11 <X> sp4_v_t_42 +(10 11) routing sp4_v_b_4 <X> sp4_v_t_42 +(10 12) routing sp4_h_l_39 <X> sp4_h_r_10 +(10 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(10 12) routing sp4_v_t_40 <X> sp4_h_r_10 +(10 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(10 13) routing sp4_h_r_5 <X> sp4_v_b_10 +(10 13) routing sp4_v_t_39 <X> sp4_v_b_10 +(10 13) routing sp4_v_t_42 <X> sp4_v_b_10 +(10 14) routing sp4_h_r_2 <X> sp4_h_l_47 +(10 14) routing sp4_v_b_5 <X> sp4_h_l_47 +(10 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(10 15) routing sp4_h_l_40 <X> sp4_v_t_47 +(10 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(10 15) routing sp4_v_b_2 <X> sp4_v_t_47 +(10 15) routing sp4_v_b_7 <X> sp4_v_t_47 +(10 2) routing sp4_h_r_10 <X> sp4_h_l_36 +(10 2) routing sp4_v_b_8 <X> sp4_h_l_36 +(10 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(10 3) routing sp4_h_l_45 <X> sp4_v_t_36 +(10 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(10 3) routing sp4_v_b_10 <X> sp4_v_t_36 +(10 3) routing sp4_v_b_5 <X> sp4_v_t_36 +(10 4) routing sp4_h_l_45 <X> sp4_h_r_4 +(10 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(10 4) routing sp4_v_t_46 <X> sp4_h_r_4 +(10 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(10 5) routing sp4_h_r_11 <X> sp4_v_b_4 +(10 5) routing sp4_v_t_36 <X> sp4_v_b_4 +(10 5) routing sp4_v_t_45 <X> sp4_v_b_4 +(10 6) routing sp4_h_r_8 <X> sp4_h_l_41 +(10 6) routing sp4_v_b_11 <X> sp4_h_l_41 +(10 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(10 7) routing sp4_h_l_46 <X> sp4_v_t_41 +(10 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(10 7) routing sp4_v_b_1 <X> sp4_v_t_41 +(10 7) routing sp4_v_b_8 <X> sp4_v_t_41 +(10 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(10 8) routing sp4_v_t_39 <X> sp4_h_r_7 +(10 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(10 9) routing sp4_h_r_2 <X> sp4_v_b_7 +(10 9) routing sp4_v_t_41 <X> sp4_v_b_7 +(10 9) routing sp4_v_t_46 <X> sp4_v_b_7 +(11 0) routing sp4_h_l_45 <X> sp4_v_b_2 +(11 0) routing sp4_h_r_9 <X> sp4_v_b_2 +(11 0) routing sp4_v_t_43 <X> sp4_v_b_2 +(11 0) routing sp4_v_t_46 <X> sp4_v_b_2 +(11 1) routing sp4_h_l_39 <X> sp4_h_r_2 +(11 1) routing sp4_h_l_43 <X> sp4_h_r_2 +(11 1) routing sp4_v_b_2 <X> sp4_h_r_2 +(11 1) routing sp4_v_b_8 <X> sp4_h_r_2 +(11 10) routing sp4_h_l_38 <X> sp4_v_t_45 +(11 10) routing sp4_h_r_2 <X> sp4_v_t_45 +(11 10) routing sp4_v_b_0 <X> sp4_v_t_45 +(11 10) routing sp4_v_b_5 <X> sp4_v_t_45 +(11 11) routing sp4_h_r_0 <X> sp4_h_l_45 +(11 11) routing sp4_h_r_8 <X> sp4_h_l_45 +(11 11) routing sp4_v_t_39 <X> sp4_h_l_45 +(11 11) routing sp4_v_t_45 <X> sp4_h_l_45 +(11 12) routing sp4_h_l_40 <X> sp4_v_b_11 +(11 12) routing sp4_h_r_6 <X> sp4_v_b_11 +(11 12) routing sp4_v_t_38 <X> sp4_v_b_11 +(11 12) routing sp4_v_t_45 <X> sp4_v_b_11 +(11 13) routing sp4_h_l_46 <X> sp4_h_r_11 +(11 13) routing sp4_v_b_11 <X> sp4_h_r_11 +(11 13) routing sp4_v_b_5 <X> sp4_h_r_11 +(11 14) routing sp4_h_l_43 <X> sp4_v_t_46 +(11 14) routing sp4_h_r_5 <X> sp4_v_t_46 +(11 14) routing sp4_v_b_3 <X> sp4_v_t_46 +(11 14) routing sp4_v_b_8 <X> sp4_v_t_46 +(11 15) routing sp4_v_t_40 <X> sp4_h_l_46 +(11 15) routing sp4_v_t_46 <X> sp4_h_l_46 +(11 2) routing sp4_h_l_44 <X> sp4_v_t_39 +(11 2) routing sp4_h_r_8 <X> sp4_v_t_39 +(11 2) routing sp4_v_b_11 <X> sp4_v_t_39 +(11 2) routing sp4_v_b_6 <X> sp4_v_t_39 +(11 3) routing sp4_h_r_2 <X> sp4_h_l_39 +(11 3) routing sp4_h_r_6 <X> sp4_h_l_39 +(11 3) routing sp4_v_t_39 <X> sp4_h_l_39 +(11 3) routing sp4_v_t_45 <X> sp4_h_l_39 +(11 4) routing sp4_h_l_46 <X> sp4_v_b_5 +(11 4) routing sp4_h_r_0 <X> sp4_v_b_5 +(11 4) routing sp4_v_t_39 <X> sp4_v_b_5 +(11 4) routing sp4_v_t_44 <X> sp4_v_b_5 +(11 5) routing sp4_h_l_40 <X> sp4_h_r_5 +(11 5) routing sp4_h_l_44 <X> sp4_h_r_5 +(11 5) routing sp4_v_b_11 <X> sp4_h_r_5 +(11 5) routing sp4_v_b_5 <X> sp4_h_r_5 +(11 6) routing sp4_h_l_37 <X> sp4_v_t_40 +(11 6) routing sp4_h_r_11 <X> sp4_v_t_40 +(11 6) routing sp4_v_b_2 <X> sp4_v_t_40 +(11 6) routing sp4_v_b_9 <X> sp4_v_t_40 +(11 7) routing sp4_h_r_9 <X> sp4_h_l_40 +(11 7) routing sp4_v_t_40 <X> sp4_h_l_40 +(11 7) routing sp4_v_t_46 <X> sp4_h_l_40 +(11 8) routing sp4_h_l_39 <X> sp4_v_b_8 +(11 8) routing sp4_h_r_3 <X> sp4_v_b_8 +(11 8) routing sp4_v_t_37 <X> sp4_v_b_8 +(11 8) routing sp4_v_t_40 <X> sp4_v_b_8 +(11 9) routing sp4_h_l_37 <X> sp4_h_r_8 +(11 9) routing sp4_v_b_2 <X> sp4_h_r_8 +(11 9) routing sp4_v_b_8 <X> sp4_h_r_8 +(12 0) routing sp4_h_l_46 <X> sp4_h_r_2 +(12 0) routing sp4_v_b_2 <X> sp4_h_r_2 +(12 0) routing sp4_v_b_8 <X> sp4_h_r_2 +(12 0) routing sp4_v_t_39 <X> sp4_h_r_2 +(12 1) routing sp4_h_l_39 <X> sp4_v_b_2 +(12 1) routing sp4_h_l_45 <X> sp4_v_b_2 +(12 1) routing sp4_h_r_2 <X> sp4_v_b_2 +(12 1) routing sp4_v_t_46 <X> sp4_v_b_2 +(12 10) routing sp4_v_b_8 <X> sp4_h_l_45 +(12 10) routing sp4_v_t_39 <X> sp4_h_l_45 +(12 10) routing sp4_v_t_45 <X> sp4_h_l_45 +(12 11) routing sp4_h_l_45 <X> sp4_v_t_45 +(12 11) routing sp4_h_r_2 <X> sp4_v_t_45 +(12 11) routing sp4_h_r_8 <X> sp4_v_t_45 +(12 11) routing sp4_v_b_5 <X> sp4_v_t_45 +(12 12) routing sp4_h_l_45 <X> sp4_h_r_11 +(12 12) routing sp4_v_b_11 <X> sp4_h_r_11 +(12 12) routing sp4_v_b_5 <X> sp4_h_r_11 +(12 12) routing sp4_v_t_46 <X> sp4_h_r_11 +(12 13) routing sp4_h_l_40 <X> sp4_v_b_11 +(12 13) routing sp4_h_l_46 <X> sp4_v_b_11 +(12 13) routing sp4_h_r_11 <X> sp4_v_b_11 +(12 13) routing sp4_v_t_45 <X> sp4_v_b_11 +(12 14) routing sp4_h_r_8 <X> sp4_h_l_46 +(12 14) routing sp4_v_b_11 <X> sp4_h_l_46 +(12 14) routing sp4_v_t_40 <X> sp4_h_l_46 +(12 14) routing sp4_v_t_46 <X> sp4_h_l_46 +(12 15) routing sp4_h_l_46 <X> sp4_v_t_46 +(12 15) routing sp4_h_r_11 <X> sp4_v_t_46 +(12 15) routing sp4_h_r_5 <X> sp4_v_t_46 +(12 15) routing sp4_v_b_8 <X> sp4_v_t_46 +(12 2) routing sp4_v_b_2 <X> sp4_h_l_39 +(12 2) routing sp4_v_t_39 <X> sp4_h_l_39 +(12 2) routing sp4_v_t_45 <X> sp4_h_l_39 +(12 3) routing sp4_h_l_39 <X> sp4_v_t_39 +(12 3) routing sp4_h_r_2 <X> sp4_v_t_39 +(12 3) routing sp4_h_r_8 <X> sp4_v_t_39 +(12 3) routing sp4_v_b_11 <X> sp4_v_t_39 +(12 4) routing sp4_v_b_11 <X> sp4_h_r_5 +(12 4) routing sp4_v_b_5 <X> sp4_h_r_5 +(12 4) routing sp4_v_t_40 <X> sp4_h_r_5 +(12 5) routing sp4_h_l_40 <X> sp4_v_b_5 +(12 5) routing sp4_h_l_46 <X> sp4_v_b_5 +(12 5) routing sp4_h_r_5 <X> sp4_v_b_5 +(12 5) routing sp4_v_t_39 <X> sp4_v_b_5 +(12 6) routing sp4_h_r_2 <X> sp4_h_l_40 +(12 6) routing sp4_v_b_5 <X> sp4_h_l_40 +(12 6) routing sp4_v_t_40 <X> sp4_h_l_40 +(12 6) routing sp4_v_t_46 <X> sp4_h_l_40 +(12 7) routing sp4_h_l_40 <X> sp4_v_t_40 +(12 7) routing sp4_h_r_11 <X> sp4_v_t_40 +(12 7) routing sp4_h_r_5 <X> sp4_v_t_40 +(12 7) routing sp4_v_b_2 <X> sp4_v_t_40 +(12 8) routing sp4_h_l_40 <X> sp4_h_r_8 +(12 8) routing sp4_v_b_2 <X> sp4_h_r_8 +(12 8) routing sp4_v_b_8 <X> sp4_h_r_8 +(12 8) routing sp4_v_t_45 <X> sp4_h_r_8 +(12 9) routing sp4_h_l_39 <X> sp4_v_b_8 +(12 9) routing sp4_h_l_45 <X> sp4_v_b_8 +(12 9) routing sp4_h_r_8 <X> sp4_v_b_8 +(12 9) routing sp4_v_t_40 <X> sp4_v_b_8 +(13 0) routing sp4_h_l_39 <X> sp4_v_b_2 +(13 0) routing sp4_h_l_45 <X> sp4_v_b_2 +(13 0) routing sp4_v_t_39 <X> sp4_v_b_2 +(13 0) routing sp4_v_t_43 <X> sp4_v_b_2 +(13 1) routing sp4_h_l_43 <X> sp4_h_r_2 +(13 1) routing sp4_h_l_46 <X> sp4_h_r_2 +(13 1) routing sp4_v_b_8 <X> sp4_h_r_2 +(13 1) routing sp4_v_t_44 <X> sp4_h_r_2 +(13 10) routing sp4_h_r_2 <X> sp4_v_t_45 +(13 10) routing sp4_h_r_8 <X> sp4_v_t_45 +(13 10) routing sp4_v_b_0 <X> sp4_v_t_45 +(13 10) routing sp4_v_b_8 <X> sp4_v_t_45 +(13 11) routing sp4_h_r_0 <X> sp4_h_l_45 +(13 11) routing sp4_v_b_3 <X> sp4_h_l_45 +(13 11) routing sp4_v_t_39 <X> sp4_h_l_45 +(13 12) routing sp4_h_l_40 <X> sp4_v_b_11 +(13 12) routing sp4_h_l_46 <X> sp4_v_b_11 +(13 12) routing sp4_v_t_38 <X> sp4_v_b_11 +(13 12) routing sp4_v_t_46 <X> sp4_v_b_11 +(13 13) routing sp4_h_l_45 <X> sp4_h_r_11 +(13 13) routing sp4_v_b_5 <X> sp4_h_r_11 +(13 13) routing sp4_v_t_43 <X> sp4_h_r_11 +(13 14) routing sp4_h_r_11 <X> sp4_v_t_46 +(13 14) routing sp4_h_r_5 <X> sp4_v_t_46 +(13 14) routing sp4_v_b_11 <X> sp4_v_t_46 +(13 14) routing sp4_v_b_3 <X> sp4_v_t_46 +(13 15) routing sp4_h_r_8 <X> sp4_h_l_46 +(13 15) routing sp4_v_b_6 <X> sp4_h_l_46 +(13 15) routing sp4_v_t_40 <X> sp4_h_l_46 +(13 2) routing sp4_h_r_2 <X> sp4_v_t_39 +(13 2) routing sp4_h_r_8 <X> sp4_v_t_39 +(13 2) routing sp4_v_b_2 <X> sp4_v_t_39 +(13 2) routing sp4_v_b_6 <X> sp4_v_t_39 +(13 3) routing sp4_h_r_6 <X> sp4_h_l_39 +(13 3) routing sp4_v_b_9 <X> sp4_h_l_39 +(13 3) routing sp4_v_t_45 <X> sp4_h_l_39 +(13 4) routing sp4_h_l_40 <X> sp4_v_b_5 +(13 4) routing sp4_h_l_46 <X> sp4_v_b_5 +(13 4) routing sp4_v_t_40 <X> sp4_v_b_5 +(13 4) routing sp4_v_t_44 <X> sp4_v_b_5 +(13 5) routing sp4_h_l_44 <X> sp4_h_r_5 +(13 5) routing sp4_v_b_11 <X> sp4_h_r_5 +(13 5) routing sp4_v_t_37 <X> sp4_h_r_5 +(13 6) routing sp4_h_r_11 <X> sp4_v_t_40 +(13 6) routing sp4_h_r_5 <X> sp4_v_t_40 +(13 6) routing sp4_v_b_5 <X> sp4_v_t_40 +(13 6) routing sp4_v_b_9 <X> sp4_v_t_40 +(13 7) routing sp4_h_r_2 <X> sp4_h_l_40 +(13 7) routing sp4_h_r_9 <X> sp4_h_l_40 +(13 7) routing sp4_v_b_0 <X> sp4_h_l_40 +(13 7) routing sp4_v_t_46 <X> sp4_h_l_40 +(13 8) routing sp4_h_l_39 <X> sp4_v_b_8 +(13 8) routing sp4_h_l_45 <X> sp4_v_b_8 +(13 8) routing sp4_v_t_37 <X> sp4_v_b_8 +(13 8) routing sp4_v_t_45 <X> sp4_v_b_8 +(13 9) routing sp4_h_l_37 <X> sp4_h_r_8 +(13 9) routing sp4_h_l_40 <X> sp4_h_r_8 +(13 9) routing sp4_v_b_2 <X> sp4_h_r_8 +(13 9) routing sp4_v_t_38 <X> sp4_h_r_8 +(14 0) routing bnr_op_0 <X> lc_trk_g0_0 +(14 0) routing lft_op_0 <X> lc_trk_g0_0 +(14 0) routing sp12_h_r_0 <X> lc_trk_g0_0 +(14 0) routing sp4_h_r_16 <X> lc_trk_g0_0 +(14 0) routing sp4_h_r_8 <X> lc_trk_g0_0 +(14 0) routing sp4_v_b_0 <X> lc_trk_g0_0 +(14 0) routing sp4_v_b_8 <X> lc_trk_g0_0 +(14 1) routing bnr_op_0 <X> lc_trk_g0_0 +(14 1) routing sp12_h_r_0 <X> lc_trk_g0_0 +(14 1) routing sp12_h_r_16 <X> lc_trk_g0_0 +(14 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(14 1) routing sp4_h_r_16 <X> lc_trk_g0_0 +(14 1) routing sp4_r_v_b_35 <X> lc_trk_g0_0 +(14 1) routing sp4_v_b_8 <X> lc_trk_g0_0 +(14 10) routing bnl_op_4 <X> lc_trk_g2_4 +(14 10) routing rgt_op_4 <X> lc_trk_g2_4 +(14 10) routing sp12_v_t_3 <X> lc_trk_g2_4 +(14 10) routing sp4_h_l_33 <X> lc_trk_g2_4 +(14 10) routing sp4_h_r_36 <X> lc_trk_g2_4 +(14 10) routing sp4_v_b_36 <X> lc_trk_g2_4 +(14 10) routing sp4_v_t_17 <X> lc_trk_g2_4 +(14 11) routing bnl_op_4 <X> lc_trk_g2_4 +(14 11) routing sp12_v_t_19 <X> lc_trk_g2_4 +(14 11) routing sp12_v_t_3 <X> lc_trk_g2_4 +(14 11) routing sp4_h_l_17 <X> lc_trk_g2_4 +(14 11) routing sp4_h_l_33 <X> lc_trk_g2_4 +(14 11) routing sp4_r_v_b_36 <X> lc_trk_g2_4 +(14 11) routing sp4_v_b_36 <X> lc_trk_g2_4 +(14 11) routing tnl_op_4 <X> lc_trk_g2_4 +(14 12) routing bnl_op_0 <X> lc_trk_g3_0 +(14 12) routing rgt_op_0 <X> lc_trk_g3_0 +(14 12) routing sp12_v_b_0 <X> lc_trk_g3_0 +(14 12) routing sp4_h_r_32 <X> lc_trk_g3_0 +(14 12) routing sp4_h_r_40 <X> lc_trk_g3_0 +(14 12) routing sp4_v_b_32 <X> lc_trk_g3_0 +(14 12) routing sp4_v_t_13 <X> lc_trk_g3_0 +(14 13) routing bnl_op_0 <X> lc_trk_g3_0 +(14 13) routing sp12_v_b_0 <X> lc_trk_g3_0 +(14 13) routing sp12_v_b_16 <X> lc_trk_g3_0 +(14 13) routing sp4_h_l_13 <X> lc_trk_g3_0 +(14 13) routing sp4_h_r_40 <X> lc_trk_g3_0 +(14 13) routing sp4_r_v_b_40 <X> lc_trk_g3_0 +(14 13) routing sp4_v_b_32 <X> lc_trk_g3_0 +(14 13) routing tnl_op_0 <X> lc_trk_g3_0 +(14 14) routing bnl_op_4 <X> lc_trk_g3_4 +(14 14) routing sp12_v_t_3 <X> lc_trk_g3_4 +(14 14) routing sp4_h_l_33 <X> lc_trk_g3_4 +(14 14) routing sp4_h_r_36 <X> lc_trk_g3_4 +(14 14) routing sp4_v_b_36 <X> lc_trk_g3_4 +(14 14) routing sp4_v_t_17 <X> lc_trk_g3_4 +(14 15) routing bnl_op_4 <X> lc_trk_g3_4 +(14 15) routing sp12_v_t_19 <X> lc_trk_g3_4 +(14 15) routing sp12_v_t_3 <X> lc_trk_g3_4 +(14 15) routing sp4_h_l_17 <X> lc_trk_g3_4 +(14 15) routing sp4_h_l_33 <X> lc_trk_g3_4 +(14 15) routing sp4_r_v_b_44 <X> lc_trk_g3_4 +(14 15) routing sp4_v_b_36 <X> lc_trk_g3_4 +(14 15) routing tnl_op_4 <X> lc_trk_g3_4 +(14 2) routing lft_op_4 <X> lc_trk_g0_4 +(14 2) routing sp12_h_r_4 <X> lc_trk_g0_4 +(14 2) routing sp4_h_l_9 <X> lc_trk_g0_4 +(14 2) routing sp4_h_r_12 <X> lc_trk_g0_4 +(14 2) routing sp4_v_b_4 <X> lc_trk_g0_4 +(14 2) routing sp4_v_t_1 <X> lc_trk_g0_4 +(14 3) routing sp12_h_r_20 <X> lc_trk_g0_4 +(14 3) routing sp12_h_r_4 <X> lc_trk_g0_4 +(14 3) routing sp4_h_l_9 <X> lc_trk_g0_4 +(14 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(14 3) routing sp4_r_v_b_28 <X> lc_trk_g0_4 +(14 3) routing sp4_v_t_1 <X> lc_trk_g0_4 +(14 4) routing lft_op_0 <X> lc_trk_g1_0 +(14 4) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 4) routing sp4_h_r_16 <X> lc_trk_g1_0 +(14 4) routing sp4_h_r_8 <X> lc_trk_g1_0 +(14 4) routing sp4_v_b_0 <X> lc_trk_g1_0 +(14 4) routing sp4_v_b_8 <X> lc_trk_g1_0 +(14 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp12_h_r_16 <X> lc_trk_g1_0 +(14 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp4_h_r_16 <X> lc_trk_g1_0 +(14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0 +(14 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(14 6) routing bnr_op_4 <X> lc_trk_g1_4 +(14 6) routing lft_op_4 <X> lc_trk_g1_4 +(14 6) routing sp12_h_r_4 <X> lc_trk_g1_4 +(14 6) routing sp4_h_l_9 <X> lc_trk_g1_4 +(14 6) routing sp4_h_r_12 <X> lc_trk_g1_4 +(14 6) routing sp4_v_b_4 <X> lc_trk_g1_4 +(14 6) routing sp4_v_t_1 <X> lc_trk_g1_4 +(14 7) routing bnr_op_4 <X> lc_trk_g1_4 +(14 7) routing sp12_h_r_20 <X> lc_trk_g1_4 +(14 7) routing sp12_h_r_4 <X> lc_trk_g1_4 +(14 7) routing sp4_h_l_9 <X> lc_trk_g1_4 +(14 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4 +(14 7) routing sp4_v_t_1 <X> lc_trk_g1_4 +(14 8) routing bnl_op_0 <X> lc_trk_g2_0 +(14 8) routing rgt_op_0 <X> lc_trk_g2_0 +(14 8) routing sp12_v_b_0 <X> lc_trk_g2_0 +(14 8) routing sp4_h_r_32 <X> lc_trk_g2_0 +(14 8) routing sp4_h_r_40 <X> lc_trk_g2_0 +(14 8) routing sp4_v_b_32 <X> lc_trk_g2_0 +(14 8) routing sp4_v_t_13 <X> lc_trk_g2_0 +(14 9) routing bnl_op_0 <X> lc_trk_g2_0 +(14 9) routing sp12_v_b_0 <X> lc_trk_g2_0 +(14 9) routing sp12_v_b_16 <X> lc_trk_g2_0 +(14 9) routing sp4_h_l_13 <X> lc_trk_g2_0 +(14 9) routing sp4_h_r_40 <X> lc_trk_g2_0 +(14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0 +(14 9) routing sp4_v_b_32 <X> lc_trk_g2_0 +(14 9) routing tnl_op_0 <X> lc_trk_g2_0 +(15 0) routing lft_op_1 <X> lc_trk_g0_1 +(15 0) routing sp12_h_r_1 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_1 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(15 0) routing sp4_v_t_4 <X> lc_trk_g0_1 +(15 1) routing lft_op_0 <X> lc_trk_g0_0 +(15 1) routing sp12_h_r_0 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_16 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_8 <X> lc_trk_g0_0 +(15 1) routing sp4_v_b_16 <X> lc_trk_g0_0 +(15 10) routing sp12_v_b_5 <X> lc_trk_g2_5 +(15 10) routing sp4_h_l_24 <X> lc_trk_g2_5 +(15 10) routing sp4_h_r_29 <X> lc_trk_g2_5 +(15 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(15 10) routing sp4_v_b_45 <X> lc_trk_g2_5 +(15 10) routing tnl_op_5 <X> lc_trk_g2_5 +(15 10) routing tnr_op_5 <X> lc_trk_g2_5 +(15 11) routing rgt_op_4 <X> lc_trk_g2_4 +(15 11) routing sp12_v_t_3 <X> lc_trk_g2_4 +(15 11) routing sp4_h_l_17 <X> lc_trk_g2_4 +(15 11) routing sp4_h_l_33 <X> lc_trk_g2_4 +(15 11) routing sp4_h_r_36 <X> lc_trk_g2_4 +(15 11) routing sp4_v_t_33 <X> lc_trk_g2_4 +(15 11) routing tnl_op_4 <X> lc_trk_g2_4 +(15 11) routing tnr_op_4 <X> lc_trk_g2_4 +(15 12) routing rgt_op_1 <X> lc_trk_g3_1 +(15 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(15 12) routing sp4_h_l_12 <X> lc_trk_g3_1 +(15 12) routing sp4_h_l_20 <X> lc_trk_g3_1 +(15 12) routing sp4_h_l_28 <X> lc_trk_g3_1 +(15 12) routing sp4_v_b_41 <X> lc_trk_g3_1 +(15 12) routing tnl_op_1 <X> lc_trk_g3_1 +(15 13) routing rgt_op_0 <X> lc_trk_g3_0 +(15 13) routing sp12_v_b_0 <X> lc_trk_g3_0 +(15 13) routing sp4_h_l_13 <X> lc_trk_g3_0 +(15 13) routing sp4_h_r_32 <X> lc_trk_g3_0 +(15 13) routing sp4_h_r_40 <X> lc_trk_g3_0 +(15 13) routing sp4_v_t_29 <X> lc_trk_g3_0 +(15 13) routing tnl_op_0 <X> lc_trk_g3_0 +(15 13) routing tnr_op_0 <X> lc_trk_g3_0 +(15 14) routing rgt_op_5 <X> lc_trk_g3_5 +(15 14) routing sp12_v_b_5 <X> lc_trk_g3_5 +(15 14) routing sp4_h_l_24 <X> lc_trk_g3_5 +(15 14) routing sp4_h_r_29 <X> lc_trk_g3_5 +(15 14) routing sp4_h_r_45 <X> lc_trk_g3_5 +(15 14) routing sp4_v_b_45 <X> lc_trk_g3_5 +(15 14) routing tnr_op_5 <X> lc_trk_g3_5 +(15 15) routing sp12_v_t_3 <X> lc_trk_g3_4 +(15 15) routing sp4_h_l_17 <X> lc_trk_g3_4 +(15 15) routing sp4_h_l_33 <X> lc_trk_g3_4 +(15 15) routing sp4_h_r_36 <X> lc_trk_g3_4 +(15 15) routing sp4_v_t_33 <X> lc_trk_g3_4 +(15 15) routing tnl_op_4 <X> lc_trk_g3_4 +(15 15) routing tnr_op_4 <X> lc_trk_g3_4 +(15 2) routing lft_op_5 <X> lc_trk_g0_5 +(15 2) routing sp12_h_r_5 <X> lc_trk_g0_5 +(15 2) routing sp4_h_l_0 <X> lc_trk_g0_5 +(15 2) routing sp4_h_r_21 <X> lc_trk_g0_5 +(15 2) routing sp4_h_r_5 <X> lc_trk_g0_5 +(15 2) routing sp4_v_t_8 <X> lc_trk_g0_5 +(15 3) routing lft_op_4 <X> lc_trk_g0_4 +(15 3) routing sp12_h_r_4 <X> lc_trk_g0_4 +(15 3) routing sp4_h_l_9 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_12 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(15 3) routing sp4_v_b_20 <X> lc_trk_g0_4 +(15 4) routing sp12_h_r_1 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_1 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(15 4) routing sp4_v_t_4 <X> lc_trk_g1_1 +(15 5) routing lft_op_0 <X> lc_trk_g1_0 +(15 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_16 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_8 <X> lc_trk_g1_0 +(15 5) routing sp4_v_b_16 <X> lc_trk_g1_0 +(15 6) routing lft_op_5 <X> lc_trk_g1_5 +(15 6) routing sp12_h_r_5 <X> lc_trk_g1_5 +(15 6) routing sp4_h_l_0 <X> lc_trk_g1_5 +(15 6) routing sp4_h_r_21 <X> lc_trk_g1_5 +(15 6) routing sp4_h_r_5 <X> lc_trk_g1_5 +(15 6) routing sp4_v_t_8 <X> lc_trk_g1_5 +(15 7) routing lft_op_4 <X> lc_trk_g1_4 +(15 7) routing sp12_h_r_4 <X> lc_trk_g1_4 +(15 7) routing sp4_h_l_9 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_12 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(15 7) routing sp4_v_b_20 <X> lc_trk_g1_4 +(15 8) routing rgt_op_1 <X> lc_trk_g2_1 +(15 8) routing sp12_v_b_1 <X> lc_trk_g2_1 +(15 8) routing sp4_h_l_12 <X> lc_trk_g2_1 +(15 8) routing sp4_h_l_20 <X> lc_trk_g2_1 +(15 8) routing sp4_h_l_28 <X> lc_trk_g2_1 +(15 8) routing sp4_v_b_41 <X> lc_trk_g2_1 +(15 8) routing tnl_op_1 <X> lc_trk_g2_1 +(15 9) routing rgt_op_0 <X> lc_trk_g2_0 +(15 9) routing sp12_v_b_0 <X> lc_trk_g2_0 +(15 9) routing sp4_h_l_13 <X> lc_trk_g2_0 +(15 9) routing sp4_h_r_32 <X> lc_trk_g2_0 +(15 9) routing sp4_h_r_40 <X> lc_trk_g2_0 +(15 9) routing sp4_v_t_29 <X> lc_trk_g2_0 +(15 9) routing tnl_op_0 <X> lc_trk_g2_0 +(15 9) routing tnr_op_0 <X> lc_trk_g2_0 +(16 0) routing sp12_h_l_14 <X> lc_trk_g0_1 +(16 0) routing sp12_h_r_9 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_1 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_1 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_9 <X> lc_trk_g0_1 +(16 0) routing sp4_v_t_4 <X> lc_trk_g0_1 +(16 1) routing sp12_h_r_16 <X> lc_trk_g0_0 +(16 1) routing sp12_h_r_8 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_16 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_8 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_0 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_16 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_8 <X> lc_trk_g0_0 +(16 10) routing sp12_v_b_13 <X> lc_trk_g2_5 +(16 10) routing sp12_v_t_18 <X> lc_trk_g2_5 +(16 10) routing sp4_h_l_24 <X> lc_trk_g2_5 +(16 10) routing sp4_h_r_29 <X> lc_trk_g2_5 +(16 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_37 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_45 <X> lc_trk_g2_5 +(16 10) routing sp4_v_t_16 <X> lc_trk_g2_5 +(16 11) routing sp12_v_b_12 <X> lc_trk_g2_4 +(16 11) routing sp12_v_t_19 <X> lc_trk_g2_4 +(16 11) routing sp4_h_l_17 <X> lc_trk_g2_4 +(16 11) routing sp4_h_l_33 <X> lc_trk_g2_4 +(16 11) routing sp4_h_r_36 <X> lc_trk_g2_4 +(16 11) routing sp4_v_b_36 <X> lc_trk_g2_4 +(16 11) routing sp4_v_t_17 <X> lc_trk_g2_4 +(16 11) routing sp4_v_t_33 <X> lc_trk_g2_4 +(16 12) routing sp12_v_b_9 <X> lc_trk_g3_1 +(16 12) routing sp12_v_t_14 <X> lc_trk_g3_1 +(16 12) routing sp4_h_l_12 <X> lc_trk_g3_1 +(16 12) routing sp4_h_l_20 <X> lc_trk_g3_1 +(16 12) routing sp4_h_l_28 <X> lc_trk_g3_1 +(16 12) routing sp4_v_b_25 <X> lc_trk_g3_1 +(16 12) routing sp4_v_b_41 <X> lc_trk_g3_1 +(16 12) routing sp4_v_t_20 <X> lc_trk_g3_1 +(16 13) routing sp12_v_b_16 <X> lc_trk_g3_0 +(16 13) routing sp12_v_b_8 <X> lc_trk_g3_0 +(16 13) routing sp4_h_l_13 <X> lc_trk_g3_0 +(16 13) routing sp4_h_r_32 <X> lc_trk_g3_0 +(16 13) routing sp4_h_r_40 <X> lc_trk_g3_0 +(16 13) routing sp4_v_b_32 <X> lc_trk_g3_0 +(16 13) routing sp4_v_t_13 <X> lc_trk_g3_0 +(16 13) routing sp4_v_t_29 <X> lc_trk_g3_0 +(16 14) routing sp12_v_b_13 <X> lc_trk_g3_5 +(16 14) routing sp12_v_t_18 <X> lc_trk_g3_5 +(16 14) routing sp4_h_l_24 <X> lc_trk_g3_5 +(16 14) routing sp4_h_r_29 <X> lc_trk_g3_5 +(16 14) routing sp4_h_r_45 <X> lc_trk_g3_5 +(16 14) routing sp4_v_b_37 <X> lc_trk_g3_5 +(16 14) routing sp4_v_b_45 <X> lc_trk_g3_5 +(16 14) routing sp4_v_t_16 <X> lc_trk_g3_5 +(16 15) routing sp12_v_b_12 <X> lc_trk_g3_4 +(16 15) routing sp12_v_t_19 <X> lc_trk_g3_4 +(16 15) routing sp4_h_l_17 <X> lc_trk_g3_4 +(16 15) routing sp4_h_l_33 <X> lc_trk_g3_4 +(16 15) routing sp4_h_r_36 <X> lc_trk_g3_4 +(16 15) routing sp4_v_b_36 <X> lc_trk_g3_4 +(16 15) routing sp4_v_t_17 <X> lc_trk_g3_4 +(16 15) routing sp4_v_t_33 <X> lc_trk_g3_4 +(16 2) routing sp12_h_l_18 <X> lc_trk_g0_5 +(16 2) routing sp12_h_r_13 <X> lc_trk_g0_5 +(16 2) routing sp4_h_l_0 <X> lc_trk_g0_5 +(16 2) routing sp4_h_r_21 <X> lc_trk_g0_5 +(16 2) routing sp4_h_r_5 <X> lc_trk_g0_5 +(16 2) routing sp4_v_b_5 <X> lc_trk_g0_5 +(16 2) routing sp4_v_t_0 <X> lc_trk_g0_5 +(16 2) routing sp4_v_t_8 <X> lc_trk_g0_5 +(16 3) routing sp12_h_l_11 <X> lc_trk_g0_4 +(16 3) routing sp12_h_r_20 <X> lc_trk_g0_4 +(16 3) routing sp4_h_l_9 <X> lc_trk_g0_4 +(16 3) routing sp4_h_r_12 <X> lc_trk_g0_4 +(16 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(16 3) routing sp4_v_b_20 <X> lc_trk_g0_4 +(16 3) routing sp4_v_b_4 <X> lc_trk_g0_4 +(16 3) routing sp4_v_t_1 <X> lc_trk_g0_4 +(16 4) routing sp12_h_l_14 <X> lc_trk_g1_1 +(16 4) routing sp12_h_r_9 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_1 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_1 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_9 <X> lc_trk_g1_1 +(16 4) routing sp4_v_t_4 <X> lc_trk_g1_1 +(16 5) routing sp12_h_r_16 <X> lc_trk_g1_0 +(16 5) routing sp12_h_r_8 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_16 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_8 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_0 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_16 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(16 6) routing sp12_h_l_18 <X> lc_trk_g1_5 +(16 6) routing sp12_h_r_13 <X> lc_trk_g1_5 +(16 6) routing sp4_h_l_0 <X> lc_trk_g1_5 +(16 6) routing sp4_h_r_21 <X> lc_trk_g1_5 +(16 6) routing sp4_h_r_5 <X> lc_trk_g1_5 +(16 6) routing sp4_v_b_5 <X> lc_trk_g1_5 +(16 6) routing sp4_v_t_0 <X> lc_trk_g1_5 +(16 6) routing sp4_v_t_8 <X> lc_trk_g1_5 +(16 7) routing sp12_h_l_11 <X> lc_trk_g1_4 +(16 7) routing sp12_h_r_20 <X> lc_trk_g1_4 +(16 7) routing sp4_h_l_9 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_12 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(16 7) routing sp4_v_b_20 <X> lc_trk_g1_4 +(16 7) routing sp4_v_b_4 <X> lc_trk_g1_4 +(16 7) routing sp4_v_t_1 <X> lc_trk_g1_4 +(16 8) routing sp12_v_b_9 <X> lc_trk_g2_1 +(16 8) routing sp12_v_t_14 <X> lc_trk_g2_1 +(16 8) routing sp4_h_l_12 <X> lc_trk_g2_1 +(16 8) routing sp4_h_l_20 <X> lc_trk_g2_1 +(16 8) routing sp4_h_l_28 <X> lc_trk_g2_1 +(16 8) routing sp4_v_b_25 <X> lc_trk_g2_1 +(16 8) routing sp4_v_b_41 <X> lc_trk_g2_1 +(16 8) routing sp4_v_t_20 <X> lc_trk_g2_1 +(16 9) routing sp12_v_b_16 <X> lc_trk_g2_0 +(16 9) routing sp12_v_b_8 <X> lc_trk_g2_0 +(16 9) routing sp4_h_l_13 <X> lc_trk_g2_0 +(16 9) routing sp4_h_r_32 <X> lc_trk_g2_0 +(16 9) routing sp4_h_r_40 <X> lc_trk_g2_0 +(16 9) routing sp4_v_b_32 <X> lc_trk_g2_0 +(16 9) routing sp4_v_t_13 <X> lc_trk_g2_0 +(16 9) routing sp4_v_t_29 <X> lc_trk_g2_0 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_t_4 lc_trk_g0_1 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_13 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_18 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_24 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_16 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_19 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_33 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_17 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_33 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_12 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_8 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_32 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_32 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_29 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_13 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_18 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_24 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_29 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_37 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_16 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_19 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_33 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_33 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_13 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_0 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_0 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_11 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_9 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_t_4 lc_trk_g1_1 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_13 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_0 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_0 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_11 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_12 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_20 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_29 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 +(18 0) routing bnr_op_1 <X> lc_trk_g0_1 +(18 0) routing lft_op_1 <X> lc_trk_g0_1 +(18 0) routing sp12_h_r_1 <X> lc_trk_g0_1 +(18 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(18 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(18 0) routing sp4_v_b_1 <X> lc_trk_g0_1 +(18 0) routing sp4_v_b_9 <X> lc_trk_g0_1 +(18 1) routing bnr_op_1 <X> lc_trk_g0_1 +(18 1) routing sp12_h_l_14 <X> lc_trk_g0_1 +(18 1) routing sp12_h_r_1 <X> lc_trk_g0_1 +(18 1) routing sp4_h_r_1 <X> lc_trk_g0_1 +(18 1) routing sp4_h_r_17 <X> lc_trk_g0_1 +(18 1) routing sp4_r_v_b_34 <X> lc_trk_g0_1 +(18 1) routing sp4_v_b_9 <X> lc_trk_g0_1 +(18 10) routing bnl_op_5 <X> lc_trk_g2_5 +(18 10) routing sp12_v_b_5 <X> lc_trk_g2_5 +(18 10) routing sp4_h_l_24 <X> lc_trk_g2_5 +(18 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(18 10) routing sp4_v_b_37 <X> lc_trk_g2_5 +(18 10) routing sp4_v_t_16 <X> lc_trk_g2_5 +(18 11) routing bnl_op_5 <X> lc_trk_g2_5 +(18 11) routing sp12_v_b_5 <X> lc_trk_g2_5 +(18 11) routing sp12_v_t_18 <X> lc_trk_g2_5 +(18 11) routing sp4_h_r_29 <X> lc_trk_g2_5 +(18 11) routing sp4_h_r_45 <X> lc_trk_g2_5 +(18 11) routing sp4_r_v_b_37 <X> lc_trk_g2_5 +(18 11) routing sp4_v_b_37 <X> lc_trk_g2_5 +(18 11) routing tnl_op_5 <X> lc_trk_g2_5 +(18 12) routing bnl_op_1 <X> lc_trk_g3_1 +(18 12) routing rgt_op_1 <X> lc_trk_g3_1 +(18 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(18 12) routing sp4_h_l_20 <X> lc_trk_g3_1 +(18 12) routing sp4_h_l_28 <X> lc_trk_g3_1 +(18 12) routing sp4_v_b_25 <X> lc_trk_g3_1 +(18 12) routing sp4_v_t_20 <X> lc_trk_g3_1 +(18 13) routing bnl_op_1 <X> lc_trk_g3_1 +(18 13) routing sp12_v_b_1 <X> lc_trk_g3_1 +(18 13) routing sp12_v_t_14 <X> lc_trk_g3_1 +(18 13) routing sp4_h_l_12 <X> lc_trk_g3_1 +(18 13) routing sp4_h_l_28 <X> lc_trk_g3_1 +(18 13) routing sp4_r_v_b_41 <X> lc_trk_g3_1 +(18 13) routing sp4_v_t_20 <X> lc_trk_g3_1 +(18 13) routing tnl_op_1 <X> lc_trk_g3_1 +(18 14) routing bnl_op_5 <X> lc_trk_g3_5 +(18 14) routing rgt_op_5 <X> lc_trk_g3_5 +(18 14) routing sp12_v_b_5 <X> lc_trk_g3_5 +(18 14) routing sp4_h_l_24 <X> lc_trk_g3_5 +(18 14) routing sp4_h_r_45 <X> lc_trk_g3_5 +(18 14) routing sp4_v_b_37 <X> lc_trk_g3_5 +(18 14) routing sp4_v_t_16 <X> lc_trk_g3_5 +(18 15) routing bnl_op_5 <X> lc_trk_g3_5 +(18 15) routing sp12_v_b_5 <X> lc_trk_g3_5 +(18 15) routing sp12_v_t_18 <X> lc_trk_g3_5 +(18 15) routing sp4_h_r_29 <X> lc_trk_g3_5 +(18 15) routing sp4_h_r_45 <X> lc_trk_g3_5 +(18 15) routing sp4_r_v_b_45 <X> lc_trk_g3_5 +(18 15) routing sp4_v_b_37 <X> lc_trk_g3_5 +(18 2) routing bnr_op_5 <X> lc_trk_g0_5 +(18 2) routing lft_op_5 <X> lc_trk_g0_5 +(18 2) routing sp12_h_r_5 <X> lc_trk_g0_5 +(18 2) routing sp4_h_l_0 <X> lc_trk_g0_5 +(18 2) routing sp4_h_r_21 <X> lc_trk_g0_5 +(18 2) routing sp4_v_b_5 <X> lc_trk_g0_5 +(18 2) routing sp4_v_t_0 <X> lc_trk_g0_5 +(18 3) routing bnr_op_5 <X> lc_trk_g0_5 +(18 3) routing sp12_h_l_18 <X> lc_trk_g0_5 +(18 3) routing sp12_h_r_5 <X> lc_trk_g0_5 +(18 3) routing sp4_h_r_21 <X> lc_trk_g0_5 +(18 3) routing sp4_h_r_5 <X> lc_trk_g0_5 +(18 3) routing sp4_r_v_b_29 <X> lc_trk_g0_5 +(18 3) routing sp4_v_t_0 <X> lc_trk_g0_5 +(18 4) routing bnr_op_1 <X> lc_trk_g1_1 +(18 4) routing sp12_h_r_1 <X> lc_trk_g1_1 +(18 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(18 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(18 4) routing sp4_v_b_1 <X> lc_trk_g1_1 +(18 4) routing sp4_v_b_9 <X> lc_trk_g1_1 +(18 5) routing bnr_op_1 <X> lc_trk_g1_1 +(18 5) routing sp12_h_l_14 <X> lc_trk_g1_1 +(18 5) routing sp12_h_r_1 <X> lc_trk_g1_1 +(18 5) routing sp4_h_r_1 <X> lc_trk_g1_1 +(18 5) routing sp4_h_r_17 <X> lc_trk_g1_1 +(18 5) routing sp4_r_v_b_25 <X> lc_trk_g1_1 +(18 5) routing sp4_v_b_9 <X> lc_trk_g1_1 +(18 6) routing bnr_op_5 <X> lc_trk_g1_5 +(18 6) routing lft_op_5 <X> lc_trk_g1_5 +(18 6) routing sp12_h_r_5 <X> lc_trk_g1_5 +(18 6) routing sp4_h_l_0 <X> lc_trk_g1_5 +(18 6) routing sp4_h_r_21 <X> lc_trk_g1_5 +(18 6) routing sp4_v_b_5 <X> lc_trk_g1_5 +(18 6) routing sp4_v_t_0 <X> lc_trk_g1_5 +(18 7) routing bnr_op_5 <X> lc_trk_g1_5 +(18 7) routing sp12_h_l_18 <X> lc_trk_g1_5 +(18 7) routing sp12_h_r_5 <X> lc_trk_g1_5 +(18 7) routing sp4_h_r_21 <X> lc_trk_g1_5 +(18 7) routing sp4_h_r_5 <X> lc_trk_g1_5 +(18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5 +(18 7) routing sp4_v_t_0 <X> lc_trk_g1_5 +(18 8) routing bnl_op_1 <X> lc_trk_g2_1 +(18 8) routing rgt_op_1 <X> lc_trk_g2_1 +(18 8) routing sp12_v_b_1 <X> lc_trk_g2_1 +(18 8) routing sp4_h_l_20 <X> lc_trk_g2_1 +(18 8) routing sp4_h_l_28 <X> lc_trk_g2_1 +(18 8) routing sp4_v_b_25 <X> lc_trk_g2_1 +(18 8) routing sp4_v_t_20 <X> lc_trk_g2_1 +(18 9) routing bnl_op_1 <X> lc_trk_g2_1 +(18 9) routing sp12_v_b_1 <X> lc_trk_g2_1 +(18 9) routing sp12_v_t_14 <X> lc_trk_g2_1 +(18 9) routing sp4_h_l_12 <X> lc_trk_g2_1 +(18 9) routing sp4_h_l_28 <X> lc_trk_g2_1 +(18 9) routing sp4_r_v_b_33 <X> lc_trk_g2_1 +(18 9) routing sp4_v_t_20 <X> lc_trk_g2_1 +(18 9) routing tnl_op_1 <X> lc_trk_g2_1 +(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_b_3 sp4_v_t_0 +(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_t_1 +(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_b_23 +(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_t_18 sp4_v_t_11 +(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_r_2 sp4_h_l_0 +(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_r_12 +(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_r_6 sp4_h_r_15 +(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_r_4 sp4_h_l_3 +(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_t_4 sp4_v_t_2 +(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14 +(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_t_8 sp4_v_t_4 +(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16 +(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_b_19 +(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_b_13 sp4_v_b_18 +(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_t_16 sp4_v_t_8 +(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_b_20 +(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_r_16 +(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_r_18 sp4_h_r_21 +(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_r_22 +(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_l_21 sp4_h_r_23 +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_mult/lc_7/clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_mult/lc_7/clk +(2 3) routing lc_trk_g0_0 <X> wire_mult/lc_7/clk +(2 3) routing lc_trk_g1_1 <X> wire_mult/lc_7/clk +(2 3) routing lc_trk_g2_0 <X> wire_mult/lc_7/clk +(2 3) routing lc_trk_g3_1 <X> wire_mult/lc_7/clk +(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_l_11 sp4_h_r_18 +(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_l_13 sp4_h_l_6 +(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_l_9 +(21 0) routing bnr_op_3 <X> lc_trk_g0_3 +(21 0) routing lft_op_3 <X> lc_trk_g0_3 +(21 0) routing sp12_h_l_0 <X> lc_trk_g0_3 +(21 0) routing sp4_h_l_6 <X> lc_trk_g0_3 +(21 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(21 0) routing sp4_v_b_11 <X> lc_trk_g0_3 +(21 0) routing sp4_v_b_3 <X> lc_trk_g0_3 +(21 1) routing bnr_op_3 <X> lc_trk_g0_3 +(21 1) routing sp12_h_l_0 <X> lc_trk_g0_3 +(21 1) routing sp12_h_r_19 <X> lc_trk_g0_3 +(21 1) routing sp4_h_l_6 <X> lc_trk_g0_3 +(21 1) routing sp4_h_r_3 <X> lc_trk_g0_3 +(21 1) routing sp4_r_v_b_32 <X> lc_trk_g0_3 +(21 1) routing sp4_v_b_11 <X> lc_trk_g0_3 +(21 10) routing bnl_op_7 <X> lc_trk_g2_7 +(21 10) routing rgt_op_7 <X> lc_trk_g2_7 +(21 10) routing sp12_v_t_4 <X> lc_trk_g2_7 +(21 10) routing sp4_h_l_34 <X> lc_trk_g2_7 +(21 10) routing sp4_h_r_39 <X> lc_trk_g2_7 +(21 10) routing sp4_v_t_18 <X> lc_trk_g2_7 +(21 10) routing sp4_v_t_26 <X> lc_trk_g2_7 +(21 11) routing bnl_op_7 <X> lc_trk_g2_7 +(21 11) routing sp12_v_b_23 <X> lc_trk_g2_7 +(21 11) routing sp12_v_t_4 <X> lc_trk_g2_7 +(21 11) routing sp4_h_l_18 <X> lc_trk_g2_7 +(21 11) routing sp4_h_l_34 <X> lc_trk_g2_7 +(21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7 +(21 11) routing sp4_v_t_26 <X> lc_trk_g2_7 +(21 11) routing tnl_op_7 <X> lc_trk_g2_7 +(21 12) routing bnl_op_3 <X> lc_trk_g3_3 +(21 12) routing rgt_op_3 <X> lc_trk_g3_3 +(21 12) routing sp12_v_b_3 <X> lc_trk_g3_3 +(21 12) routing sp4_h_l_22 <X> lc_trk_g3_3 +(21 12) routing sp4_h_r_43 <X> lc_trk_g3_3 +(21 12) routing sp4_v_b_27 <X> lc_trk_g3_3 +(21 12) routing sp4_v_b_35 <X> lc_trk_g3_3 +(21 13) routing bnl_op_3 <X> lc_trk_g3_3 +(21 13) routing sp12_v_b_3 <X> lc_trk_g3_3 +(21 13) routing sp12_v_t_16 <X> lc_trk_g3_3 +(21 13) routing sp4_h_r_27 <X> lc_trk_g3_3 +(21 13) routing sp4_h_r_43 <X> lc_trk_g3_3 +(21 13) routing sp4_r_v_b_43 <X> lc_trk_g3_3 +(21 13) routing sp4_v_b_35 <X> lc_trk_g3_3 +(21 13) routing tnl_op_3 <X> lc_trk_g3_3 +(21 14) routing bnl_op_7 <X> lc_trk_g3_7 +(21 14) routing rgt_op_7 <X> lc_trk_g3_7 +(21 14) routing sp12_v_t_4 <X> lc_trk_g3_7 +(21 14) routing sp4_h_l_34 <X> lc_trk_g3_7 +(21 14) routing sp4_h_r_39 <X> lc_trk_g3_7 +(21 14) routing sp4_v_t_18 <X> lc_trk_g3_7 +(21 14) routing sp4_v_t_26 <X> lc_trk_g3_7 +(21 15) routing bnl_op_7 <X> lc_trk_g3_7 +(21 15) routing sp12_v_b_23 <X> lc_trk_g3_7 +(21 15) routing sp12_v_t_4 <X> lc_trk_g3_7 +(21 15) routing sp4_h_l_18 <X> lc_trk_g3_7 +(21 15) routing sp4_h_l_34 <X> lc_trk_g3_7 +(21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7 +(21 15) routing sp4_v_t_26 <X> lc_trk_g3_7 +(21 2) routing bnr_op_7 <X> lc_trk_g0_7 +(21 2) routing lft_op_7 <X> lc_trk_g0_7 +(21 2) routing sp12_h_l_4 <X> lc_trk_g0_7 +(21 2) routing sp4_h_r_15 <X> lc_trk_g0_7 +(21 2) routing sp4_h_r_23 <X> lc_trk_g0_7 +(21 2) routing sp4_v_b_7 <X> lc_trk_g0_7 +(21 2) routing sp4_v_t_2 <X> lc_trk_g0_7 +(21 3) routing bnr_op_7 <X> lc_trk_g0_7 +(21 3) routing sp12_h_l_4 <X> lc_trk_g0_7 +(21 3) routing sp12_h_r_23 <X> lc_trk_g0_7 +(21 3) routing sp4_h_r_23 <X> lc_trk_g0_7 +(21 3) routing sp4_h_r_7 <X> lc_trk_g0_7 +(21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7 +(21 3) routing sp4_v_t_2 <X> lc_trk_g0_7 +(21 4) routing bnr_op_3 <X> lc_trk_g1_3 +(21 4) routing lft_op_3 <X> lc_trk_g1_3 +(21 4) routing sp12_h_l_0 <X> lc_trk_g1_3 +(21 4) routing sp4_h_l_6 <X> lc_trk_g1_3 +(21 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(21 4) routing sp4_v_b_11 <X> lc_trk_g1_3 +(21 4) routing sp4_v_b_3 <X> lc_trk_g1_3 +(21 5) routing bnr_op_3 <X> lc_trk_g1_3 +(21 5) routing sp12_h_l_0 <X> lc_trk_g1_3 +(21 5) routing sp12_h_r_19 <X> lc_trk_g1_3 +(21 5) routing sp4_h_l_6 <X> lc_trk_g1_3 +(21 5) routing sp4_h_r_3 <X> lc_trk_g1_3 +(21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3 +(21 5) routing sp4_v_b_11 <X> lc_trk_g1_3 +(21 6) routing bnr_op_7 <X> lc_trk_g1_7 +(21 6) routing sp12_h_l_4 <X> lc_trk_g1_7 +(21 6) routing sp4_h_r_15 <X> lc_trk_g1_7 +(21 6) routing sp4_h_r_23 <X> lc_trk_g1_7 +(21 6) routing sp4_v_b_7 <X> lc_trk_g1_7 +(21 6) routing sp4_v_t_2 <X> lc_trk_g1_7 +(21 7) routing bnr_op_7 <X> lc_trk_g1_7 +(21 7) routing sp12_h_l_4 <X> lc_trk_g1_7 +(21 7) routing sp12_h_r_23 <X> lc_trk_g1_7 +(21 7) routing sp4_h_r_23 <X> lc_trk_g1_7 +(21 7) routing sp4_h_r_7 <X> lc_trk_g1_7 +(21 7) routing sp4_r_v_b_31 <X> lc_trk_g1_7 +(21 7) routing sp4_v_t_2 <X> lc_trk_g1_7 +(21 8) routing bnl_op_3 <X> lc_trk_g2_3 +(21 8) routing rgt_op_3 <X> lc_trk_g2_3 +(21 8) routing sp12_v_b_3 <X> lc_trk_g2_3 +(21 8) routing sp4_h_l_22 <X> lc_trk_g2_3 +(21 8) routing sp4_h_r_43 <X> lc_trk_g2_3 +(21 8) routing sp4_v_b_27 <X> lc_trk_g2_3 +(21 8) routing sp4_v_b_35 <X> lc_trk_g2_3 +(21 9) routing bnl_op_3 <X> lc_trk_g2_3 +(21 9) routing sp12_v_b_3 <X> lc_trk_g2_3 +(21 9) routing sp12_v_t_16 <X> lc_trk_g2_3 +(21 9) routing sp4_h_r_27 <X> lc_trk_g2_3 +(21 9) routing sp4_h_r_43 <X> lc_trk_g2_3 +(21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3 +(21 9) routing sp4_v_b_35 <X> lc_trk_g2_3 +(21 9) routing tnl_op_3 <X> lc_trk_g2_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_8 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_l_6 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_47 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_22 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_5 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_19 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_35 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_16 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_8 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_22 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_30 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_18 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_9 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_23 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_34 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_39 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_5 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_38 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_35 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_15 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_23 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_23 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_23 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_13 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_21 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_8 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_l_6 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_18 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_18 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_18 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_15 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_23 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_15 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_23 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_23 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_13 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_21 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_16 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_27 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_30 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_18 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_9 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_23 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 +(23 0) routing sp12_h_l_8 <X> lc_trk_g0_3 +(23 0) routing sp12_h_r_19 <X> lc_trk_g0_3 +(23 0) routing sp4_h_l_6 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_3 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_11 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_19 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_3 <X> lc_trk_g0_3 +(23 1) routing sp12_h_l_9 <X> lc_trk_g0_2 +(23 1) routing sp12_h_r_18 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_10 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_18 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_10 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_18 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_2 <X> lc_trk_g0_2 +(23 10) routing sp12_v_b_23 <X> lc_trk_g2_7 +(23 10) routing sp12_v_t_12 <X> lc_trk_g2_7 +(23 10) routing sp4_h_l_18 <X> lc_trk_g2_7 +(23 10) routing sp4_h_l_34 <X> lc_trk_g2_7 +(23 10) routing sp4_h_r_39 <X> lc_trk_g2_7 +(23 10) routing sp4_v_b_47 <X> lc_trk_g2_7 +(23 10) routing sp4_v_t_18 <X> lc_trk_g2_7 +(23 10) routing sp4_v_t_26 <X> lc_trk_g2_7 +(23 11) routing sp12_v_b_14 <X> lc_trk_g2_6 +(23 11) routing sp12_v_b_22 <X> lc_trk_g2_6 +(23 11) routing sp4_h_l_27 <X> lc_trk_g2_6 +(23 11) routing sp4_h_r_30 <X> lc_trk_g2_6 +(23 11) routing sp4_h_r_46 <X> lc_trk_g2_6 +(23 11) routing sp4_v_b_38 <X> lc_trk_g2_6 +(23 11) routing sp4_v_t_19 <X> lc_trk_g2_6 +(23 11) routing sp4_v_t_35 <X> lc_trk_g2_6 +(23 12) routing sp12_v_t_16 <X> lc_trk_g3_3 +(23 12) routing sp12_v_t_8 <X> lc_trk_g3_3 +(23 12) routing sp4_h_l_22 <X> lc_trk_g3_3 +(23 12) routing sp4_h_r_27 <X> lc_trk_g3_3 +(23 12) routing sp4_h_r_43 <X> lc_trk_g3_3 +(23 12) routing sp4_v_b_27 <X> lc_trk_g3_3 +(23 12) routing sp4_v_b_35 <X> lc_trk_g3_3 +(23 12) routing sp4_v_t_30 <X> lc_trk_g3_3 +(23 13) routing sp12_v_b_18 <X> lc_trk_g3_2 +(23 13) routing sp12_v_t_9 <X> lc_trk_g3_2 +(23 13) routing sp4_h_l_15 <X> lc_trk_g3_2 +(23 13) routing sp4_h_l_23 <X> lc_trk_g3_2 +(23 13) routing sp4_h_r_42 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_15 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_23 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_31 <X> lc_trk_g3_2 +(23 14) routing sp12_v_b_23 <X> lc_trk_g3_7 +(23 14) routing sp12_v_t_12 <X> lc_trk_g3_7 +(23 14) routing sp4_h_l_18 <X> lc_trk_g3_7 +(23 14) routing sp4_h_l_34 <X> lc_trk_g3_7 +(23 14) routing sp4_h_r_39 <X> lc_trk_g3_7 +(23 14) routing sp4_v_b_47 <X> lc_trk_g3_7 +(23 14) routing sp4_v_t_18 <X> lc_trk_g3_7 +(23 14) routing sp4_v_t_26 <X> lc_trk_g3_7 +(23 15) routing sp12_v_b_14 <X> lc_trk_g3_6 +(23 15) routing sp12_v_b_22 <X> lc_trk_g3_6 +(23 15) routing sp4_h_l_27 <X> lc_trk_g3_6 +(23 15) routing sp4_h_r_30 <X> lc_trk_g3_6 +(23 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(23 15) routing sp4_v_b_38 <X> lc_trk_g3_6 +(23 15) routing sp4_v_t_19 <X> lc_trk_g3_6 +(23 15) routing sp4_v_t_35 <X> lc_trk_g3_6 +(23 2) routing sp12_h_r_15 <X> lc_trk_g0_7 +(23 2) routing sp12_h_r_23 <X> lc_trk_g0_7 +(23 2) routing sp4_h_r_15 <X> lc_trk_g0_7 +(23 2) routing sp4_h_r_23 <X> lc_trk_g0_7 +(23 2) routing sp4_h_r_7 <X> lc_trk_g0_7 +(23 2) routing sp4_v_b_23 <X> lc_trk_g0_7 +(23 2) routing sp4_v_b_7 <X> lc_trk_g0_7 +(23 2) routing sp4_v_t_2 <X> lc_trk_g0_7 +(23 3) routing sp12_h_l_13 <X> lc_trk_g0_6 +(23 3) routing sp12_h_l_21 <X> lc_trk_g0_6 +(23 3) routing sp4_h_l_3 <X> lc_trk_g0_6 +(23 3) routing sp4_h_r_22 <X> lc_trk_g0_6 +(23 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(23 3) routing sp4_v_b_14 <X> lc_trk_g0_6 +(23 3) routing sp4_v_b_6 <X> lc_trk_g0_6 +(23 3) routing sp4_v_t_11 <X> lc_trk_g0_6 +(23 4) routing sp12_h_l_8 <X> lc_trk_g1_3 +(23 4) routing sp12_h_r_19 <X> lc_trk_g1_3 +(23 4) routing sp4_h_l_6 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_3 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_11 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_19 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_3 <X> lc_trk_g1_3 +(23 5) routing sp12_h_l_9 <X> lc_trk_g1_2 +(23 5) routing sp12_h_r_18 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_18 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_10 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_18 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_2 <X> lc_trk_g1_2 +(23 6) routing sp12_h_r_15 <X> lc_trk_g1_7 +(23 6) routing sp12_h_r_23 <X> lc_trk_g1_7 +(23 6) routing sp4_h_r_15 <X> lc_trk_g1_7 +(23 6) routing sp4_h_r_23 <X> lc_trk_g1_7 +(23 6) routing sp4_h_r_7 <X> lc_trk_g1_7 +(23 6) routing sp4_v_b_23 <X> lc_trk_g1_7 +(23 6) routing sp4_v_b_7 <X> lc_trk_g1_7 +(23 6) routing sp4_v_t_2 <X> lc_trk_g1_7 +(23 7) routing sp12_h_l_13 <X> lc_trk_g1_6 +(23 7) routing sp12_h_l_21 <X> lc_trk_g1_6 +(23 7) routing sp4_h_l_3 <X> lc_trk_g1_6 +(23 7) routing sp4_h_r_22 <X> lc_trk_g1_6 +(23 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_14 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_6 <X> lc_trk_g1_6 +(23 7) routing sp4_v_t_11 <X> lc_trk_g1_6 +(23 8) routing sp12_v_t_16 <X> lc_trk_g2_3 +(23 8) routing sp12_v_t_8 <X> lc_trk_g2_3 +(23 8) routing sp4_h_l_22 <X> lc_trk_g2_3 +(23 8) routing sp4_h_r_27 <X> lc_trk_g2_3 +(23 8) routing sp4_h_r_43 <X> lc_trk_g2_3 +(23 8) routing sp4_v_b_27 <X> lc_trk_g2_3 +(23 8) routing sp4_v_b_35 <X> lc_trk_g2_3 +(23 8) routing sp4_v_t_30 <X> lc_trk_g2_3 +(23 9) routing sp12_v_b_18 <X> lc_trk_g2_2 +(23 9) routing sp12_v_t_9 <X> lc_trk_g2_2 +(23 9) routing sp4_h_l_15 <X> lc_trk_g2_2 +(23 9) routing sp4_h_l_23 <X> lc_trk_g2_2 +(23 9) routing sp4_h_r_42 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_15 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_23 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_31 <X> lc_trk_g2_2 +(24 0) routing lft_op_3 <X> lc_trk_g0_3 +(24 0) routing sp12_h_l_0 <X> lc_trk_g0_3 +(24 0) routing sp4_h_l_6 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_3 <X> lc_trk_g0_3 +(24 0) routing sp4_v_b_19 <X> lc_trk_g0_3 +(24 1) routing lft_op_2 <X> lc_trk_g0_2 +(24 1) routing sp12_h_r_2 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_10 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_18 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(24 1) routing sp4_v_b_18 <X> lc_trk_g0_2 +(24 10) routing rgt_op_7 <X> lc_trk_g2_7 +(24 10) routing sp12_v_t_4 <X> lc_trk_g2_7 +(24 10) routing sp4_h_l_18 <X> lc_trk_g2_7 +(24 10) routing sp4_h_l_34 <X> lc_trk_g2_7 +(24 10) routing sp4_h_r_39 <X> lc_trk_g2_7 +(24 10) routing sp4_v_b_47 <X> lc_trk_g2_7 +(24 10) routing tnl_op_7 <X> lc_trk_g2_7 +(24 10) routing tnr_op_7 <X> lc_trk_g2_7 +(24 11) routing sp12_v_t_5 <X> lc_trk_g2_6 +(24 11) routing sp4_h_l_27 <X> lc_trk_g2_6 +(24 11) routing sp4_h_r_30 <X> lc_trk_g2_6 +(24 11) routing sp4_h_r_46 <X> lc_trk_g2_6 +(24 11) routing sp4_v_t_35 <X> lc_trk_g2_6 +(24 11) routing tnr_op_6 <X> lc_trk_g2_6 +(24 12) routing rgt_op_3 <X> lc_trk_g3_3 +(24 12) routing sp12_v_b_3 <X> lc_trk_g3_3 +(24 12) routing sp4_h_l_22 <X> lc_trk_g3_3 +(24 12) routing sp4_h_r_27 <X> lc_trk_g3_3 +(24 12) routing sp4_h_r_43 <X> lc_trk_g3_3 +(24 12) routing sp4_v_t_30 <X> lc_trk_g3_3 +(24 12) routing tnl_op_3 <X> lc_trk_g3_3 +(24 12) routing tnr_op_3 <X> lc_trk_g3_3 +(24 13) routing rgt_op_2 <X> lc_trk_g3_2 +(24 13) routing sp12_v_b_2 <X> lc_trk_g3_2 +(24 13) routing sp4_h_l_15 <X> lc_trk_g3_2 +(24 13) routing sp4_h_l_23 <X> lc_trk_g3_2 +(24 13) routing sp4_h_r_42 <X> lc_trk_g3_2 +(24 13) routing sp4_v_t_31 <X> lc_trk_g3_2 +(24 13) routing tnl_op_2 <X> lc_trk_g3_2 +(24 13) routing tnr_op_2 <X> lc_trk_g3_2 +(24 14) routing rgt_op_7 <X> lc_trk_g3_7 +(24 14) routing sp12_v_t_4 <X> lc_trk_g3_7 +(24 14) routing sp4_h_l_18 <X> lc_trk_g3_7 +(24 14) routing sp4_h_l_34 <X> lc_trk_g3_7 +(24 14) routing sp4_h_r_39 <X> lc_trk_g3_7 +(24 14) routing sp4_v_b_47 <X> lc_trk_g3_7 +(24 14) routing tnr_op_7 <X> lc_trk_g3_7 +(24 15) routing rgt_op_6 <X> lc_trk_g3_6 +(24 15) routing sp12_v_t_5 <X> lc_trk_g3_6 +(24 15) routing sp4_h_l_27 <X> lc_trk_g3_6 +(24 15) routing sp4_h_r_30 <X> lc_trk_g3_6 +(24 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(24 15) routing sp4_v_t_35 <X> lc_trk_g3_6 +(24 15) routing tnl_op_6 <X> lc_trk_g3_6 +(24 15) routing tnr_op_6 <X> lc_trk_g3_6 +(24 2) routing lft_op_7 <X> lc_trk_g0_7 +(24 2) routing sp12_h_l_4 <X> lc_trk_g0_7 +(24 2) routing sp4_h_r_15 <X> lc_trk_g0_7 +(24 2) routing sp4_h_r_23 <X> lc_trk_g0_7 +(24 2) routing sp4_h_r_7 <X> lc_trk_g0_7 +(24 2) routing sp4_v_b_23 <X> lc_trk_g0_7 +(24 3) routing lft_op_6 <X> lc_trk_g0_6 +(24 3) routing sp12_h_r_6 <X> lc_trk_g0_6 +(24 3) routing sp4_h_l_3 <X> lc_trk_g0_6 +(24 3) routing sp4_h_r_22 <X> lc_trk_g0_6 +(24 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(24 3) routing sp4_v_t_11 <X> lc_trk_g0_6 +(24 4) routing lft_op_3 <X> lc_trk_g1_3 +(24 4) routing sp12_h_l_0 <X> lc_trk_g1_3 +(24 4) routing sp4_h_l_6 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_3 <X> lc_trk_g1_3 +(24 4) routing sp4_v_b_19 <X> lc_trk_g1_3 +(24 5) routing lft_op_2 <X> lc_trk_g1_2 +(24 5) routing sp12_h_r_2 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_18 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(24 5) routing sp4_v_b_18 <X> lc_trk_g1_2 +(24 6) routing sp12_h_l_4 <X> lc_trk_g1_7 +(24 6) routing sp4_h_r_15 <X> lc_trk_g1_7 +(24 6) routing sp4_h_r_23 <X> lc_trk_g1_7 +(24 6) routing sp4_h_r_7 <X> lc_trk_g1_7 +(24 6) routing sp4_v_b_23 <X> lc_trk_g1_7 +(24 7) routing lft_op_6 <X> lc_trk_g1_6 +(24 7) routing sp12_h_r_6 <X> lc_trk_g1_6 +(24 7) routing sp4_h_l_3 <X> lc_trk_g1_6 +(24 7) routing sp4_h_r_22 <X> lc_trk_g1_6 +(24 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(24 7) routing sp4_v_t_11 <X> lc_trk_g1_6 +(24 8) routing rgt_op_3 <X> lc_trk_g2_3 +(24 8) routing sp12_v_b_3 <X> lc_trk_g2_3 +(24 8) routing sp4_h_l_22 <X> lc_trk_g2_3 +(24 8) routing sp4_h_r_27 <X> lc_trk_g2_3 +(24 8) routing sp4_h_r_43 <X> lc_trk_g2_3 +(24 8) routing sp4_v_t_30 <X> lc_trk_g2_3 +(24 8) routing tnl_op_3 <X> lc_trk_g2_3 +(24 8) routing tnr_op_3 <X> lc_trk_g2_3 +(24 9) routing rgt_op_2 <X> lc_trk_g2_2 +(24 9) routing sp12_v_b_2 <X> lc_trk_g2_2 +(24 9) routing sp4_h_l_15 <X> lc_trk_g2_2 +(24 9) routing sp4_h_l_23 <X> lc_trk_g2_2 +(24 9) routing sp4_h_r_42 <X> lc_trk_g2_2 +(24 9) routing sp4_v_t_31 <X> lc_trk_g2_2 +(24 9) routing tnl_op_2 <X> lc_trk_g2_2 +(24 9) routing tnr_op_2 <X> lc_trk_g2_2 +(25 0) routing bnr_op_2 <X> lc_trk_g0_2 +(25 0) routing lft_op_2 <X> lc_trk_g0_2 +(25 0) routing sp12_h_r_2 <X> lc_trk_g0_2 +(25 0) routing sp4_h_r_10 <X> lc_trk_g0_2 +(25 0) routing sp4_h_r_18 <X> lc_trk_g0_2 +(25 0) routing sp4_v_b_10 <X> lc_trk_g0_2 +(25 0) routing sp4_v_b_2 <X> lc_trk_g0_2 +(25 1) routing bnr_op_2 <X> lc_trk_g0_2 +(25 1) routing sp12_h_r_18 <X> lc_trk_g0_2 +(25 1) routing sp12_h_r_2 <X> lc_trk_g0_2 +(25 1) routing sp4_h_r_18 <X> lc_trk_g0_2 +(25 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(25 1) routing sp4_r_v_b_33 <X> lc_trk_g0_2 +(25 1) routing sp4_v_b_10 <X> lc_trk_g0_2 +(25 10) routing bnl_op_6 <X> lc_trk_g2_6 +(25 10) routing sp12_v_t_5 <X> lc_trk_g2_6 +(25 10) routing sp4_h_l_27 <X> lc_trk_g2_6 +(25 10) routing sp4_h_r_46 <X> lc_trk_g2_6 +(25 10) routing sp4_v_b_38 <X> lc_trk_g2_6 +(25 10) routing sp4_v_t_19 <X> lc_trk_g2_6 +(25 11) routing bnl_op_6 <X> lc_trk_g2_6 +(25 11) routing sp12_v_b_22 <X> lc_trk_g2_6 +(25 11) routing sp12_v_t_5 <X> lc_trk_g2_6 +(25 11) routing sp4_h_r_30 <X> lc_trk_g2_6 +(25 11) routing sp4_h_r_46 <X> lc_trk_g2_6 +(25 11) routing sp4_r_v_b_38 <X> lc_trk_g2_6 +(25 11) routing sp4_v_b_38 <X> lc_trk_g2_6 +(25 12) routing bnl_op_2 <X> lc_trk_g3_2 +(25 12) routing rgt_op_2 <X> lc_trk_g3_2 +(25 12) routing sp12_v_b_2 <X> lc_trk_g3_2 +(25 12) routing sp4_h_l_23 <X> lc_trk_g3_2 +(25 12) routing sp4_h_r_42 <X> lc_trk_g3_2 +(25 12) routing sp4_v_t_15 <X> lc_trk_g3_2 +(25 12) routing sp4_v_t_23 <X> lc_trk_g3_2 +(25 13) routing bnl_op_2 <X> lc_trk_g3_2 +(25 13) routing sp12_v_b_18 <X> lc_trk_g3_2 +(25 13) routing sp12_v_b_2 <X> lc_trk_g3_2 +(25 13) routing sp4_h_l_15 <X> lc_trk_g3_2 +(25 13) routing sp4_h_r_42 <X> lc_trk_g3_2 +(25 13) routing sp4_r_v_b_42 <X> lc_trk_g3_2 +(25 13) routing sp4_v_t_23 <X> lc_trk_g3_2 +(25 13) routing tnl_op_2 <X> lc_trk_g3_2 +(25 14) routing bnl_op_6 <X> lc_trk_g3_6 +(25 14) routing rgt_op_6 <X> lc_trk_g3_6 +(25 14) routing sp12_v_t_5 <X> lc_trk_g3_6 +(25 14) routing sp4_h_l_27 <X> lc_trk_g3_6 +(25 14) routing sp4_h_r_46 <X> lc_trk_g3_6 +(25 14) routing sp4_v_b_38 <X> lc_trk_g3_6 +(25 14) routing sp4_v_t_19 <X> lc_trk_g3_6 +(25 15) routing bnl_op_6 <X> lc_trk_g3_6 +(25 15) routing sp12_v_b_22 <X> lc_trk_g3_6 +(25 15) routing sp12_v_t_5 <X> lc_trk_g3_6 +(25 15) routing sp4_h_r_30 <X> lc_trk_g3_6 +(25 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(25 15) routing sp4_r_v_b_46 <X> lc_trk_g3_6 +(25 15) routing sp4_v_b_38 <X> lc_trk_g3_6 +(25 15) routing tnl_op_6 <X> lc_trk_g3_6 +(25 2) routing bnr_op_6 <X> lc_trk_g0_6 +(25 2) routing lft_op_6 <X> lc_trk_g0_6 +(25 2) routing sp12_h_r_6 <X> lc_trk_g0_6 +(25 2) routing sp4_h_l_3 <X> lc_trk_g0_6 +(25 2) routing sp4_h_r_22 <X> lc_trk_g0_6 +(25 2) routing sp4_v_b_14 <X> lc_trk_g0_6 +(25 2) routing sp4_v_b_6 <X> lc_trk_g0_6 +(25 3) routing bnr_op_6 <X> lc_trk_g0_6 +(25 3) routing sp12_h_l_21 <X> lc_trk_g0_6 +(25 3) routing sp12_h_r_6 <X> lc_trk_g0_6 +(25 3) routing sp4_h_r_22 <X> lc_trk_g0_6 +(25 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(25 3) routing sp4_r_v_b_30 <X> lc_trk_g0_6 +(25 3) routing sp4_v_b_14 <X> lc_trk_g0_6 +(25 4) routing bnr_op_2 <X> lc_trk_g1_2 +(25 4) routing lft_op_2 <X> lc_trk_g1_2 +(25 4) routing sp12_h_r_2 <X> lc_trk_g1_2 +(25 4) routing sp4_h_r_10 <X> lc_trk_g1_2 +(25 4) routing sp4_h_r_18 <X> lc_trk_g1_2 +(25 4) routing sp4_v_b_10 <X> lc_trk_g1_2 +(25 4) routing sp4_v_b_2 <X> lc_trk_g1_2 +(25 5) routing bnr_op_2 <X> lc_trk_g1_2 +(25 5) routing sp12_h_r_18 <X> lc_trk_g1_2 +(25 5) routing sp12_h_r_2 <X> lc_trk_g1_2 +(25 5) routing sp4_h_r_18 <X> lc_trk_g1_2 +(25 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(25 5) routing sp4_r_v_b_26 <X> lc_trk_g1_2 +(25 5) routing sp4_v_b_10 <X> lc_trk_g1_2 +(25 6) routing bnr_op_6 <X> lc_trk_g1_6 +(25 6) routing lft_op_6 <X> lc_trk_g1_6 +(25 6) routing sp12_h_r_6 <X> lc_trk_g1_6 +(25 6) routing sp4_h_l_3 <X> lc_trk_g1_6 +(25 6) routing sp4_h_r_22 <X> lc_trk_g1_6 +(25 6) routing sp4_v_b_14 <X> lc_trk_g1_6 +(25 6) routing sp4_v_b_6 <X> lc_trk_g1_6 +(25 7) routing bnr_op_6 <X> lc_trk_g1_6 +(25 7) routing sp12_h_l_21 <X> lc_trk_g1_6 +(25 7) routing sp12_h_r_6 <X> lc_trk_g1_6 +(25 7) routing sp4_h_r_22 <X> lc_trk_g1_6 +(25 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6 +(25 7) routing sp4_v_b_14 <X> lc_trk_g1_6 +(25 8) routing bnl_op_2 <X> lc_trk_g2_2 +(25 8) routing rgt_op_2 <X> lc_trk_g2_2 +(25 8) routing sp12_v_b_2 <X> lc_trk_g2_2 +(25 8) routing sp4_h_l_23 <X> lc_trk_g2_2 +(25 8) routing sp4_h_r_42 <X> lc_trk_g2_2 +(25 8) routing sp4_v_t_15 <X> lc_trk_g2_2 +(25 8) routing sp4_v_t_23 <X> lc_trk_g2_2 +(25 9) routing bnl_op_2 <X> lc_trk_g2_2 +(25 9) routing sp12_v_b_18 <X> lc_trk_g2_2 +(25 9) routing sp12_v_b_2 <X> lc_trk_g2_2 +(25 9) routing sp4_h_l_15 <X> lc_trk_g2_2 +(25 9) routing sp4_h_r_42 <X> lc_trk_g2_2 +(25 9) routing sp4_r_v_b_34 <X> lc_trk_g2_2 +(25 9) routing sp4_v_t_23 <X> lc_trk_g2_2 +(25 9) routing tnl_op_2 <X> lc_trk_g2_2 +(26 0) routing lc_trk_g0_4 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g0_6 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_5 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_7 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_4 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_6 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_5 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_2 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_6 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_3 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_7 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_2 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_6 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_3 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(27 0) routing lc_trk_g1_0 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(27 1) routing lc_trk_g1_1 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_3 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_5 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_7 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_1 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_3 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_5 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(27 10) routing lc_trk_g1_1 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(27 12) routing lc_trk_g1_0 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(27 14) routing lc_trk_g1_1 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(27 2) routing lc_trk_g1_1 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(27 4) routing lc_trk_g1_0 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(27 6) routing lc_trk_g1_1 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(27 8) routing lc_trk_g1_0 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(28 0) routing lc_trk_g2_1 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(28 1) routing lc_trk_g2_0 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_2 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_4 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_6 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_1 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_3 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_5 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(28 10) routing lc_trk_g2_0 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(28 12) routing lc_trk_g2_1 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(28 14) routing lc_trk_g2_0 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(28 2) routing lc_trk_g2_0 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(28 4) routing lc_trk_g2_1 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(28 6) routing lc_trk_g2_0 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(28 8) routing lc_trk_g2_1 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_6 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_6 wire_mult/lc_0/in_1 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_7 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_7 wire_mult/lc_0/in_0 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_7 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_7 wire_mult/lc_5/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_6 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_6 wire_mult/lc_6/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_7 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_7 wire_mult/lc_7/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_7 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_7 wire_mult/lc_1/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_6 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_6 wire_mult/lc_2/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_7 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_7 wire_mult/lc_3/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_6 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_6 wire_mult/lc_4/in_1 +(3 0) routing sp12_h_r_0 <X> sp12_v_b_0 +(3 0) routing sp12_v_t_23 <X> sp12_v_b_0 +(3 1) routing sp12_h_l_23 <X> sp12_v_b_0 +(3 1) routing sp12_h_r_0 <X> sp12_v_b_0 +(3 10) routing sp12_v_t_22 <X> sp12_h_l_22 +(3 11) routing sp12_v_b_1 <X> sp12_h_l_22 +(3 12) routing sp12_v_b_1 <X> sp12_h_r_1 +(3 12) routing sp12_v_t_22 <X> sp12_h_r_1 +(3 13) routing sp12_h_l_22 <X> sp12_h_r_1 +(3 13) routing sp12_v_b_1 <X> sp12_h_r_1 +(3 14) routing sp12_h_r_1 <X> sp12_v_t_22 +(3 14) routing sp12_v_b_1 <X> sp12_v_t_22 +(3 15) routing sp12_h_l_22 <X> sp12_v_t_22 +(3 15) routing sp12_h_r_1 <X> sp12_v_t_22 +(3 2) routing sp12_h_r_0 <X> sp12_h_l_23 +(3 2) routing sp12_v_t_23 <X> sp12_h_l_23 +(3 3) routing sp12_h_r_0 <X> sp12_h_l_23 +(3 3) routing sp12_v_b_0 <X> sp12_h_l_23 +(3 4) routing sp12_v_b_0 <X> sp12_h_r_0 +(3 4) routing sp12_v_t_23 <X> sp12_h_r_0 +(3 5) routing sp12_h_l_23 <X> sp12_h_r_0 +(3 5) routing sp12_v_b_0 <X> sp12_h_r_0 +(3 6) routing sp12_h_r_0 <X> sp12_v_t_23 +(3 6) routing sp12_v_b_0 <X> sp12_v_t_23 +(3 7) routing sp12_h_l_23 <X> sp12_v_t_23 +(3 7) routing sp12_h_r_0 <X> sp12_v_t_23 +(3 8) routing sp12_h_r_1 <X> sp12_v_b_1 +(3 8) routing sp12_v_t_22 <X> sp12_v_b_1 +(3 9) routing sp12_h_l_22 <X> sp12_v_b_1 +(3 9) routing sp12_h_r_1 <X> sp12_v_b_1 +(30 0) routing lc_trk_g0_5 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_3 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(30 10) routing lc_trk_g0_4 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_2 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(30 12) routing lc_trk_g0_5 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_3 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(30 14) routing lc_trk_g0_4 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_2 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(30 2) routing lc_trk_g0_4 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_2 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(30 4) routing lc_trk_g0_5 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_3 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(30 6) routing lc_trk_g0_4 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_2 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(30 8) routing lc_trk_g0_5 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_3 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(31 0) routing lc_trk_g0_5 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_3 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(31 10) routing lc_trk_g0_4 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_2 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(31 12) routing lc_trk_g0_5 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_3 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(31 14) routing lc_trk_g0_4 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_2 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(31 2) routing lc_trk_g0_4 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_2 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(31 4) routing lc_trk_g0_5 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_3 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(31 6) routing lc_trk_g0_4 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_2 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(31 8) routing lc_trk_g0_5 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_3 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_6 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_1 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_6 wire_mult/lc_0/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_7 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_0 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_7 wire_mult/lc_5/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_6 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_1 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_6 wire_mult/lc_6/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_7 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_0 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_7 wire_mult/lc_7/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_7 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_0 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_7 wire_mult/lc_1/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_6 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_1 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_6 wire_mult/lc_2/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_7 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_0 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_7 wire_mult/lc_3/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_6 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_1 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_6 wire_mult/lc_4/in_3 +(33 0) routing lc_trk_g2_1 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(33 10) routing lc_trk_g2_0 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(33 12) routing lc_trk_g2_1 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(33 14) routing lc_trk_g2_0 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(33 2) routing lc_trk_g2_0 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(33 4) routing lc_trk_g2_1 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(33 6) routing lc_trk_g2_0 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(33 8) routing lc_trk_g2_1 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(34 0) routing lc_trk_g1_0 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(34 10) routing lc_trk_g1_1 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(34 12) routing lc_trk_g1_0 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(34 14) routing lc_trk_g1_1 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(34 2) routing lc_trk_g1_1 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(34 4) routing lc_trk_g1_0 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(34 6) routing lc_trk_g1_1 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(34 8) routing lc_trk_g1_0 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(36 0) LC_0 Logic Functioning bit +(36 1) LC_0 Logic Functioning bit +(36 10) LC_5 Logic Functioning bit +(36 11) LC_5 Logic Functioning bit +(36 12) LC_6 Logic Functioning bit +(36 13) LC_6 Logic Functioning bit +(36 14) LC_7 Logic Functioning bit +(36 15) LC_7 Logic Functioning bit +(36 2) LC_1 Logic Functioning bit +(36 3) LC_1 Logic Functioning bit +(36 4) LC_2 Logic Functioning bit +(36 5) LC_2 Logic Functioning bit +(36 6) LC_3 Logic Functioning bit +(36 7) LC_3 Logic Functioning bit +(36 8) LC_4 Logic Functioning bit +(36 9) LC_4 Logic Functioning bit +(37 0) LC_0 Logic Functioning bit +(37 1) LC_0 Logic Functioning bit +(37 10) LC_5 Logic Functioning bit +(37 11) LC_5 Logic Functioning bit +(37 12) LC_6 Logic Functioning bit +(37 13) LC_6 Logic Functioning bit +(37 14) LC_7 Logic Functioning bit +(37 15) LC_7 Logic Functioning bit +(37 2) LC_1 Logic Functioning bit +(37 3) LC_1 Logic Functioning bit +(37 4) LC_2 Logic Functioning bit +(37 5) LC_2 Logic Functioning bit +(37 6) LC_3 Logic Functioning bit +(37 7) LC_3 Logic Functioning bit +(37 8) LC_4 Logic Functioning bit +(37 9) LC_4 Logic Functioning bit +(4 0) routing sp4_h_l_37 <X> sp4_v_b_0 +(4 0) routing sp4_h_l_43 <X> sp4_v_b_0 +(4 0) routing sp4_v_t_37 <X> sp4_v_b_0 +(4 0) routing sp4_v_t_41 <X> sp4_v_b_0 +(4 1) routing sp4_v_b_6 <X> sp4_h_r_0 +(4 1) routing sp4_v_t_42 <X> sp4_h_r_0 +(4 10) routing sp4_h_r_0 <X> sp4_v_t_43 +(4 10) routing sp4_h_r_6 <X> sp4_v_t_43 +(4 10) routing sp4_v_b_10 <X> sp4_v_t_43 +(4 10) routing sp4_v_b_6 <X> sp4_v_t_43 +(4 11) routing sp4_h_r_10 <X> sp4_h_l_43 +(4 11) routing sp4_h_r_3 <X> sp4_h_l_43 +(4 11) routing sp4_v_b_1 <X> sp4_h_l_43 +(4 11) routing sp4_v_t_37 <X> sp4_h_l_43 +(4 12) routing sp4_h_l_38 <X> sp4_v_b_9 +(4 12) routing sp4_h_l_44 <X> sp4_v_b_9 +(4 12) routing sp4_v_t_36 <X> sp4_v_b_9 +(4 12) routing sp4_v_t_44 <X> sp4_v_b_9 +(4 13) routing sp4_v_b_3 <X> sp4_h_r_9 +(4 13) routing sp4_v_t_41 <X> sp4_h_r_9 +(4 14) routing sp4_h_r_3 <X> sp4_v_t_44 +(4 14) routing sp4_h_r_9 <X> sp4_v_t_44 +(4 14) routing sp4_v_b_1 <X> sp4_v_t_44 +(4 14) routing sp4_v_b_9 <X> sp4_v_t_44 +(4 15) routing sp4_h_r_6 <X> sp4_h_l_44 +(4 15) routing sp4_v_b_4 <X> sp4_h_l_44 +(4 15) routing sp4_v_t_38 <X> sp4_h_l_44 +(4 2) routing sp4_h_r_0 <X> sp4_v_t_37 +(4 2) routing sp4_h_r_6 <X> sp4_v_t_37 +(4 2) routing sp4_v_b_0 <X> sp4_v_t_37 +(4 2) routing sp4_v_b_4 <X> sp4_v_t_37 +(4 3) routing sp4_h_r_4 <X> sp4_h_l_37 +(4 3) routing sp4_v_b_7 <X> sp4_h_l_37 +(4 3) routing sp4_v_t_43 <X> sp4_h_l_37 +(4 4) routing sp4_h_l_38 <X> sp4_v_b_3 +(4 4) routing sp4_h_l_44 <X> sp4_v_b_3 +(4 4) routing sp4_v_t_38 <X> sp4_v_b_3 +(4 4) routing sp4_v_t_42 <X> sp4_v_b_3 +(4 5) routing sp4_h_l_37 <X> sp4_h_r_3 +(4 5) routing sp4_v_b_9 <X> sp4_h_r_3 +(4 5) routing sp4_v_t_47 <X> sp4_h_r_3 +(4 6) routing sp4_h_r_3 <X> sp4_v_t_38 +(4 6) routing sp4_h_r_9 <X> sp4_v_t_38 +(4 6) routing sp4_v_b_3 <X> sp4_v_t_38 +(4 6) routing sp4_v_b_7 <X> sp4_v_t_38 +(4 7) routing sp4_h_r_0 <X> sp4_h_l_38 +(4 7) routing sp4_v_b_10 <X> sp4_h_l_38 +(4 7) routing sp4_v_t_44 <X> sp4_h_l_38 +(4 8) routing sp4_h_l_37 <X> sp4_v_b_6 +(4 8) routing sp4_h_l_43 <X> sp4_v_b_6 +(4 8) routing sp4_v_t_43 <X> sp4_v_b_6 +(4 8) routing sp4_v_t_47 <X> sp4_v_b_6 +(4 9) routing sp4_h_l_38 <X> sp4_h_r_6 +(4 9) routing sp4_v_b_0 <X> sp4_h_r_6 +(4 9) routing sp4_v_t_36 <X> sp4_h_r_6 +(42 0) LC_0 Logic Functioning bit +(42 1) LC_0 Logic Functioning bit +(42 10) LC_5 Logic Functioning bit +(42 11) LC_5 Logic Functioning bit +(42 12) LC_6 Logic Functioning bit +(42 13) LC_6 Logic Functioning bit +(42 14) LC_7 Logic Functioning bit +(42 15) LC_7 Logic Functioning bit +(42 2) LC_1 Logic Functioning bit +(42 3) LC_1 Logic Functioning bit +(42 4) LC_2 Logic Functioning bit +(42 5) LC_2 Logic Functioning bit +(42 6) LC_3 Logic Functioning bit +(42 7) LC_3 Logic Functioning bit +(42 8) LC_4 Logic Functioning bit +(42 9) LC_4 Logic Functioning bit +(43 0) LC_0 Logic Functioning bit +(43 1) LC_0 Logic Functioning bit +(43 10) LC_5 Logic Functioning bit +(43 11) LC_5 Logic Functioning bit +(43 12) LC_6 Logic Functioning bit +(43 13) LC_6 Logic Functioning bit +(43 14) LC_7 Logic Functioning bit +(43 15) LC_7 Logic Functioning bit +(43 2) LC_1 Logic Functioning bit +(43 3) LC_1 Logic Functioning bit +(43 4) LC_2 Logic Functioning bit +(43 5) LC_2 Logic Functioning bit +(43 6) LC_3 Logic Functioning bit +(43 7) LC_3 Logic Functioning bit +(43 8) LC_4 Logic Functioning bit +(43 9) LC_4 Logic Functioning bit +(46 0) Enable bit of Mux _out_links/OutMux7_0 => wire_mult/mult/O_16 sp4_h_r_16 +(46 1) Enable bit of Mux _out_links/OutMux6_0 => wire_mult/mult/O_16 sp4_h_r_0 +(46 10) Enable bit of Mux _out_links/OutMux7_5 => wire_mult/mult/O_21 sp4_h_l_15 +(46 11) Enable bit of Mux _out_links/OutMux6_5 => wire_mult/mult/O_21 sp4_h_r_10 +(46 12) Enable bit of Mux _out_links/OutMux7_6 => wire_mult/mult/O_22 sp4_h_l_17 +(46 13) Enable bit of Mux _out_links/OutMux6_6 => wire_mult/mult/O_22 sp4_h_r_12 +(46 14) Enable bit of Mux _out_links/OutMux7_7 => wire_mult/mult/O_23 sp4_h_r_30 +(46 15) Enable bit of Mux _out_links/OutMux6_7 => wire_mult/mult/O_23 sp4_h_l_3 +(46 2) Enable bit of Mux _out_links/OutMux7_1 => wire_mult/mult/O_17 sp4_h_r_18 +(46 3) Enable bit of Mux _out_links/OutMux6_1 => wire_mult/mult/O_17 sp4_h_r_2 +(46 4) Enable bit of Mux _out_links/OutMux7_2 => wire_mult/mult/O_18 sp4_h_l_9 +(46 5) Enable bit of Mux _out_links/OutMux6_2 => wire_mult/mult/O_18 sp4_h_r_4 +(46 6) Enable bit of Mux _out_links/OutMux7_3 => wire_mult/mult/O_19 sp4_h_r_22 +(46 7) Enable bit of Mux _out_links/OutMux6_3 => wire_mult/mult/O_19 sp4_h_r_6 +(46 8) Enable bit of Mux _out_links/OutMux7_4 => wire_mult/mult/O_20 sp4_h_l_13 +(46 9) Enable bit of Mux _out_links/OutMux6_4 => wire_mult/mult/O_20 sp4_h_r_8 +(47 0) Enable bit of Mux _out_links/OutMux5_0 => wire_mult/mult/O_16 sp12_h_r_8 +(47 1) Enable bit of Mux _out_links/OutMux8_0 => wire_mult/mult/O_16 sp4_h_r_32 +(47 10) Enable bit of Mux _out_links/OutMux4_5 => wire_mult/mult/O_21 sp12_h_r_2 +(47 11) Enable bit of Mux _out_links/OutMux8_5 => wire_mult/mult/O_21 sp4_h_r_42 +(47 12) Enable bit of Mux _out_links/OutMux4_6 => wire_mult/mult/O_22 sp12_h_r_4 +(47 13) Enable bit of Mux _out_links/OutMux8_6 => wire_mult/mult/O_22 sp4_h_l_33 +(47 14) Enable bit of Mux _out_links/OutMux4_7 => wire_mult/mult/O_23 sp12_h_r_6 +(47 15) Enable bit of Mux _out_links/OutMux8_7 => wire_mult/mult/O_23 sp4_h_r_46 +(47 2) Enable bit of Mux _out_links/OutMux5_1 => wire_mult/mult/O_17 sp12_h_l_9 +(47 3) Enable bit of Mux _out_links/OutMux8_1 => wire_mult/mult/O_17 sp4_h_l_23 +(47 4) Enable bit of Mux _out_links/OutMux5_2 => wire_mult/mult/O_18 sp12_h_l_11 +(47 5) Enable bit of Mux _out_links/OutMux8_2 => wire_mult/mult/O_18 sp4_h_r_36 +(47 6) Enable bit of Mux _out_links/OutMux5_3 => wire_mult/mult/O_19 sp12_h_l_13 +(47 7) Enable bit of Mux _out_links/OutMux8_3 => wire_mult/mult/O_19 sp4_h_l_27 +(47 8) Enable bit of Mux _out_links/OutMux4_4 => wire_mult/mult/O_20 sp12_h_r_0 +(47 9) Enable bit of Mux _out_links/OutMux8_4 => wire_mult/mult/O_20 sp4_h_r_40 +(48 0) Enable bit of Mux _out_links/OutMux0_0 => wire_mult/mult/O_16 sp4_v_b_0 +(48 1) Enable bit of Mux _out_links/OutMux1_0 => wire_mult/mult/O_16 sp4_v_b_16 +(48 10) Enable bit of Mux _out_links/OutMux5_5 => wire_mult/mult/O_21 sp12_h_r_18 +(48 11) Enable bit of Mux _out_links/OutMux0_5 => wire_mult/mult/O_21 sp4_v_b_10 +(48 12) Enable bit of Mux _out_links/OutMux5_6 => wire_mult/mult/O_22 sp12_h_r_20 +(48 13) Enable bit of Mux _out_links/OutMux0_6 => wire_mult/mult/O_22 sp4_v_t_1 +(48 14) Enable bit of Mux _out_links/OutMux5_7 => wire_mult/mult/O_23 sp12_h_l_21 +(48 15) Enable bit of Mux _out_links/OutMux0_7 => wire_mult/mult/O_23 sp4_v_b_14 +(48 2) Enable bit of Mux _out_links/OutMux0_1 => wire_mult/mult/O_17 sp4_v_b_2 +(48 3) Enable bit of Mux _out_links/OutMux1_1 => wire_mult/mult/O_17 sp4_v_b_18 +(48 4) Enable bit of Mux _out_links/OutMux0_2 => wire_mult/mult/O_18 sp4_v_b_4 +(48 5) Enable bit of Mux _out_links/OutMux1_2 => wire_mult/mult/O_18 sp4_v_b_20 +(48 6) Enable bit of Mux _out_links/OutMux0_3 => wire_mult/mult/O_19 sp4_v_b_6 +(48 7) Enable bit of Mux _out_links/OutMux1_3 => wire_mult/mult/O_19 sp4_v_t_11 +(48 8) Enable bit of Mux _out_links/OutMux5_4 => wire_mult/mult/O_20 sp12_h_r_16 +(48 9) Enable bit of Mux _out_links/OutMux0_4 => wire_mult/mult/O_20 sp4_v_b_8 +(5 0) routing sp4_v_b_0 <X> sp4_h_r_0 +(5 0) routing sp4_v_b_6 <X> sp4_h_r_0 +(5 0) routing sp4_v_t_37 <X> sp4_h_r_0 +(5 1) routing sp4_h_l_37 <X> sp4_v_b_0 +(5 1) routing sp4_h_l_43 <X> sp4_v_b_0 +(5 1) routing sp4_h_r_0 <X> sp4_v_b_0 +(5 1) routing sp4_v_t_44 <X> sp4_v_b_0 +(5 10) routing sp4_h_r_3 <X> sp4_h_l_43 +(5 10) routing sp4_v_b_6 <X> sp4_h_l_43 +(5 10) routing sp4_v_t_37 <X> sp4_h_l_43 +(5 10) routing sp4_v_t_43 <X> sp4_h_l_43 +(5 11) routing sp4_h_l_43 <X> sp4_v_t_43 +(5 11) routing sp4_h_r_0 <X> sp4_v_t_43 +(5 11) routing sp4_h_r_6 <X> sp4_v_t_43 +(5 11) routing sp4_v_b_3 <X> sp4_v_t_43 +(5 12) routing sp4_v_b_3 <X> sp4_h_r_9 +(5 12) routing sp4_v_b_9 <X> sp4_h_r_9 +(5 12) routing sp4_v_t_44 <X> sp4_h_r_9 +(5 13) routing sp4_h_l_38 <X> sp4_v_b_9 +(5 13) routing sp4_h_l_44 <X> sp4_v_b_9 +(5 13) routing sp4_h_r_9 <X> sp4_v_b_9 +(5 13) routing sp4_v_t_43 <X> sp4_v_b_9 +(5 14) routing sp4_h_r_6 <X> sp4_h_l_44 +(5 14) routing sp4_v_b_9 <X> sp4_h_l_44 +(5 14) routing sp4_v_t_38 <X> sp4_h_l_44 +(5 14) routing sp4_v_t_44 <X> sp4_h_l_44 +(5 15) routing sp4_h_l_44 <X> sp4_v_t_44 +(5 15) routing sp4_h_r_3 <X> sp4_v_t_44 +(5 15) routing sp4_h_r_9 <X> sp4_v_t_44 +(5 15) routing sp4_v_b_6 <X> sp4_v_t_44 +(5 2) routing sp4_v_b_0 <X> sp4_h_l_37 +(5 2) routing sp4_v_t_37 <X> sp4_h_l_37 +(5 2) routing sp4_v_t_43 <X> sp4_h_l_37 +(5 3) routing sp4_h_l_37 <X> sp4_v_t_37 +(5 3) routing sp4_h_r_0 <X> sp4_v_t_37 +(5 3) routing sp4_h_r_6 <X> sp4_v_t_37 +(5 3) routing sp4_v_b_9 <X> sp4_v_t_37 +(5 4) routing sp4_h_l_37 <X> sp4_h_r_3 +(5 4) routing sp4_v_b_3 <X> sp4_h_r_3 +(5 4) routing sp4_v_b_9 <X> sp4_h_r_3 +(5 4) routing sp4_v_t_38 <X> sp4_h_r_3 +(5 5) routing sp4_h_l_38 <X> sp4_v_b_3 +(5 5) routing sp4_h_l_44 <X> sp4_v_b_3 +(5 5) routing sp4_h_r_3 <X> sp4_v_b_3 +(5 5) routing sp4_v_t_37 <X> sp4_v_b_3 +(5 6) routing sp4_h_r_0 <X> sp4_h_l_38 +(5 6) routing sp4_v_b_3 <X> sp4_h_l_38 +(5 6) routing sp4_v_t_38 <X> sp4_h_l_38 +(5 6) routing sp4_v_t_44 <X> sp4_h_l_38 +(5 7) routing sp4_h_l_38 <X> sp4_v_t_38 +(5 7) routing sp4_h_r_3 <X> sp4_v_t_38 +(5 7) routing sp4_h_r_9 <X> sp4_v_t_38 +(5 7) routing sp4_v_b_0 <X> sp4_v_t_38 +(5 8) routing sp4_h_l_38 <X> sp4_h_r_6 +(5 8) routing sp4_v_b_0 <X> sp4_h_r_6 +(5 8) routing sp4_v_b_6 <X> sp4_h_r_6 +(5 8) routing sp4_v_t_43 <X> sp4_h_r_6 +(5 9) routing sp4_h_l_37 <X> sp4_v_b_6 +(5 9) routing sp4_h_l_43 <X> sp4_v_b_6 +(5 9) routing sp4_h_r_6 <X> sp4_v_b_6 +(5 9) routing sp4_v_t_38 <X> sp4_v_b_6 +(50 0) Cascade buffer Enable bit: MULT2_LC00_inmux02_5 +(50 10) Cascade buffer Enable bit: MULT2_LC05_inmux02_5 +(50 12) Cascade buffer Enable bit: MULT2_LC06_inmux02_5 +(50 14) Cascade buffer Enable bit: MULT2_LC07_inmux02_5 +(50 2) Cascade buffer Enable bit: MULT2_LC01_inmux02_5 +(50 4) Cascade buffer Enable bit: MULT2_LC02_inmux02_5 +(50 6) Cascade buffer Enable bit: MULT2_LC03_inmux02_5 +(50 8) Cascade buffer Enable bit: MULT2_LC04_inmux02_5 +(51 0) Enable bit of Mux _out_links/OutMux3_0 => wire_mult/mult/O_16 sp12_v_b_0 +(51 1) Enable bit of Mux _out_links/OutMux2_0 => wire_mult/mult/O_16 sp4_v_b_32 +(51 10) Enable bit of Mux _out_links/OutMux2_5 => wire_mult/mult/O_21 sp4_v_t_31 +(51 11) Enable bit of Mux _out_links/OutMux1_5 => wire_mult/mult/O_21 sp4_v_t_15 +(51 12) Enable bit of Mux _out_links/OutMux2_6 => wire_mult/mult/O_22 sp4_v_t_33 +(51 13) Enable bit of Mux _out_links/OutMux1_6 => wire_mult/mult/O_22 sp4_v_t_17 +(51 14) Enable bit of Mux _out_links/OutMux2_7 => wire_mult/mult/O_23 sp4_v_t_35 +(51 15) Enable bit of Mux _out_links/OutMux1_7 => wire_mult/mult/O_23 sp4_v_t_19 +(51 2) Enable bit of Mux _out_links/OutMux3_1 => wire_mult/mult/O_17 sp12_v_b_2 +(51 3) Enable bit of Mux _out_links/OutMux2_1 => wire_mult/mult/O_17 sp4_v_t_23 +(51 4) Enable bit of Mux _out_links/OutMux3_2 => wire_mult/mult/O_18 sp12_v_t_3 +(51 5) Enable bit of Mux _out_links/OutMux2_2 => wire_mult/mult/O_18 sp4_v_b_36 +(51 6) Enable bit of Mux _out_links/OutMux3_3 => wire_mult/mult/O_19 sp12_v_t_5 +(51 7) Enable bit of Mux _out_links/OutMux2_3 => wire_mult/mult/O_19 sp4_v_b_38 +(51 8) Enable bit of Mux _out_links/OutMux2_4 => wire_mult/mult/O_20 sp4_v_t_29 +(51 9) Enable bit of Mux _out_links/OutMux1_4 => wire_mult/mult/O_20 sp4_v_t_13 +(52 0) Enable bit of Mux _out_links/OutMux4_0 => wire_mult/mult/O_16 sp12_v_b_16 +(52 1) Enable bit of Mux _out_links/OutMux9_0 => wire_mult/mult/O_16 sp4_r_v_b_1 +(52 10) Enable bit of Mux _out_links/OutMux3_5 => wire_mult/mult/O_21 sp12_v_t_9 +(52 11) Enable bit of Mux _out_links/OutMux9_5 => wire_mult/mult/O_21 sp4_r_v_b_11 +(52 12) Enable bit of Mux _out_links/OutMux3_6 => wire_mult/mult/O_22 sp12_v_b_12 +(52 13) Enable bit of Mux _out_links/OutMux9_6 => wire_mult/mult/O_22 sp4_r_v_b_13 +(52 14) Enable bit of Mux _out_links/OutMux3_7 => wire_mult/mult/O_23 sp12_v_b_14 +(52 15) Enable bit of Mux _out_links/OutMux9_7 => wire_mult/mult/O_23 sp4_r_v_b_15 +(52 2) Enable bit of Mux _out_links/OutMux4_1 => wire_mult/mult/O_17 sp12_v_b_18 +(52 3) Enable bit of Mux _out_links/OutMux9_1 => wire_mult/mult/O_17 sp4_r_v_b_3 +(52 4) Enable bit of Mux _out_links/OutMux4_2 => wire_mult/mult/O_18 sp12_v_t_19 +(52 5) Enable bit of Mux _out_links/OutMux9_2 => wire_mult/mult/O_18 sp4_r_v_b_5 +(52 6) Enable bit of Mux _out_links/OutMux4_3 => wire_mult/mult/O_19 sp12_v_b_22 +(52 7) Enable bit of Mux _out_links/OutMux9_3 => wire_mult/mult/O_19 sp4_r_v_b_7 +(52 8) Enable bit of Mux _out_links/OutMux3_4 => wire_mult/mult/O_20 sp12_v_b_8 +(52 9) Enable bit of Mux _out_links/OutMux9_4 => wire_mult/mult/O_20 sp4_r_v_b_9 +(53 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_mult/mult/O_16 sp4_r_v_b_17 +(53 1) Enable bit of Mux _out_links/OutMuxb_0 => wire_mult/mult/O_16 sp4_r_v_b_33 +(53 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_mult/mult/O_21 sp4_r_v_b_27 +(53 11) Enable bit of Mux _out_links/OutMuxb_5 => wire_mult/mult/O_21 sp4_r_v_b_43 +(53 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_mult/mult/O_22 sp4_r_v_b_29 +(53 13) Enable bit of Mux _out_links/OutMuxb_6 => wire_mult/mult/O_22 sp4_r_v_b_45 +(53 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_mult/mult/O_23 sp4_r_v_b_31 +(53 15) Enable bit of Mux _out_links/OutMuxb_7 => wire_mult/mult/O_23 sp4_r_v_b_47 +(53 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_mult/mult/O_17 sp4_r_v_b_19 +(53 3) Enable bit of Mux _out_links/OutMuxb_1 => wire_mult/mult/O_17 sp4_r_v_b_35 +(53 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_mult/mult/O_18 sp4_r_v_b_21 +(53 5) Enable bit of Mux _out_links/OutMuxb_2 => wire_mult/mult/O_18 sp4_r_v_b_37 +(53 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_mult/mult/O_19 sp4_r_v_b_23 +(53 7) Enable bit of Mux _out_links/OutMuxb_3 => wire_mult/mult/O_19 sp4_r_v_b_39 +(53 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_mult/mult/O_20 sp4_r_v_b_25 +(53 9) Enable bit of Mux _out_links/OutMuxb_4 => wire_mult/mult/O_20 sp4_r_v_b_41 +(6 0) routing sp4_h_l_43 <X> sp4_v_b_0 +(6 0) routing sp4_h_r_7 <X> sp4_v_b_0 +(6 0) routing sp4_v_t_41 <X> sp4_v_b_0 +(6 0) routing sp4_v_t_44 <X> sp4_v_b_0 +(6 1) routing sp4_v_b_0 <X> sp4_h_r_0 +(6 1) routing sp4_v_b_6 <X> sp4_h_r_0 +(6 10) routing sp4_h_l_36 <X> sp4_v_t_43 +(6 10) routing sp4_h_r_0 <X> sp4_v_t_43 +(6 10) routing sp4_v_b_10 <X> sp4_v_t_43 +(6 10) routing sp4_v_b_3 <X> sp4_v_t_43 +(6 11) routing sp4_h_r_10 <X> sp4_h_l_43 +(6 11) routing sp4_h_r_6 <X> sp4_h_l_43 +(6 11) routing sp4_v_t_37 <X> sp4_h_l_43 +(6 11) routing sp4_v_t_43 <X> sp4_h_l_43 +(6 12) routing sp4_h_l_38 <X> sp4_v_b_9 +(6 12) routing sp4_h_r_4 <X> sp4_v_b_9 +(6 12) routing sp4_v_t_36 <X> sp4_v_b_9 +(6 12) routing sp4_v_t_43 <X> sp4_v_b_9 +(6 13) routing sp4_h_l_44 <X> sp4_h_r_9 +(6 13) routing sp4_v_b_3 <X> sp4_h_r_9 +(6 13) routing sp4_v_b_9 <X> sp4_h_r_9 +(6 14) routing sp4_h_l_41 <X> sp4_v_t_44 +(6 14) routing sp4_h_r_3 <X> sp4_v_t_44 +(6 14) routing sp4_v_b_1 <X> sp4_v_t_44 +(6 14) routing sp4_v_b_6 <X> sp4_v_t_44 +(6 15) routing sp4_v_t_38 <X> sp4_h_l_44 +(6 15) routing sp4_v_t_44 <X> sp4_h_l_44 +(6 2) routing sp4_h_l_42 <X> sp4_v_t_37 +(6 2) routing sp4_h_r_6 <X> sp4_v_t_37 +(6 2) routing sp4_v_b_4 <X> sp4_v_t_37 +(6 2) routing sp4_v_b_9 <X> sp4_v_t_37 +(6 3) routing sp4_h_r_0 <X> sp4_h_l_37 +(6 3) routing sp4_h_r_4 <X> sp4_h_l_37 +(6 3) routing sp4_v_t_37 <X> sp4_h_l_37 +(6 3) routing sp4_v_t_43 <X> sp4_h_l_37 +(6 4) routing sp4_h_l_44 <X> sp4_v_b_3 +(6 4) routing sp4_h_r_10 <X> sp4_v_b_3 +(6 4) routing sp4_v_t_37 <X> sp4_v_b_3 +(6 4) routing sp4_v_t_42 <X> sp4_v_b_3 +(6 5) routing sp4_h_l_38 <X> sp4_h_r_3 +(6 5) routing sp4_v_b_3 <X> sp4_h_r_3 +(6 5) routing sp4_v_b_9 <X> sp4_h_r_3 +(6 6) routing sp4_h_l_47 <X> sp4_v_t_38 +(6 6) routing sp4_h_r_9 <X> sp4_v_t_38 +(6 6) routing sp4_v_b_0 <X> sp4_v_t_38 +(6 6) routing sp4_v_b_7 <X> sp4_v_t_38 +(6 7) routing sp4_v_t_38 <X> sp4_h_l_38 +(6 7) routing sp4_v_t_44 <X> sp4_h_l_38 +(6 8) routing sp4_h_l_37 <X> sp4_v_b_6 +(6 8) routing sp4_h_r_1 <X> sp4_v_b_6 +(6 8) routing sp4_v_t_38 <X> sp4_v_b_6 +(6 8) routing sp4_v_t_47 <X> sp4_v_b_6 +(6 9) routing sp4_v_b_0 <X> sp4_h_r_6 +(6 9) routing sp4_v_b_6 <X> sp4_h_r_6 +(7 0) MAC16 functional bit: MULT2_bram_cbit_1 +(7 1) MAC16 functional bit: MULT2_bram_cbit_0 +(7 2) MAC16 functional bit: MULT2_bram_cbit_3 +(7 3) MAC16 functional bit: MULT2_bram_cbit_2 +(7 4) MAC16 functional bit: MULT2_bram_cbit_5 +(7 5) MAC16 functional bit: MULT2_bram_cbit_4 +(7 6) MAC16 functional bit: MULT2_bram_cbit_7 +(7 7) MAC16 functional bit: MULT2_bram_cbit_6 +(8 0) routing sp4_h_l_40 <X> sp4_h_r_1 +(8 0) routing sp4_v_b_1 <X> sp4_h_r_1 +(8 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(8 1) routing sp4_h_l_36 <X> sp4_v_b_1 +(8 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(8 1) routing sp4_h_r_1 <X> sp4_v_b_1 +(8 1) routing sp4_v_t_47 <X> sp4_v_b_1 +(8 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(8 10) routing sp4_v_t_42 <X> sp4_h_l_42 +(8 11) routing sp4_h_l_42 <X> sp4_v_t_42 +(8 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(8 11) routing sp4_h_r_7 <X> sp4_v_t_42 +(8 11) routing sp4_v_b_4 <X> sp4_v_t_42 +(8 12) routing sp4_h_l_39 <X> sp4_h_r_10 +(8 12) routing sp4_h_l_47 <X> sp4_h_r_10 +(8 12) routing sp4_v_b_10 <X> sp4_h_r_10 +(8 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(8 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(8 13) routing sp4_h_l_47 <X> sp4_v_b_10 +(8 13) routing sp4_h_r_10 <X> sp4_v_b_10 +(8 13) routing sp4_v_t_42 <X> sp4_v_b_10 +(8 14) routing sp4_h_r_10 <X> sp4_h_l_47 +(8 14) routing sp4_h_r_2 <X> sp4_h_l_47 +(8 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(8 14) routing sp4_v_t_47 <X> sp4_h_l_47 +(8 15) routing sp4_h_l_47 <X> sp4_v_t_47 +(8 15) routing sp4_h_r_10 <X> sp4_v_t_47 +(8 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(8 15) routing sp4_v_b_7 <X> sp4_v_t_47 +(8 2) routing sp4_v_t_36 <X> sp4_h_l_36 +(8 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(8 3) routing sp4_h_l_36 <X> sp4_v_t_36 +(8 3) routing sp4_h_r_1 <X> sp4_v_t_36 +(8 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(8 3) routing sp4_v_b_10 <X> sp4_v_t_36 +(8 4) routing sp4_h_l_45 <X> sp4_h_r_4 +(8 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(8 4) routing sp4_v_b_4 <X> sp4_h_r_4 +(8 5) routing sp4_h_l_41 <X> sp4_v_b_4 +(8 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(8 5) routing sp4_h_r_4 <X> sp4_v_b_4 +(8 5) routing sp4_v_t_36 <X> sp4_v_b_4 +(8 6) routing sp4_h_r_4 <X> sp4_h_l_41 +(8 6) routing sp4_h_r_8 <X> sp4_h_l_41 +(8 6) routing sp4_v_t_41 <X> sp4_h_l_41 +(8 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(8 7) routing sp4_h_l_41 <X> sp4_v_t_41 +(8 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(8 7) routing sp4_h_r_4 <X> sp4_v_t_41 +(8 7) routing sp4_v_b_1 <X> sp4_v_t_41 +(8 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(8 8) routing sp4_v_b_7 <X> sp4_h_r_7 +(8 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(8 9) routing sp4_h_l_42 <X> sp4_v_b_7 +(8 9) routing sp4_h_r_7 <X> sp4_v_b_7 +(8 9) routing sp4_v_t_41 <X> sp4_v_b_7 +(9 0) routing sp4_v_b_1 <X> sp4_h_r_1 +(9 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(9 0) routing sp4_v_t_36 <X> sp4_h_r_1 +(9 1) routing sp4_h_l_36 <X> sp4_v_b_1 +(9 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(9 1) routing sp4_v_t_36 <X> sp4_v_b_1 +(9 1) routing sp4_v_t_40 <X> sp4_v_b_1 +(9 10) routing sp4_h_r_4 <X> sp4_h_l_42 +(9 10) routing sp4_v_b_7 <X> sp4_h_l_42 +(9 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(9 10) routing sp4_v_t_42 <X> sp4_h_l_42 +(9 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(9 11) routing sp4_h_r_7 <X> sp4_v_t_42 +(9 11) routing sp4_v_b_11 <X> sp4_v_t_42 +(9 11) routing sp4_v_b_7 <X> sp4_v_t_42 +(9 12) routing sp4_v_b_10 <X> sp4_h_r_10 +(9 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(9 12) routing sp4_v_t_47 <X> sp4_h_r_10 +(9 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(9 13) routing sp4_h_l_47 <X> sp4_v_b_10 +(9 13) routing sp4_v_t_39 <X> sp4_v_b_10 +(9 13) routing sp4_v_t_47 <X> sp4_v_b_10 +(9 14) routing sp4_v_b_10 <X> sp4_h_l_47 +(9 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(9 14) routing sp4_v_t_47 <X> sp4_h_l_47 +(9 15) routing sp4_h_r_10 <X> sp4_v_t_47 +(9 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(9 15) routing sp4_v_b_10 <X> sp4_v_t_47 +(9 15) routing sp4_v_b_2 <X> sp4_v_t_47 +(9 2) routing sp4_h_r_10 <X> sp4_h_l_36 +(9 2) routing sp4_v_b_1 <X> sp4_h_l_36 +(9 2) routing sp4_v_t_36 <X> sp4_h_l_36 +(9 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(9 3) routing sp4_h_r_1 <X> sp4_v_t_36 +(9 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(9 3) routing sp4_v_b_1 <X> sp4_v_t_36 +(9 3) routing sp4_v_b_5 <X> sp4_v_t_36 +(9 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(9 4) routing sp4_v_b_4 <X> sp4_h_r_4 +(9 4) routing sp4_v_t_41 <X> sp4_h_r_4 +(9 5) routing sp4_h_l_41 <X> sp4_v_b_4 +(9 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(9 5) routing sp4_v_t_41 <X> sp4_v_b_4 +(9 5) routing sp4_v_t_45 <X> sp4_v_b_4 +(9 6) routing sp4_v_b_4 <X> sp4_h_l_41 +(9 6) routing sp4_v_t_41 <X> sp4_h_l_41 +(9 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(9 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(9 7) routing sp4_h_r_4 <X> sp4_v_t_41 +(9 7) routing sp4_v_b_4 <X> sp4_v_t_41 +(9 7) routing sp4_v_b_8 <X> sp4_v_t_41 +(9 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(9 8) routing sp4_v_b_7 <X> sp4_h_r_7 +(9 8) routing sp4_v_t_42 <X> sp4_h_r_7 +(9 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(9 9) routing sp4_h_l_42 <X> sp4_v_b_7 +(9 9) routing sp4_v_t_42 <X> sp4_v_b_7 +(9 9) routing sp4_v_t_46 <X> sp4_v_b_7 diff --git a/icefuzz/cached_dsp3_5k.txt b/icefuzz/cached_dsp3_5k.txt index e69de29..f42a3f9 100644 --- a/icefuzz/cached_dsp3_5k.txt +++ b/icefuzz/cached_dsp3_5k.txt @@ -0,0 +1,3159 @@ +(0 10) routing glb_netwk_2 <X> glb2local_2 +(0 10) routing glb_netwk_3 <X> glb2local_2 +(0 10) routing glb_netwk_6 <X> glb2local_2 +(0 10) routing glb_netwk_7 <X> glb2local_2 +(0 11) routing glb_netwk_1 <X> glb2local_2 +(0 11) routing glb_netwk_3 <X> glb2local_2 +(0 11) routing glb_netwk_5 <X> glb2local_2 +(0 11) routing glb_netwk_7 <X> glb2local_2 +(0 12) routing glb_netwk_2 <X> glb2local_3 +(0 12) routing glb_netwk_3 <X> glb2local_3 +(0 12) routing glb_netwk_6 <X> glb2local_3 +(0 12) routing glb_netwk_7 <X> glb2local_3 +(0 13) routing glb_netwk_1 <X> glb2local_3 +(0 13) routing glb_netwk_3 <X> glb2local_3 +(0 13) routing glb_netwk_5 <X> glb2local_3 +(0 13) routing glb_netwk_7 <X> glb2local_3 +(0 14) routing glb_netwk_4 <X> wire_mult/lc_7/s_r +(0 14) routing glb_netwk_6 <X> wire_mult/lc_7/s_r +(0 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/s_r +(0 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/s_r +(0 15) routing glb_netwk_2 <X> wire_mult/lc_7/s_r +(0 15) routing glb_netwk_6 <X> wire_mult/lc_7/s_r +(0 15) routing lc_trk_g1_5 <X> wire_mult/lc_7/s_r +(0 15) routing lc_trk_g3_5 <X> wire_mult/lc_7/s_r +(0 6) routing glb_netwk_3 <X> glb2local_0 +(0 6) routing glb_netwk_6 <X> glb2local_0 +(0 6) routing glb_netwk_7 <X> glb2local_0 +(0 7) routing glb_netwk_1 <X> glb2local_0 +(0 7) routing glb_netwk_3 <X> glb2local_0 +(0 7) routing glb_netwk_5 <X> glb2local_0 +(0 7) routing glb_netwk_7 <X> glb2local_0 +(0 8) routing glb_netwk_2 <X> glb2local_1 +(0 8) routing glb_netwk_3 <X> glb2local_1 +(0 8) routing glb_netwk_6 <X> glb2local_1 +(0 8) routing glb_netwk_7 <X> glb2local_1 +(0 9) routing glb_netwk_1 <X> glb2local_1 +(0 9) routing glb_netwk_3 <X> glb2local_1 +(0 9) routing glb_netwk_5 <X> glb2local_1 +(0 9) routing glb_netwk_7 <X> glb2local_1 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 +(1 11) routing glb_netwk_4 <X> glb2local_2 +(1 11) routing glb_netwk_5 <X> glb2local_2 +(1 11) routing glb_netwk_6 <X> glb2local_2 +(1 11) routing glb_netwk_7 <X> glb2local_2 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 +(1 13) routing glb_netwk_4 <X> glb2local_3 +(1 13) routing glb_netwk_5 <X> glb2local_3 +(1 13) routing glb_netwk_6 <X> glb2local_3 +(1 13) routing glb_netwk_7 <X> glb2local_3 +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_mult/lc_7/s_r +(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_mult/lc_7/s_r +(1 15) routing lc_trk_g0_4 <X> wire_mult/lc_7/s_r +(1 15) routing lc_trk_g1_5 <X> wire_mult/lc_7/s_r +(1 15) routing lc_trk_g2_4 <X> wire_mult/lc_7/s_r +(1 15) routing lc_trk_g3_5 <X> wire_mult/lc_7/s_r +(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 +(1 7) routing glb_netwk_4 <X> glb2local_0 +(1 7) routing glb_netwk_5 <X> glb2local_0 +(1 7) routing glb_netwk_6 <X> glb2local_0 +(1 7) routing glb_netwk_7 <X> glb2local_0 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 +(1 9) routing glb_netwk_4 <X> glb2local_1 +(1 9) routing glb_netwk_5 <X> glb2local_1 +(1 9) routing glb_netwk_6 <X> glb2local_1 +(1 9) routing glb_netwk_7 <X> glb2local_1 +(10 0) routing sp4_h_l_40 <X> sp4_h_r_1 +(10 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(10 0) routing sp4_v_t_45 <X> sp4_h_r_1 +(10 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(10 1) routing sp4_h_r_8 <X> sp4_v_b_1 +(10 1) routing sp4_v_t_40 <X> sp4_v_b_1 +(10 1) routing sp4_v_t_47 <X> sp4_v_b_1 +(10 10) routing sp4_h_r_4 <X> sp4_h_l_42 +(10 10) routing sp4_v_b_2 <X> sp4_h_l_42 +(10 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(10 11) routing sp4_h_l_39 <X> sp4_v_t_42 +(10 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(10 11) routing sp4_v_b_11 <X> sp4_v_t_42 +(10 11) routing sp4_v_b_4 <X> sp4_v_t_42 +(10 12) routing sp4_h_l_42 <X> sp4_h_r_10 +(10 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(10 12) routing sp4_v_t_40 <X> sp4_h_r_10 +(10 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(10 13) routing sp4_h_r_5 <X> sp4_v_b_10 +(10 13) routing sp4_v_t_39 <X> sp4_v_b_10 +(10 13) routing sp4_v_t_42 <X> sp4_v_b_10 +(10 14) routing sp4_h_r_2 <X> sp4_h_l_47 +(10 14) routing sp4_v_b_5 <X> sp4_h_l_47 +(10 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(10 15) routing sp4_h_l_40 <X> sp4_v_t_47 +(10 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(10 15) routing sp4_v_b_2 <X> sp4_v_t_47 +(10 15) routing sp4_v_b_7 <X> sp4_v_t_47 +(10 2) routing sp4_h_r_10 <X> sp4_h_l_36 +(10 2) routing sp4_v_b_8 <X> sp4_h_l_36 +(10 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(10 3) routing sp4_h_l_45 <X> sp4_v_t_36 +(10 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(10 3) routing sp4_v_b_10 <X> sp4_v_t_36 +(10 3) routing sp4_v_b_5 <X> sp4_v_t_36 +(10 4) routing sp4_h_l_45 <X> sp4_h_r_4 +(10 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(10 4) routing sp4_v_t_46 <X> sp4_h_r_4 +(10 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(10 5) routing sp4_h_r_11 <X> sp4_v_b_4 +(10 5) routing sp4_v_t_36 <X> sp4_v_b_4 +(10 5) routing sp4_v_t_45 <X> sp4_v_b_4 +(10 6) routing sp4_h_r_8 <X> sp4_h_l_41 +(10 6) routing sp4_v_b_11 <X> sp4_h_l_41 +(10 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(10 7) routing sp4_h_l_46 <X> sp4_v_t_41 +(10 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(10 7) routing sp4_v_b_1 <X> sp4_v_t_41 +(10 7) routing sp4_v_b_8 <X> sp4_v_t_41 +(10 8) routing sp4_h_l_41 <X> sp4_h_r_7 +(10 8) routing sp4_h_l_46 <X> sp4_h_r_7 +(10 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(10 8) routing sp4_v_t_39 <X> sp4_h_r_7 +(10 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(10 9) routing sp4_h_r_2 <X> sp4_v_b_7 +(10 9) routing sp4_v_t_41 <X> sp4_v_b_7 +(10 9) routing sp4_v_t_46 <X> sp4_v_b_7 +(11 0) routing sp4_h_l_45 <X> sp4_v_b_2 +(11 0) routing sp4_h_r_9 <X> sp4_v_b_2 +(11 0) routing sp4_v_t_43 <X> sp4_v_b_2 +(11 0) routing sp4_v_t_46 <X> sp4_v_b_2 +(11 1) routing sp4_v_b_2 <X> sp4_h_r_2 +(11 1) routing sp4_v_b_8 <X> sp4_h_r_2 +(11 10) routing sp4_h_l_38 <X> sp4_v_t_45 +(11 10) routing sp4_h_r_2 <X> sp4_v_t_45 +(11 10) routing sp4_v_b_0 <X> sp4_v_t_45 +(11 10) routing sp4_v_b_5 <X> sp4_v_t_45 +(11 11) routing sp4_h_r_0 <X> sp4_h_l_45 +(11 11) routing sp4_h_r_8 <X> sp4_h_l_45 +(11 11) routing sp4_v_t_39 <X> sp4_h_l_45 +(11 11) routing sp4_v_t_45 <X> sp4_h_l_45 +(11 12) routing sp4_h_l_40 <X> sp4_v_b_11 +(11 12) routing sp4_h_r_6 <X> sp4_v_b_11 +(11 12) routing sp4_v_t_38 <X> sp4_v_b_11 +(11 12) routing sp4_v_t_45 <X> sp4_v_b_11 +(11 13) routing sp4_h_l_46 <X> sp4_h_r_11 +(11 13) routing sp4_v_b_11 <X> sp4_h_r_11 +(11 13) routing sp4_v_b_5 <X> sp4_h_r_11 +(11 14) routing sp4_h_l_43 <X> sp4_v_t_46 +(11 14) routing sp4_h_r_5 <X> sp4_v_t_46 +(11 14) routing sp4_v_b_3 <X> sp4_v_t_46 +(11 14) routing sp4_v_b_8 <X> sp4_v_t_46 +(11 15) routing sp4_h_r_3 <X> sp4_h_l_46 +(11 15) routing sp4_v_t_40 <X> sp4_h_l_46 +(11 15) routing sp4_v_t_46 <X> sp4_h_l_46 +(11 2) routing sp4_h_l_44 <X> sp4_v_t_39 +(11 2) routing sp4_h_r_8 <X> sp4_v_t_39 +(11 2) routing sp4_v_b_11 <X> sp4_v_t_39 +(11 2) routing sp4_v_b_6 <X> sp4_v_t_39 +(11 3) routing sp4_h_r_2 <X> sp4_h_l_39 +(11 3) routing sp4_h_r_6 <X> sp4_h_l_39 +(11 3) routing sp4_v_t_39 <X> sp4_h_l_39 +(11 3) routing sp4_v_t_45 <X> sp4_h_l_39 +(11 4) routing sp4_h_l_46 <X> sp4_v_b_5 +(11 4) routing sp4_h_r_0 <X> sp4_v_b_5 +(11 4) routing sp4_v_t_39 <X> sp4_v_b_5 +(11 4) routing sp4_v_t_44 <X> sp4_v_b_5 +(11 5) routing sp4_h_l_40 <X> sp4_h_r_5 +(11 5) routing sp4_h_l_44 <X> sp4_h_r_5 +(11 5) routing sp4_v_b_11 <X> sp4_h_r_5 +(11 5) routing sp4_v_b_5 <X> sp4_h_r_5 +(11 6) routing sp4_h_l_37 <X> sp4_v_t_40 +(11 6) routing sp4_h_r_11 <X> sp4_v_t_40 +(11 6) routing sp4_v_b_2 <X> sp4_v_t_40 +(11 6) routing sp4_v_b_9 <X> sp4_v_t_40 +(11 7) routing sp4_v_t_40 <X> sp4_h_l_40 +(11 7) routing sp4_v_t_46 <X> sp4_h_l_40 +(11 8) routing sp4_h_l_39 <X> sp4_v_b_8 +(11 8) routing sp4_h_r_3 <X> sp4_v_b_8 +(11 8) routing sp4_v_t_37 <X> sp4_v_b_8 +(11 8) routing sp4_v_t_40 <X> sp4_v_b_8 +(11 9) routing sp4_h_l_37 <X> sp4_h_r_8 +(11 9) routing sp4_v_b_2 <X> sp4_h_r_8 +(11 9) routing sp4_v_b_8 <X> sp4_h_r_8 +(12 0) routing sp4_h_l_46 <X> sp4_h_r_2 +(12 0) routing sp4_v_b_2 <X> sp4_h_r_2 +(12 0) routing sp4_v_b_8 <X> sp4_h_r_2 +(12 0) routing sp4_v_t_39 <X> sp4_h_r_2 +(12 1) routing sp4_h_l_39 <X> sp4_v_b_2 +(12 1) routing sp4_h_l_45 <X> sp4_v_b_2 +(12 1) routing sp4_h_r_2 <X> sp4_v_b_2 +(12 1) routing sp4_v_t_46 <X> sp4_v_b_2 +(12 10) routing sp4_v_b_8 <X> sp4_h_l_45 +(12 10) routing sp4_v_t_39 <X> sp4_h_l_45 +(12 10) routing sp4_v_t_45 <X> sp4_h_l_45 +(12 11) routing sp4_h_l_45 <X> sp4_v_t_45 +(12 11) routing sp4_h_r_2 <X> sp4_v_t_45 +(12 11) routing sp4_h_r_8 <X> sp4_v_t_45 +(12 11) routing sp4_v_b_5 <X> sp4_v_t_45 +(12 12) routing sp4_v_b_11 <X> sp4_h_r_11 +(12 12) routing sp4_v_b_5 <X> sp4_h_r_11 +(12 12) routing sp4_v_t_46 <X> sp4_h_r_11 +(12 13) routing sp4_h_l_40 <X> sp4_v_b_11 +(12 13) routing sp4_h_l_46 <X> sp4_v_b_11 +(12 13) routing sp4_h_r_11 <X> sp4_v_b_11 +(12 13) routing sp4_v_t_45 <X> sp4_v_b_11 +(12 14) routing sp4_h_r_8 <X> sp4_h_l_46 +(12 14) routing sp4_v_b_11 <X> sp4_h_l_46 +(12 14) routing sp4_v_t_40 <X> sp4_h_l_46 +(12 14) routing sp4_v_t_46 <X> sp4_h_l_46 +(12 15) routing sp4_h_l_46 <X> sp4_v_t_46 +(12 15) routing sp4_h_r_11 <X> sp4_v_t_46 +(12 15) routing sp4_h_r_5 <X> sp4_v_t_46 +(12 15) routing sp4_v_b_8 <X> sp4_v_t_46 +(12 2) routing sp4_v_b_2 <X> sp4_h_l_39 +(12 2) routing sp4_v_t_39 <X> sp4_h_l_39 +(12 2) routing sp4_v_t_45 <X> sp4_h_l_39 +(12 3) routing sp4_h_l_39 <X> sp4_v_t_39 +(12 3) routing sp4_h_r_2 <X> sp4_v_t_39 +(12 3) routing sp4_h_r_8 <X> sp4_v_t_39 +(12 3) routing sp4_v_b_11 <X> sp4_v_t_39 +(12 4) routing sp4_v_b_11 <X> sp4_h_r_5 +(12 4) routing sp4_v_b_5 <X> sp4_h_r_5 +(12 4) routing sp4_v_t_40 <X> sp4_h_r_5 +(12 5) routing sp4_h_l_40 <X> sp4_v_b_5 +(12 5) routing sp4_h_l_46 <X> sp4_v_b_5 +(12 5) routing sp4_h_r_5 <X> sp4_v_b_5 +(12 5) routing sp4_v_t_39 <X> sp4_v_b_5 +(12 6) routing sp4_h_r_2 <X> sp4_h_l_40 +(12 6) routing sp4_v_b_5 <X> sp4_h_l_40 +(12 6) routing sp4_v_t_40 <X> sp4_h_l_40 +(12 6) routing sp4_v_t_46 <X> sp4_h_l_40 +(12 7) routing sp4_h_l_40 <X> sp4_v_t_40 +(12 7) routing sp4_h_r_11 <X> sp4_v_t_40 +(12 7) routing sp4_h_r_5 <X> sp4_v_t_40 +(12 7) routing sp4_v_b_2 <X> sp4_v_t_40 +(12 8) routing sp4_h_l_40 <X> sp4_h_r_8 +(12 8) routing sp4_v_b_2 <X> sp4_h_r_8 +(12 8) routing sp4_v_b_8 <X> sp4_h_r_8 +(12 8) routing sp4_v_t_45 <X> sp4_h_r_8 +(12 9) routing sp4_h_l_39 <X> sp4_v_b_8 +(12 9) routing sp4_h_l_45 <X> sp4_v_b_8 +(12 9) routing sp4_h_r_8 <X> sp4_v_b_8 +(12 9) routing sp4_v_t_40 <X> sp4_v_b_8 +(13 0) routing sp4_h_l_39 <X> sp4_v_b_2 +(13 0) routing sp4_h_l_45 <X> sp4_v_b_2 +(13 0) routing sp4_v_t_39 <X> sp4_v_b_2 +(13 0) routing sp4_v_t_43 <X> sp4_v_b_2 +(13 1) routing sp4_h_l_46 <X> sp4_h_r_2 +(13 1) routing sp4_v_b_8 <X> sp4_h_r_2 +(13 1) routing sp4_v_t_44 <X> sp4_h_r_2 +(13 10) routing sp4_h_r_2 <X> sp4_v_t_45 +(13 10) routing sp4_h_r_8 <X> sp4_v_t_45 +(13 10) routing sp4_v_b_0 <X> sp4_v_t_45 +(13 10) routing sp4_v_b_8 <X> sp4_v_t_45 +(13 11) routing sp4_h_r_0 <X> sp4_h_l_45 +(13 11) routing sp4_v_b_3 <X> sp4_h_l_45 +(13 11) routing sp4_v_t_39 <X> sp4_h_l_45 +(13 12) routing sp4_h_l_40 <X> sp4_v_b_11 +(13 12) routing sp4_h_l_46 <X> sp4_v_b_11 +(13 12) routing sp4_v_t_38 <X> sp4_v_b_11 +(13 12) routing sp4_v_t_46 <X> sp4_v_b_11 +(13 13) routing sp4_v_b_5 <X> sp4_h_r_11 +(13 13) routing sp4_v_t_43 <X> sp4_h_r_11 +(13 14) routing sp4_h_r_11 <X> sp4_v_t_46 +(13 14) routing sp4_h_r_5 <X> sp4_v_t_46 +(13 14) routing sp4_v_b_11 <X> sp4_v_t_46 +(13 14) routing sp4_v_b_3 <X> sp4_v_t_46 +(13 15) routing sp4_h_r_3 <X> sp4_h_l_46 +(13 15) routing sp4_h_r_8 <X> sp4_h_l_46 +(13 15) routing sp4_v_b_6 <X> sp4_h_l_46 +(13 15) routing sp4_v_t_40 <X> sp4_h_l_46 +(13 2) routing sp4_h_r_2 <X> sp4_v_t_39 +(13 2) routing sp4_h_r_8 <X> sp4_v_t_39 +(13 2) routing sp4_v_b_2 <X> sp4_v_t_39 +(13 2) routing sp4_v_b_6 <X> sp4_v_t_39 +(13 3) routing sp4_h_r_6 <X> sp4_h_l_39 +(13 3) routing sp4_v_b_9 <X> sp4_h_l_39 +(13 3) routing sp4_v_t_45 <X> sp4_h_l_39 +(13 4) routing sp4_h_l_40 <X> sp4_v_b_5 +(13 4) routing sp4_h_l_46 <X> sp4_v_b_5 +(13 4) routing sp4_v_t_40 <X> sp4_v_b_5 +(13 4) routing sp4_v_t_44 <X> sp4_v_b_5 +(13 5) routing sp4_h_l_44 <X> sp4_h_r_5 +(13 5) routing sp4_v_b_11 <X> sp4_h_r_5 +(13 5) routing sp4_v_t_37 <X> sp4_h_r_5 +(13 6) routing sp4_h_r_11 <X> sp4_v_t_40 +(13 6) routing sp4_h_r_5 <X> sp4_v_t_40 +(13 6) routing sp4_v_b_5 <X> sp4_v_t_40 +(13 6) routing sp4_v_b_9 <X> sp4_v_t_40 +(13 7) routing sp4_h_r_2 <X> sp4_h_l_40 +(13 7) routing sp4_v_b_0 <X> sp4_h_l_40 +(13 7) routing sp4_v_t_46 <X> sp4_h_l_40 +(13 8) routing sp4_h_l_39 <X> sp4_v_b_8 +(13 8) routing sp4_h_l_45 <X> sp4_v_b_8 +(13 8) routing sp4_v_t_37 <X> sp4_v_b_8 +(13 8) routing sp4_v_t_45 <X> sp4_v_b_8 +(13 9) routing sp4_h_l_37 <X> sp4_h_r_8 +(13 9) routing sp4_h_l_40 <X> sp4_h_r_8 +(13 9) routing sp4_v_b_2 <X> sp4_h_r_8 +(13 9) routing sp4_v_t_38 <X> sp4_h_r_8 +(14 0) routing sp12_h_r_0 <X> lc_trk_g0_0 +(14 0) routing sp4_h_l_5 <X> lc_trk_g0_0 +(14 0) routing sp4_h_r_8 <X> lc_trk_g0_0 +(14 0) routing sp4_v_b_0 <X> lc_trk_g0_0 +(14 0) routing sp4_v_b_8 <X> lc_trk_g0_0 +(14 1) routing sp12_h_r_0 <X> lc_trk_g0_0 +(14 1) routing sp12_h_r_16 <X> lc_trk_g0_0 +(14 1) routing sp4_h_l_5 <X> lc_trk_g0_0 +(14 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(14 1) routing sp4_r_v_b_35 <X> lc_trk_g0_0 +(14 1) routing sp4_v_b_8 <X> lc_trk_g0_0 +(14 10) routing bnl_op_4 <X> lc_trk_g2_4 +(14 10) routing rgt_op_4 <X> lc_trk_g2_4 +(14 10) routing sp12_v_t_3 <X> lc_trk_g2_4 +(14 10) routing sp4_h_l_25 <X> lc_trk_g2_4 +(14 10) routing sp4_h_l_33 <X> lc_trk_g2_4 +(14 10) routing sp4_v_b_28 <X> lc_trk_g2_4 +(14 10) routing sp4_v_t_25 <X> lc_trk_g2_4 +(14 11) routing bnl_op_4 <X> lc_trk_g2_4 +(14 11) routing sp12_v_b_20 <X> lc_trk_g2_4 +(14 11) routing sp12_v_t_3 <X> lc_trk_g2_4 +(14 11) routing sp4_h_l_17 <X> lc_trk_g2_4 +(14 11) routing sp4_h_l_33 <X> lc_trk_g2_4 +(14 11) routing sp4_r_v_b_36 <X> lc_trk_g2_4 +(14 11) routing sp4_v_t_25 <X> lc_trk_g2_4 +(14 11) routing tnl_op_4 <X> lc_trk_g2_4 +(14 12) routing bnl_op_0 <X> lc_trk_g3_0 +(14 12) routing rgt_op_0 <X> lc_trk_g3_0 +(14 12) routing sp12_v_b_0 <X> lc_trk_g3_0 +(14 12) routing sp4_h_r_32 <X> lc_trk_g3_0 +(14 12) routing sp4_h_r_40 <X> lc_trk_g3_0 +(14 12) routing sp4_v_b_32 <X> lc_trk_g3_0 +(14 12) routing sp4_v_t_13 <X> lc_trk_g3_0 +(14 13) routing bnl_op_0 <X> lc_trk_g3_0 +(14 13) routing sp12_v_b_0 <X> lc_trk_g3_0 +(14 13) routing sp12_v_b_16 <X> lc_trk_g3_0 +(14 13) routing sp4_h_l_13 <X> lc_trk_g3_0 +(14 13) routing sp4_h_r_40 <X> lc_trk_g3_0 +(14 13) routing sp4_r_v_b_40 <X> lc_trk_g3_0 +(14 13) routing sp4_v_b_32 <X> lc_trk_g3_0 +(14 13) routing tnl_op_0 <X> lc_trk_g3_0 +(14 14) routing bnl_op_4 <X> lc_trk_g3_4 +(14 14) routing rgt_op_4 <X> lc_trk_g3_4 +(14 14) routing sp12_v_t_3 <X> lc_trk_g3_4 +(14 14) routing sp4_h_l_25 <X> lc_trk_g3_4 +(14 14) routing sp4_h_l_33 <X> lc_trk_g3_4 +(14 14) routing sp4_v_b_28 <X> lc_trk_g3_4 +(14 14) routing sp4_v_t_25 <X> lc_trk_g3_4 +(14 15) routing bnl_op_4 <X> lc_trk_g3_4 +(14 15) routing sp12_v_b_20 <X> lc_trk_g3_4 +(14 15) routing sp12_v_t_3 <X> lc_trk_g3_4 +(14 15) routing sp4_h_l_17 <X> lc_trk_g3_4 +(14 15) routing sp4_h_l_33 <X> lc_trk_g3_4 +(14 15) routing sp4_r_v_b_44 <X> lc_trk_g3_4 +(14 15) routing sp4_v_t_25 <X> lc_trk_g3_4 +(14 15) routing tnl_op_4 <X> lc_trk_g3_4 +(14 2) routing bnr_op_4 <X> lc_trk_g0_4 +(14 2) routing lft_op_4 <X> lc_trk_g0_4 +(14 2) routing sp12_h_r_4 <X> lc_trk_g0_4 +(14 2) routing sp4_h_r_12 <X> lc_trk_g0_4 +(14 2) routing sp4_h_r_20 <X> lc_trk_g0_4 +(14 2) routing sp4_v_b_4 <X> lc_trk_g0_4 +(14 2) routing sp4_v_t_1 <X> lc_trk_g0_4 +(14 3) routing bnr_op_4 <X> lc_trk_g0_4 +(14 3) routing sp12_h_r_20 <X> lc_trk_g0_4 +(14 3) routing sp12_h_r_4 <X> lc_trk_g0_4 +(14 3) routing sp4_h_r_20 <X> lc_trk_g0_4 +(14 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(14 3) routing sp4_r_v_b_28 <X> lc_trk_g0_4 +(14 3) routing sp4_v_t_1 <X> lc_trk_g0_4 +(14 4) routing bnr_op_0 <X> lc_trk_g1_0 +(14 4) routing lft_op_0 <X> lc_trk_g1_0 +(14 4) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 4) routing sp4_h_l_5 <X> lc_trk_g1_0 +(14 4) routing sp4_h_r_8 <X> lc_trk_g1_0 +(14 4) routing sp4_v_b_0 <X> lc_trk_g1_0 +(14 4) routing sp4_v_b_8 <X> lc_trk_g1_0 +(14 5) routing bnr_op_0 <X> lc_trk_g1_0 +(14 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp12_h_r_16 <X> lc_trk_g1_0 +(14 5) routing sp4_h_l_5 <X> lc_trk_g1_0 +(14 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0 +(14 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(14 6) routing bnr_op_4 <X> lc_trk_g1_4 +(14 6) routing sp12_h_r_4 <X> lc_trk_g1_4 +(14 6) routing sp4_h_r_12 <X> lc_trk_g1_4 +(14 6) routing sp4_h_r_20 <X> lc_trk_g1_4 +(14 6) routing sp4_v_b_4 <X> lc_trk_g1_4 +(14 6) routing sp4_v_t_1 <X> lc_trk_g1_4 +(14 7) routing bnr_op_4 <X> lc_trk_g1_4 +(14 7) routing sp12_h_r_20 <X> lc_trk_g1_4 +(14 7) routing sp12_h_r_4 <X> lc_trk_g1_4 +(14 7) routing sp4_h_r_20 <X> lc_trk_g1_4 +(14 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4 +(14 7) routing sp4_v_t_1 <X> lc_trk_g1_4 +(14 8) routing bnl_op_0 <X> lc_trk_g2_0 +(14 8) routing rgt_op_0 <X> lc_trk_g2_0 +(14 8) routing sp12_v_b_0 <X> lc_trk_g2_0 +(14 8) routing sp4_h_r_32 <X> lc_trk_g2_0 +(14 8) routing sp4_h_r_40 <X> lc_trk_g2_0 +(14 8) routing sp4_v_b_32 <X> lc_trk_g2_0 +(14 8) routing sp4_v_t_13 <X> lc_trk_g2_0 +(14 9) routing bnl_op_0 <X> lc_trk_g2_0 +(14 9) routing sp12_v_b_0 <X> lc_trk_g2_0 +(14 9) routing sp12_v_b_16 <X> lc_trk_g2_0 +(14 9) routing sp4_h_l_13 <X> lc_trk_g2_0 +(14 9) routing sp4_h_r_40 <X> lc_trk_g2_0 +(14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0 +(14 9) routing sp4_v_b_32 <X> lc_trk_g2_0 +(14 9) routing tnl_op_0 <X> lc_trk_g2_0 +(15 0) routing lft_op_1 <X> lc_trk_g0_1 +(15 0) routing sp12_h_r_1 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_1 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(15 0) routing sp4_v_b_17 <X> lc_trk_g0_1 +(15 1) routing sp12_h_r_0 <X> lc_trk_g0_0 +(15 1) routing sp4_h_l_5 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_8 <X> lc_trk_g0_0 +(15 1) routing sp4_v_t_5 <X> lc_trk_g0_0 +(15 10) routing rgt_op_5 <X> lc_trk_g2_5 +(15 10) routing sp12_v_b_5 <X> lc_trk_g2_5 +(15 10) routing sp4_h_l_24 <X> lc_trk_g2_5 +(15 10) routing sp4_h_r_29 <X> lc_trk_g2_5 +(15 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(15 10) routing sp4_v_t_32 <X> lc_trk_g2_5 +(15 10) routing tnl_op_5 <X> lc_trk_g2_5 +(15 10) routing tnr_op_5 <X> lc_trk_g2_5 +(15 11) routing rgt_op_4 <X> lc_trk_g2_4 +(15 11) routing sp12_v_t_3 <X> lc_trk_g2_4 +(15 11) routing sp4_h_l_17 <X> lc_trk_g2_4 +(15 11) routing sp4_h_l_25 <X> lc_trk_g2_4 +(15 11) routing sp4_h_l_33 <X> lc_trk_g2_4 +(15 11) routing sp4_v_b_44 <X> lc_trk_g2_4 +(15 11) routing tnl_op_4 <X> lc_trk_g2_4 +(15 11) routing tnr_op_4 <X> lc_trk_g2_4 +(15 12) routing rgt_op_1 <X> lc_trk_g3_1 +(15 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(15 12) routing sp4_h_l_20 <X> lc_trk_g3_1 +(15 12) routing sp4_h_r_25 <X> lc_trk_g3_1 +(15 12) routing sp4_h_r_41 <X> lc_trk_g3_1 +(15 12) routing sp4_v_b_41 <X> lc_trk_g3_1 +(15 12) routing tnl_op_1 <X> lc_trk_g3_1 +(15 12) routing tnr_op_1 <X> lc_trk_g3_1 +(15 13) routing rgt_op_0 <X> lc_trk_g3_0 +(15 13) routing sp12_v_b_0 <X> lc_trk_g3_0 +(15 13) routing sp4_h_l_13 <X> lc_trk_g3_0 +(15 13) routing sp4_h_r_32 <X> lc_trk_g3_0 +(15 13) routing sp4_h_r_40 <X> lc_trk_g3_0 +(15 13) routing sp4_v_t_29 <X> lc_trk_g3_0 +(15 13) routing tnl_op_0 <X> lc_trk_g3_0 +(15 13) routing tnr_op_0 <X> lc_trk_g3_0 +(15 14) routing rgt_op_5 <X> lc_trk_g3_5 +(15 14) routing sp12_v_b_5 <X> lc_trk_g3_5 +(15 14) routing sp4_h_l_24 <X> lc_trk_g3_5 +(15 14) routing sp4_h_r_29 <X> lc_trk_g3_5 +(15 14) routing sp4_h_r_45 <X> lc_trk_g3_5 +(15 14) routing sp4_v_t_32 <X> lc_trk_g3_5 +(15 14) routing tnl_op_5 <X> lc_trk_g3_5 +(15 14) routing tnr_op_5 <X> lc_trk_g3_5 +(15 15) routing rgt_op_4 <X> lc_trk_g3_4 +(15 15) routing sp12_v_t_3 <X> lc_trk_g3_4 +(15 15) routing sp4_h_l_17 <X> lc_trk_g3_4 +(15 15) routing sp4_h_l_25 <X> lc_trk_g3_4 +(15 15) routing sp4_h_l_33 <X> lc_trk_g3_4 +(15 15) routing sp4_v_b_44 <X> lc_trk_g3_4 +(15 15) routing tnl_op_4 <X> lc_trk_g3_4 +(15 15) routing tnr_op_4 <X> lc_trk_g3_4 +(15 2) routing lft_op_5 <X> lc_trk_g0_5 +(15 2) routing sp12_h_r_5 <X> lc_trk_g0_5 +(15 2) routing sp4_h_l_0 <X> lc_trk_g0_5 +(15 2) routing sp4_h_r_21 <X> lc_trk_g0_5 +(15 2) routing sp4_h_r_5 <X> lc_trk_g0_5 +(15 2) routing sp4_v_t_8 <X> lc_trk_g0_5 +(15 3) routing lft_op_4 <X> lc_trk_g0_4 +(15 3) routing sp12_h_r_4 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_12 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_20 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(15 3) routing sp4_v_b_20 <X> lc_trk_g0_4 +(15 4) routing lft_op_1 <X> lc_trk_g1_1 +(15 4) routing sp12_h_r_1 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_1 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(15 4) routing sp4_v_b_17 <X> lc_trk_g1_1 +(15 5) routing lft_op_0 <X> lc_trk_g1_0 +(15 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(15 5) routing sp4_h_l_5 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_8 <X> lc_trk_g1_0 +(15 5) routing sp4_v_t_5 <X> lc_trk_g1_0 +(15 6) routing lft_op_5 <X> lc_trk_g1_5 +(15 6) routing sp12_h_r_5 <X> lc_trk_g1_5 +(15 6) routing sp4_h_l_0 <X> lc_trk_g1_5 +(15 6) routing sp4_h_r_21 <X> lc_trk_g1_5 +(15 6) routing sp4_h_r_5 <X> lc_trk_g1_5 +(15 6) routing sp4_v_t_8 <X> lc_trk_g1_5 +(15 7) routing sp12_h_r_4 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_12 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_20 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(15 7) routing sp4_v_b_20 <X> lc_trk_g1_4 +(15 8) routing rgt_op_1 <X> lc_trk_g2_1 +(15 8) routing sp12_v_b_1 <X> lc_trk_g2_1 +(15 8) routing sp4_h_l_20 <X> lc_trk_g2_1 +(15 8) routing sp4_h_r_25 <X> lc_trk_g2_1 +(15 8) routing sp4_h_r_41 <X> lc_trk_g2_1 +(15 8) routing sp4_v_b_41 <X> lc_trk_g2_1 +(15 8) routing tnl_op_1 <X> lc_trk_g2_1 +(15 8) routing tnr_op_1 <X> lc_trk_g2_1 +(15 9) routing rgt_op_0 <X> lc_trk_g2_0 +(15 9) routing sp12_v_b_0 <X> lc_trk_g2_0 +(15 9) routing sp4_h_l_13 <X> lc_trk_g2_0 +(15 9) routing sp4_h_r_32 <X> lc_trk_g2_0 +(15 9) routing sp4_h_r_40 <X> lc_trk_g2_0 +(15 9) routing sp4_v_t_29 <X> lc_trk_g2_0 +(15 9) routing tnl_op_0 <X> lc_trk_g2_0 +(15 9) routing tnr_op_0 <X> lc_trk_g2_0 +(16 0) routing sp12_h_l_14 <X> lc_trk_g0_1 +(16 0) routing sp12_h_r_9 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_1 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_1 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_17 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_9 <X> lc_trk_g0_1 +(16 1) routing sp12_h_r_16 <X> lc_trk_g0_0 +(16 1) routing sp12_h_r_8 <X> lc_trk_g0_0 +(16 1) routing sp4_h_l_5 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_8 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_0 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_8 <X> lc_trk_g0_0 +(16 1) routing sp4_v_t_5 <X> lc_trk_g0_0 +(16 10) routing sp12_v_b_21 <X> lc_trk_g2_5 +(16 10) routing sp12_v_t_10 <X> lc_trk_g2_5 +(16 10) routing sp4_h_l_24 <X> lc_trk_g2_5 +(16 10) routing sp4_h_r_29 <X> lc_trk_g2_5 +(16 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_37 <X> lc_trk_g2_5 +(16 10) routing sp4_v_t_16 <X> lc_trk_g2_5 +(16 10) routing sp4_v_t_32 <X> lc_trk_g2_5 +(16 11) routing sp12_v_b_12 <X> lc_trk_g2_4 +(16 11) routing sp12_v_b_20 <X> lc_trk_g2_4 +(16 11) routing sp4_h_l_17 <X> lc_trk_g2_4 +(16 11) routing sp4_h_l_25 <X> lc_trk_g2_4 +(16 11) routing sp4_h_l_33 <X> lc_trk_g2_4 +(16 11) routing sp4_v_b_28 <X> lc_trk_g2_4 +(16 11) routing sp4_v_b_44 <X> lc_trk_g2_4 +(16 11) routing sp4_v_t_25 <X> lc_trk_g2_4 +(16 12) routing sp12_v_b_9 <X> lc_trk_g3_1 +(16 12) routing sp12_v_t_14 <X> lc_trk_g3_1 +(16 12) routing sp4_h_l_20 <X> lc_trk_g3_1 +(16 12) routing sp4_h_r_25 <X> lc_trk_g3_1 +(16 12) routing sp4_h_r_41 <X> lc_trk_g3_1 +(16 12) routing sp4_v_b_41 <X> lc_trk_g3_1 +(16 12) routing sp4_v_t_12 <X> lc_trk_g3_1 +(16 12) routing sp4_v_t_20 <X> lc_trk_g3_1 +(16 13) routing sp12_v_b_16 <X> lc_trk_g3_0 +(16 13) routing sp12_v_t_7 <X> lc_trk_g3_0 +(16 13) routing sp4_h_l_13 <X> lc_trk_g3_0 +(16 13) routing sp4_h_r_32 <X> lc_trk_g3_0 +(16 13) routing sp4_h_r_40 <X> lc_trk_g3_0 +(16 13) routing sp4_v_b_32 <X> lc_trk_g3_0 +(16 13) routing sp4_v_t_13 <X> lc_trk_g3_0 +(16 13) routing sp4_v_t_29 <X> lc_trk_g3_0 +(16 14) routing sp12_v_b_21 <X> lc_trk_g3_5 +(16 14) routing sp12_v_t_10 <X> lc_trk_g3_5 +(16 14) routing sp4_h_l_24 <X> lc_trk_g3_5 +(16 14) routing sp4_h_r_29 <X> lc_trk_g3_5 +(16 14) routing sp4_h_r_45 <X> lc_trk_g3_5 +(16 14) routing sp4_v_b_37 <X> lc_trk_g3_5 +(16 14) routing sp4_v_t_16 <X> lc_trk_g3_5 +(16 14) routing sp4_v_t_32 <X> lc_trk_g3_5 +(16 15) routing sp12_v_b_12 <X> lc_trk_g3_4 +(16 15) routing sp12_v_b_20 <X> lc_trk_g3_4 +(16 15) routing sp4_h_l_17 <X> lc_trk_g3_4 +(16 15) routing sp4_h_l_25 <X> lc_trk_g3_4 +(16 15) routing sp4_h_l_33 <X> lc_trk_g3_4 +(16 15) routing sp4_v_b_28 <X> lc_trk_g3_4 +(16 15) routing sp4_v_b_44 <X> lc_trk_g3_4 +(16 15) routing sp4_v_t_25 <X> lc_trk_g3_4 +(16 2) routing sp12_h_l_10 <X> lc_trk_g0_5 +(16 2) routing sp12_h_r_21 <X> lc_trk_g0_5 +(16 2) routing sp4_h_l_0 <X> lc_trk_g0_5 +(16 2) routing sp4_h_r_21 <X> lc_trk_g0_5 +(16 2) routing sp4_h_r_5 <X> lc_trk_g0_5 +(16 2) routing sp4_v_b_5 <X> lc_trk_g0_5 +(16 2) routing sp4_v_t_0 <X> lc_trk_g0_5 +(16 2) routing sp4_v_t_8 <X> lc_trk_g0_5 +(16 3) routing sp12_h_l_11 <X> lc_trk_g0_4 +(16 3) routing sp12_h_r_20 <X> lc_trk_g0_4 +(16 3) routing sp4_h_r_12 <X> lc_trk_g0_4 +(16 3) routing sp4_h_r_20 <X> lc_trk_g0_4 +(16 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(16 3) routing sp4_v_b_20 <X> lc_trk_g0_4 +(16 3) routing sp4_v_b_4 <X> lc_trk_g0_4 +(16 3) routing sp4_v_t_1 <X> lc_trk_g0_4 +(16 4) routing sp12_h_l_14 <X> lc_trk_g1_1 +(16 4) routing sp12_h_r_9 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_1 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_1 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_17 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_9 <X> lc_trk_g1_1 +(16 5) routing sp12_h_r_16 <X> lc_trk_g1_0 +(16 5) routing sp12_h_r_8 <X> lc_trk_g1_0 +(16 5) routing sp4_h_l_5 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_8 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_0 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(16 5) routing sp4_v_t_5 <X> lc_trk_g1_0 +(16 6) routing sp12_h_l_10 <X> lc_trk_g1_5 +(16 6) routing sp12_h_r_21 <X> lc_trk_g1_5 +(16 6) routing sp4_h_l_0 <X> lc_trk_g1_5 +(16 6) routing sp4_h_r_21 <X> lc_trk_g1_5 +(16 6) routing sp4_h_r_5 <X> lc_trk_g1_5 +(16 6) routing sp4_v_b_5 <X> lc_trk_g1_5 +(16 6) routing sp4_v_t_0 <X> lc_trk_g1_5 +(16 6) routing sp4_v_t_8 <X> lc_trk_g1_5 +(16 7) routing sp12_h_l_11 <X> lc_trk_g1_4 +(16 7) routing sp12_h_r_20 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_12 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_20 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(16 7) routing sp4_v_b_20 <X> lc_trk_g1_4 +(16 7) routing sp4_v_b_4 <X> lc_trk_g1_4 +(16 7) routing sp4_v_t_1 <X> lc_trk_g1_4 +(16 8) routing sp12_v_b_9 <X> lc_trk_g2_1 +(16 8) routing sp12_v_t_14 <X> lc_trk_g2_1 +(16 8) routing sp4_h_l_20 <X> lc_trk_g2_1 +(16 8) routing sp4_h_r_25 <X> lc_trk_g2_1 +(16 8) routing sp4_h_r_41 <X> lc_trk_g2_1 +(16 8) routing sp4_v_b_41 <X> lc_trk_g2_1 +(16 8) routing sp4_v_t_12 <X> lc_trk_g2_1 +(16 8) routing sp4_v_t_20 <X> lc_trk_g2_1 +(16 9) routing sp12_v_b_16 <X> lc_trk_g2_0 +(16 9) routing sp12_v_t_7 <X> lc_trk_g2_0 +(16 9) routing sp4_h_l_13 <X> lc_trk_g2_0 +(16 9) routing sp4_h_r_32 <X> lc_trk_g2_0 +(16 9) routing sp4_h_r_40 <X> lc_trk_g2_0 +(16 9) routing sp4_v_b_32 <X> lc_trk_g2_0 +(16 9) routing sp4_v_t_13 <X> lc_trk_g2_0 +(16 9) routing sp4_v_t_29 <X> lc_trk_g2_0 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_t_5 lc_trk_g0_0 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_24 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_16 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_32 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_25 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_33 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_44 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_12 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_32 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_32 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_29 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_24 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_29 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_37 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_16 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_32 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_25 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_33 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_0 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_0 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_11 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_t_5 lc_trk_g1_0 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_0 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_0 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_11 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_20 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_41 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_12 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_29 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 +(18 0) routing bnr_op_1 <X> lc_trk_g0_1 +(18 0) routing lft_op_1 <X> lc_trk_g0_1 +(18 0) routing sp12_h_r_1 <X> lc_trk_g0_1 +(18 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(18 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(18 0) routing sp4_v_b_1 <X> lc_trk_g0_1 +(18 0) routing sp4_v_b_9 <X> lc_trk_g0_1 +(18 1) routing bnr_op_1 <X> lc_trk_g0_1 +(18 1) routing sp12_h_l_14 <X> lc_trk_g0_1 +(18 1) routing sp12_h_r_1 <X> lc_trk_g0_1 +(18 1) routing sp4_h_r_1 <X> lc_trk_g0_1 +(18 1) routing sp4_h_r_17 <X> lc_trk_g0_1 +(18 1) routing sp4_r_v_b_34 <X> lc_trk_g0_1 +(18 1) routing sp4_v_b_9 <X> lc_trk_g0_1 +(18 10) routing bnl_op_5 <X> lc_trk_g2_5 +(18 10) routing rgt_op_5 <X> lc_trk_g2_5 +(18 10) routing sp12_v_b_5 <X> lc_trk_g2_5 +(18 10) routing sp4_h_l_24 <X> lc_trk_g2_5 +(18 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(18 10) routing sp4_v_b_37 <X> lc_trk_g2_5 +(18 10) routing sp4_v_t_16 <X> lc_trk_g2_5 +(18 11) routing bnl_op_5 <X> lc_trk_g2_5 +(18 11) routing sp12_v_b_21 <X> lc_trk_g2_5 +(18 11) routing sp12_v_b_5 <X> lc_trk_g2_5 +(18 11) routing sp4_h_r_29 <X> lc_trk_g2_5 +(18 11) routing sp4_h_r_45 <X> lc_trk_g2_5 +(18 11) routing sp4_r_v_b_37 <X> lc_trk_g2_5 +(18 11) routing sp4_v_b_37 <X> lc_trk_g2_5 +(18 11) routing tnl_op_5 <X> lc_trk_g2_5 +(18 12) routing bnl_op_1 <X> lc_trk_g3_1 +(18 12) routing rgt_op_1 <X> lc_trk_g3_1 +(18 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(18 12) routing sp4_h_l_20 <X> lc_trk_g3_1 +(18 12) routing sp4_h_r_41 <X> lc_trk_g3_1 +(18 12) routing sp4_v_t_12 <X> lc_trk_g3_1 +(18 12) routing sp4_v_t_20 <X> lc_trk_g3_1 +(18 13) routing bnl_op_1 <X> lc_trk_g3_1 +(18 13) routing sp12_v_b_1 <X> lc_trk_g3_1 +(18 13) routing sp12_v_t_14 <X> lc_trk_g3_1 +(18 13) routing sp4_h_r_25 <X> lc_trk_g3_1 +(18 13) routing sp4_h_r_41 <X> lc_trk_g3_1 +(18 13) routing sp4_r_v_b_41 <X> lc_trk_g3_1 +(18 13) routing sp4_v_t_20 <X> lc_trk_g3_1 +(18 13) routing tnl_op_1 <X> lc_trk_g3_1 +(18 14) routing bnl_op_5 <X> lc_trk_g3_5 +(18 14) routing rgt_op_5 <X> lc_trk_g3_5 +(18 14) routing sp12_v_b_5 <X> lc_trk_g3_5 +(18 14) routing sp4_h_l_24 <X> lc_trk_g3_5 +(18 14) routing sp4_h_r_45 <X> lc_trk_g3_5 +(18 14) routing sp4_v_b_37 <X> lc_trk_g3_5 +(18 14) routing sp4_v_t_16 <X> lc_trk_g3_5 +(18 15) routing bnl_op_5 <X> lc_trk_g3_5 +(18 15) routing sp12_v_b_21 <X> lc_trk_g3_5 +(18 15) routing sp12_v_b_5 <X> lc_trk_g3_5 +(18 15) routing sp4_h_r_29 <X> lc_trk_g3_5 +(18 15) routing sp4_h_r_45 <X> lc_trk_g3_5 +(18 15) routing sp4_r_v_b_45 <X> lc_trk_g3_5 +(18 15) routing sp4_v_b_37 <X> lc_trk_g3_5 +(18 15) routing tnl_op_5 <X> lc_trk_g3_5 +(18 2) routing bnr_op_5 <X> lc_trk_g0_5 +(18 2) routing lft_op_5 <X> lc_trk_g0_5 +(18 2) routing sp12_h_r_5 <X> lc_trk_g0_5 +(18 2) routing sp4_h_l_0 <X> lc_trk_g0_5 +(18 2) routing sp4_h_r_21 <X> lc_trk_g0_5 +(18 2) routing sp4_v_b_5 <X> lc_trk_g0_5 +(18 2) routing sp4_v_t_0 <X> lc_trk_g0_5 +(18 3) routing bnr_op_5 <X> lc_trk_g0_5 +(18 3) routing sp12_h_r_21 <X> lc_trk_g0_5 +(18 3) routing sp12_h_r_5 <X> lc_trk_g0_5 +(18 3) routing sp4_h_r_21 <X> lc_trk_g0_5 +(18 3) routing sp4_h_r_5 <X> lc_trk_g0_5 +(18 3) routing sp4_r_v_b_29 <X> lc_trk_g0_5 +(18 3) routing sp4_v_t_0 <X> lc_trk_g0_5 +(18 4) routing bnr_op_1 <X> lc_trk_g1_1 +(18 4) routing lft_op_1 <X> lc_trk_g1_1 +(18 4) routing sp12_h_r_1 <X> lc_trk_g1_1 +(18 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(18 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(18 4) routing sp4_v_b_1 <X> lc_trk_g1_1 +(18 4) routing sp4_v_b_9 <X> lc_trk_g1_1 +(18 5) routing bnr_op_1 <X> lc_trk_g1_1 +(18 5) routing sp12_h_l_14 <X> lc_trk_g1_1 +(18 5) routing sp12_h_r_1 <X> lc_trk_g1_1 +(18 5) routing sp4_h_r_1 <X> lc_trk_g1_1 +(18 5) routing sp4_h_r_17 <X> lc_trk_g1_1 +(18 5) routing sp4_r_v_b_25 <X> lc_trk_g1_1 +(18 5) routing sp4_v_b_9 <X> lc_trk_g1_1 +(18 6) routing bnr_op_5 <X> lc_trk_g1_5 +(18 6) routing lft_op_5 <X> lc_trk_g1_5 +(18 6) routing sp12_h_r_5 <X> lc_trk_g1_5 +(18 6) routing sp4_h_l_0 <X> lc_trk_g1_5 +(18 6) routing sp4_h_r_21 <X> lc_trk_g1_5 +(18 6) routing sp4_v_b_5 <X> lc_trk_g1_5 +(18 6) routing sp4_v_t_0 <X> lc_trk_g1_5 +(18 7) routing bnr_op_5 <X> lc_trk_g1_5 +(18 7) routing sp12_h_r_21 <X> lc_trk_g1_5 +(18 7) routing sp12_h_r_5 <X> lc_trk_g1_5 +(18 7) routing sp4_h_r_21 <X> lc_trk_g1_5 +(18 7) routing sp4_h_r_5 <X> lc_trk_g1_5 +(18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5 +(18 7) routing sp4_v_t_0 <X> lc_trk_g1_5 +(18 8) routing bnl_op_1 <X> lc_trk_g2_1 +(18 8) routing rgt_op_1 <X> lc_trk_g2_1 +(18 8) routing sp12_v_b_1 <X> lc_trk_g2_1 +(18 8) routing sp4_h_l_20 <X> lc_trk_g2_1 +(18 8) routing sp4_h_r_41 <X> lc_trk_g2_1 +(18 8) routing sp4_v_t_12 <X> lc_trk_g2_1 +(18 8) routing sp4_v_t_20 <X> lc_trk_g2_1 +(18 9) routing bnl_op_1 <X> lc_trk_g2_1 +(18 9) routing sp12_v_b_1 <X> lc_trk_g2_1 +(18 9) routing sp12_v_t_14 <X> lc_trk_g2_1 +(18 9) routing sp4_h_r_25 <X> lc_trk_g2_1 +(18 9) routing sp4_h_r_41 <X> lc_trk_g2_1 +(18 9) routing sp4_r_v_b_33 <X> lc_trk_g2_1 +(18 9) routing sp4_v_t_20 <X> lc_trk_g2_1 +(18 9) routing tnl_op_1 <X> lc_trk_g2_1 +(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_t_0 sp4_v_t_0 +(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_t_1 +(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_t_20 sp4_v_t_10 +(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_b_22 +(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_r_2 sp4_h_l_0 +(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_r_12 +(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_r_15 +(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_r_4 sp4_h_l_3 +(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_t_4 sp4_v_b_15 +(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14 +(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_t_8 sp4_v_b_17 +(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_t_5 +(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_b_19 +(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_b_18 +(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_t_16 sp4_v_t_8 +(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_b_20 +(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_l_5 +(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_r_21 +(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_l_11 +(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_r_23 +(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_l_11 sp4_h_l_7 +(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_r_14 sp4_h_l_6 +(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_r_20 +(21 0) routing bnr_op_3 <X> lc_trk_g0_3 +(21 0) routing sp12_h_l_0 <X> lc_trk_g0_3 +(21 0) routing sp4_h_l_6 <X> lc_trk_g0_3 +(21 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(21 0) routing sp4_v_b_11 <X> lc_trk_g0_3 +(21 0) routing sp4_v_b_3 <X> lc_trk_g0_3 +(21 1) routing bnr_op_3 <X> lc_trk_g0_3 +(21 1) routing sp12_h_l_0 <X> lc_trk_g0_3 +(21 1) routing sp12_h_r_19 <X> lc_trk_g0_3 +(21 1) routing sp4_h_l_6 <X> lc_trk_g0_3 +(21 1) routing sp4_h_r_3 <X> lc_trk_g0_3 +(21 1) routing sp4_r_v_b_32 <X> lc_trk_g0_3 +(21 1) routing sp4_v_b_11 <X> lc_trk_g0_3 +(21 10) routing bnl_op_7 <X> lc_trk_g2_7 +(21 10) routing rgt_op_7 <X> lc_trk_g2_7 +(21 10) routing sp12_v_t_4 <X> lc_trk_g2_7 +(21 10) routing sp4_h_r_39 <X> lc_trk_g2_7 +(21 10) routing sp4_h_r_47 <X> lc_trk_g2_7 +(21 10) routing sp4_v_b_31 <X> lc_trk_g2_7 +(21 10) routing sp4_v_b_39 <X> lc_trk_g2_7 +(21 11) routing bnl_op_7 <X> lc_trk_g2_7 +(21 11) routing sp12_v_t_20 <X> lc_trk_g2_7 +(21 11) routing sp12_v_t_4 <X> lc_trk_g2_7 +(21 11) routing sp4_h_l_18 <X> lc_trk_g2_7 +(21 11) routing sp4_h_r_47 <X> lc_trk_g2_7 +(21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7 +(21 11) routing sp4_v_b_39 <X> lc_trk_g2_7 +(21 11) routing tnl_op_7 <X> lc_trk_g2_7 +(21 12) routing bnl_op_3 <X> lc_trk_g3_3 +(21 12) routing rgt_op_3 <X> lc_trk_g3_3 +(21 12) routing sp12_v_t_0 <X> lc_trk_g3_3 +(21 12) routing sp4_h_l_30 <X> lc_trk_g3_3 +(21 12) routing sp4_h_r_35 <X> lc_trk_g3_3 +(21 12) routing sp4_v_b_27 <X> lc_trk_g3_3 +(21 12) routing sp4_v_b_35 <X> lc_trk_g3_3 +(21 13) routing bnl_op_3 <X> lc_trk_g3_3 +(21 13) routing sp12_v_t_0 <X> lc_trk_g3_3 +(21 13) routing sp12_v_t_16 <X> lc_trk_g3_3 +(21 13) routing sp4_h_l_30 <X> lc_trk_g3_3 +(21 13) routing sp4_h_r_27 <X> lc_trk_g3_3 +(21 13) routing sp4_r_v_b_43 <X> lc_trk_g3_3 +(21 13) routing sp4_v_b_35 <X> lc_trk_g3_3 +(21 13) routing tnl_op_3 <X> lc_trk_g3_3 +(21 14) routing bnl_op_7 <X> lc_trk_g3_7 +(21 14) routing rgt_op_7 <X> lc_trk_g3_7 +(21 14) routing sp12_v_t_4 <X> lc_trk_g3_7 +(21 14) routing sp4_h_r_39 <X> lc_trk_g3_7 +(21 14) routing sp4_h_r_47 <X> lc_trk_g3_7 +(21 14) routing sp4_v_b_31 <X> lc_trk_g3_7 +(21 14) routing sp4_v_b_39 <X> lc_trk_g3_7 +(21 15) routing bnl_op_7 <X> lc_trk_g3_7 +(21 15) routing sp12_v_t_20 <X> lc_trk_g3_7 +(21 15) routing sp12_v_t_4 <X> lc_trk_g3_7 +(21 15) routing sp4_h_l_18 <X> lc_trk_g3_7 +(21 15) routing sp4_h_r_47 <X> lc_trk_g3_7 +(21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7 +(21 15) routing sp4_v_b_39 <X> lc_trk_g3_7 +(21 15) routing tnl_op_7 <X> lc_trk_g3_7 +(21 2) routing lft_op_7 <X> lc_trk_g0_7 +(21 2) routing sp12_h_r_7 <X> lc_trk_g0_7 +(21 2) routing sp4_h_r_15 <X> lc_trk_g0_7 +(21 2) routing sp4_h_r_23 <X> lc_trk_g0_7 +(21 2) routing sp4_v_b_15 <X> lc_trk_g0_7 +(21 2) routing sp4_v_b_7 <X> lc_trk_g0_7 +(21 3) routing sp12_h_l_20 <X> lc_trk_g0_7 +(21 3) routing sp12_h_r_7 <X> lc_trk_g0_7 +(21 3) routing sp4_h_r_23 <X> lc_trk_g0_7 +(21 3) routing sp4_h_r_7 <X> lc_trk_g0_7 +(21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7 +(21 3) routing sp4_v_b_15 <X> lc_trk_g0_7 +(21 4) routing lft_op_3 <X> lc_trk_g1_3 +(21 4) routing sp12_h_l_0 <X> lc_trk_g1_3 +(21 4) routing sp4_h_l_6 <X> lc_trk_g1_3 +(21 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(21 4) routing sp4_v_b_11 <X> lc_trk_g1_3 +(21 4) routing sp4_v_b_3 <X> lc_trk_g1_3 +(21 5) routing sp12_h_l_0 <X> lc_trk_g1_3 +(21 5) routing sp12_h_r_19 <X> lc_trk_g1_3 +(21 5) routing sp4_h_l_6 <X> lc_trk_g1_3 +(21 5) routing sp4_h_r_3 <X> lc_trk_g1_3 +(21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3 +(21 5) routing sp4_v_b_11 <X> lc_trk_g1_3 +(21 6) routing bnr_op_7 <X> lc_trk_g1_7 +(21 6) routing lft_op_7 <X> lc_trk_g1_7 +(21 6) routing sp12_h_r_7 <X> lc_trk_g1_7 +(21 6) routing sp4_h_r_15 <X> lc_trk_g1_7 +(21 6) routing sp4_h_r_23 <X> lc_trk_g1_7 +(21 6) routing sp4_v_b_15 <X> lc_trk_g1_7 +(21 6) routing sp4_v_b_7 <X> lc_trk_g1_7 +(21 7) routing bnr_op_7 <X> lc_trk_g1_7 +(21 7) routing sp12_h_l_20 <X> lc_trk_g1_7 +(21 7) routing sp12_h_r_7 <X> lc_trk_g1_7 +(21 7) routing sp4_h_r_23 <X> lc_trk_g1_7 +(21 7) routing sp4_h_r_7 <X> lc_trk_g1_7 +(21 7) routing sp4_r_v_b_31 <X> lc_trk_g1_7 +(21 7) routing sp4_v_b_15 <X> lc_trk_g1_7 +(21 8) routing bnl_op_3 <X> lc_trk_g2_3 +(21 8) routing sp12_v_t_0 <X> lc_trk_g2_3 +(21 8) routing sp4_h_l_30 <X> lc_trk_g2_3 +(21 8) routing sp4_h_r_35 <X> lc_trk_g2_3 +(21 8) routing sp4_v_b_27 <X> lc_trk_g2_3 +(21 8) routing sp4_v_b_35 <X> lc_trk_g2_3 +(21 9) routing bnl_op_3 <X> lc_trk_g2_3 +(21 9) routing sp12_v_t_0 <X> lc_trk_g2_3 +(21 9) routing sp12_v_t_16 <X> lc_trk_g2_3 +(21 9) routing sp4_h_l_30 <X> lc_trk_g2_3 +(21 9) routing sp4_h_r_27 <X> lc_trk_g2_3 +(21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3 +(21 9) routing sp4_v_b_35 <X> lc_trk_g2_3 +(21 9) routing tnl_op_3 <X> lc_trk_g2_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_8 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_l_6 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_20 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_31 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_22 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_13 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_19 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_27 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_0 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_16 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_8 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_30 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_35 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_1 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_17 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_9 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_26 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_20 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_39 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_31 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_39 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_13 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_27 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_15 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_23 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_15 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_10 lc_trk_g0_7 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_8 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_l_6 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_17 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_18 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_15 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_15 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_23 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_15 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_10 lc_trk_g1_7 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_16 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_30 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_27 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_43 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_1 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_17 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_9 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 +(23 0) routing sp12_h_l_8 <X> lc_trk_g0_3 +(23 0) routing sp12_h_r_19 <X> lc_trk_g0_3 +(23 0) routing sp4_h_l_6 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_3 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_11 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_19 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_3 <X> lc_trk_g0_3 +(23 1) routing sp12_h_l_17 <X> lc_trk_g0_2 +(23 1) routing sp12_h_l_9 <X> lc_trk_g0_2 +(23 1) routing sp4_h_l_7 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_10 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_10 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_18 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_2 <X> lc_trk_g0_2 +(23 10) routing sp12_v_t_12 <X> lc_trk_g2_7 +(23 10) routing sp12_v_t_20 <X> lc_trk_g2_7 +(23 10) routing sp4_h_l_18 <X> lc_trk_g2_7 +(23 10) routing sp4_h_r_39 <X> lc_trk_g2_7 +(23 10) routing sp4_h_r_47 <X> lc_trk_g2_7 +(23 10) routing sp4_v_b_31 <X> lc_trk_g2_7 +(23 10) routing sp4_v_b_39 <X> lc_trk_g2_7 +(23 10) routing sp4_v_t_34 <X> lc_trk_g2_7 +(23 11) routing sp12_v_b_22 <X> lc_trk_g2_6 +(23 11) routing sp12_v_t_13 <X> lc_trk_g2_6 +(23 11) routing sp4_h_l_27 <X> lc_trk_g2_6 +(23 11) routing sp4_h_r_30 <X> lc_trk_g2_6 +(23 11) routing sp4_h_r_46 <X> lc_trk_g2_6 +(23 11) routing sp4_v_b_46 <X> lc_trk_g2_6 +(23 11) routing sp4_v_t_19 <X> lc_trk_g2_6 +(23 11) routing sp4_v_t_27 <X> lc_trk_g2_6 +(23 12) routing sp12_v_t_16 <X> lc_trk_g3_3 +(23 12) routing sp12_v_t_8 <X> lc_trk_g3_3 +(23 12) routing sp4_h_l_30 <X> lc_trk_g3_3 +(23 12) routing sp4_h_r_27 <X> lc_trk_g3_3 +(23 12) routing sp4_h_r_35 <X> lc_trk_g3_3 +(23 12) routing sp4_v_b_27 <X> lc_trk_g3_3 +(23 12) routing sp4_v_b_35 <X> lc_trk_g3_3 +(23 12) routing sp4_v_b_43 <X> lc_trk_g3_3 +(23 13) routing sp12_v_t_17 <X> lc_trk_g3_2 +(23 13) routing sp12_v_t_9 <X> lc_trk_g3_2 +(23 13) routing sp4_h_l_15 <X> lc_trk_g3_2 +(23 13) routing sp4_h_r_34 <X> lc_trk_g3_2 +(23 13) routing sp4_h_r_42 <X> lc_trk_g3_2 +(23 13) routing sp4_v_b_26 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_23 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_31 <X> lc_trk_g3_2 +(23 14) routing sp12_v_t_12 <X> lc_trk_g3_7 +(23 14) routing sp12_v_t_20 <X> lc_trk_g3_7 +(23 14) routing sp4_h_l_18 <X> lc_trk_g3_7 +(23 14) routing sp4_h_r_39 <X> lc_trk_g3_7 +(23 14) routing sp4_h_r_47 <X> lc_trk_g3_7 +(23 14) routing sp4_v_b_31 <X> lc_trk_g3_7 +(23 14) routing sp4_v_b_39 <X> lc_trk_g3_7 +(23 14) routing sp4_v_t_34 <X> lc_trk_g3_7 +(23 15) routing sp12_v_b_22 <X> lc_trk_g3_6 +(23 15) routing sp12_v_t_13 <X> lc_trk_g3_6 +(23 15) routing sp4_h_l_27 <X> lc_trk_g3_6 +(23 15) routing sp4_h_r_30 <X> lc_trk_g3_6 +(23 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(23 15) routing sp4_v_b_46 <X> lc_trk_g3_6 +(23 15) routing sp4_v_t_19 <X> lc_trk_g3_6 +(23 15) routing sp4_v_t_27 <X> lc_trk_g3_6 +(23 2) routing sp12_h_l_20 <X> lc_trk_g0_7 +(23 2) routing sp12_h_r_15 <X> lc_trk_g0_7 +(23 2) routing sp4_h_r_15 <X> lc_trk_g0_7 +(23 2) routing sp4_h_r_23 <X> lc_trk_g0_7 +(23 2) routing sp4_h_r_7 <X> lc_trk_g0_7 +(23 2) routing sp4_v_b_15 <X> lc_trk_g0_7 +(23 2) routing sp4_v_b_7 <X> lc_trk_g0_7 +(23 2) routing sp4_v_t_10 <X> lc_trk_g0_7 +(23 3) routing sp12_h_r_14 <X> lc_trk_g0_6 +(23 3) routing sp12_h_r_22 <X> lc_trk_g0_6 +(23 3) routing sp4_h_l_11 <X> lc_trk_g0_6 +(23 3) routing sp4_h_l_3 <X> lc_trk_g0_6 +(23 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(23 3) routing sp4_v_b_14 <X> lc_trk_g0_6 +(23 3) routing sp4_v_b_22 <X> lc_trk_g0_6 +(23 3) routing sp4_v_b_6 <X> lc_trk_g0_6 +(23 4) routing sp12_h_l_8 <X> lc_trk_g1_3 +(23 4) routing sp12_h_r_19 <X> lc_trk_g1_3 +(23 4) routing sp4_h_l_6 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_3 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_11 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_19 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_3 <X> lc_trk_g1_3 +(23 5) routing sp12_h_l_17 <X> lc_trk_g1_2 +(23 5) routing sp12_h_l_9 <X> lc_trk_g1_2 +(23 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_10 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_18 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_2 <X> lc_trk_g1_2 +(23 6) routing sp12_h_l_20 <X> lc_trk_g1_7 +(23 6) routing sp12_h_r_15 <X> lc_trk_g1_7 +(23 6) routing sp4_h_r_15 <X> lc_trk_g1_7 +(23 6) routing sp4_h_r_23 <X> lc_trk_g1_7 +(23 6) routing sp4_h_r_7 <X> lc_trk_g1_7 +(23 6) routing sp4_v_b_15 <X> lc_trk_g1_7 +(23 6) routing sp4_v_b_7 <X> lc_trk_g1_7 +(23 6) routing sp4_v_t_10 <X> lc_trk_g1_7 +(23 7) routing sp12_h_r_14 <X> lc_trk_g1_6 +(23 7) routing sp12_h_r_22 <X> lc_trk_g1_6 +(23 7) routing sp4_h_l_11 <X> lc_trk_g1_6 +(23 7) routing sp4_h_l_3 <X> lc_trk_g1_6 +(23 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_14 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_22 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_6 <X> lc_trk_g1_6 +(23 8) routing sp12_v_t_16 <X> lc_trk_g2_3 +(23 8) routing sp12_v_t_8 <X> lc_trk_g2_3 +(23 8) routing sp4_h_l_30 <X> lc_trk_g2_3 +(23 8) routing sp4_h_r_27 <X> lc_trk_g2_3 +(23 8) routing sp4_h_r_35 <X> lc_trk_g2_3 +(23 8) routing sp4_v_b_27 <X> lc_trk_g2_3 +(23 8) routing sp4_v_b_35 <X> lc_trk_g2_3 +(23 8) routing sp4_v_b_43 <X> lc_trk_g2_3 +(23 9) routing sp12_v_t_17 <X> lc_trk_g2_2 +(23 9) routing sp12_v_t_9 <X> lc_trk_g2_2 +(23 9) routing sp4_h_l_15 <X> lc_trk_g2_2 +(23 9) routing sp4_h_r_34 <X> lc_trk_g2_2 +(23 9) routing sp4_h_r_42 <X> lc_trk_g2_2 +(23 9) routing sp4_v_b_26 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_23 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_31 <X> lc_trk_g2_2 +(24 0) routing sp12_h_l_0 <X> lc_trk_g0_3 +(24 0) routing sp4_h_l_6 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_3 <X> lc_trk_g0_3 +(24 0) routing sp4_v_b_19 <X> lc_trk_g0_3 +(24 1) routing lft_op_2 <X> lc_trk_g0_2 +(24 1) routing sp12_h_r_2 <X> lc_trk_g0_2 +(24 1) routing sp4_h_l_7 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_10 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(24 1) routing sp4_v_b_18 <X> lc_trk_g0_2 +(24 10) routing rgt_op_7 <X> lc_trk_g2_7 +(24 10) routing sp12_v_t_4 <X> lc_trk_g2_7 +(24 10) routing sp4_h_l_18 <X> lc_trk_g2_7 +(24 10) routing sp4_h_r_39 <X> lc_trk_g2_7 +(24 10) routing sp4_h_r_47 <X> lc_trk_g2_7 +(24 10) routing sp4_v_t_34 <X> lc_trk_g2_7 +(24 10) routing tnl_op_7 <X> lc_trk_g2_7 +(24 10) routing tnr_op_7 <X> lc_trk_g2_7 +(24 11) routing rgt_op_6 <X> lc_trk_g2_6 +(24 11) routing sp12_v_b_6 <X> lc_trk_g2_6 +(24 11) routing sp4_h_l_27 <X> lc_trk_g2_6 +(24 11) routing sp4_h_r_30 <X> lc_trk_g2_6 +(24 11) routing sp4_h_r_46 <X> lc_trk_g2_6 +(24 11) routing sp4_v_b_46 <X> lc_trk_g2_6 +(24 11) routing tnl_op_6 <X> lc_trk_g2_6 +(24 11) routing tnr_op_6 <X> lc_trk_g2_6 +(24 12) routing rgt_op_3 <X> lc_trk_g3_3 +(24 12) routing sp12_v_t_0 <X> lc_trk_g3_3 +(24 12) routing sp4_h_l_30 <X> lc_trk_g3_3 +(24 12) routing sp4_h_r_27 <X> lc_trk_g3_3 +(24 12) routing sp4_h_r_35 <X> lc_trk_g3_3 +(24 12) routing sp4_v_b_43 <X> lc_trk_g3_3 +(24 12) routing tnl_op_3 <X> lc_trk_g3_3 +(24 12) routing tnr_op_3 <X> lc_trk_g3_3 +(24 13) routing rgt_op_2 <X> lc_trk_g3_2 +(24 13) routing sp12_v_t_1 <X> lc_trk_g3_2 +(24 13) routing sp4_h_l_15 <X> lc_trk_g3_2 +(24 13) routing sp4_h_r_34 <X> lc_trk_g3_2 +(24 13) routing sp4_h_r_42 <X> lc_trk_g3_2 +(24 13) routing sp4_v_t_31 <X> lc_trk_g3_2 +(24 13) routing tnl_op_2 <X> lc_trk_g3_2 +(24 13) routing tnr_op_2 <X> lc_trk_g3_2 +(24 14) routing rgt_op_7 <X> lc_trk_g3_7 +(24 14) routing sp12_v_t_4 <X> lc_trk_g3_7 +(24 14) routing sp4_h_l_18 <X> lc_trk_g3_7 +(24 14) routing sp4_h_r_39 <X> lc_trk_g3_7 +(24 14) routing sp4_h_r_47 <X> lc_trk_g3_7 +(24 14) routing sp4_v_t_34 <X> lc_trk_g3_7 +(24 14) routing tnl_op_7 <X> lc_trk_g3_7 +(24 14) routing tnr_op_7 <X> lc_trk_g3_7 +(24 15) routing rgt_op_6 <X> lc_trk_g3_6 +(24 15) routing sp12_v_b_6 <X> lc_trk_g3_6 +(24 15) routing sp4_h_l_27 <X> lc_trk_g3_6 +(24 15) routing sp4_h_r_30 <X> lc_trk_g3_6 +(24 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(24 15) routing sp4_v_b_46 <X> lc_trk_g3_6 +(24 15) routing tnl_op_6 <X> lc_trk_g3_6 +(24 15) routing tnr_op_6 <X> lc_trk_g3_6 +(24 2) routing lft_op_7 <X> lc_trk_g0_7 +(24 2) routing sp12_h_r_7 <X> lc_trk_g0_7 +(24 2) routing sp4_h_r_15 <X> lc_trk_g0_7 +(24 2) routing sp4_h_r_23 <X> lc_trk_g0_7 +(24 2) routing sp4_h_r_7 <X> lc_trk_g0_7 +(24 2) routing sp4_v_t_10 <X> lc_trk_g0_7 +(24 3) routing lft_op_6 <X> lc_trk_g0_6 +(24 3) routing sp12_h_l_5 <X> lc_trk_g0_6 +(24 3) routing sp4_h_l_11 <X> lc_trk_g0_6 +(24 3) routing sp4_h_l_3 <X> lc_trk_g0_6 +(24 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(24 3) routing sp4_v_b_22 <X> lc_trk_g0_6 +(24 4) routing lft_op_3 <X> lc_trk_g1_3 +(24 4) routing sp12_h_l_0 <X> lc_trk_g1_3 +(24 4) routing sp4_h_l_6 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_3 <X> lc_trk_g1_3 +(24 4) routing sp4_v_b_19 <X> lc_trk_g1_3 +(24 5) routing lft_op_2 <X> lc_trk_g1_2 +(24 5) routing sp12_h_r_2 <X> lc_trk_g1_2 +(24 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(24 5) routing sp4_v_b_18 <X> lc_trk_g1_2 +(24 6) routing lft_op_7 <X> lc_trk_g1_7 +(24 6) routing sp12_h_r_7 <X> lc_trk_g1_7 +(24 6) routing sp4_h_r_15 <X> lc_trk_g1_7 +(24 6) routing sp4_h_r_23 <X> lc_trk_g1_7 +(24 6) routing sp4_h_r_7 <X> lc_trk_g1_7 +(24 6) routing sp4_v_t_10 <X> lc_trk_g1_7 +(24 7) routing lft_op_6 <X> lc_trk_g1_6 +(24 7) routing sp12_h_l_5 <X> lc_trk_g1_6 +(24 7) routing sp4_h_l_11 <X> lc_trk_g1_6 +(24 7) routing sp4_h_l_3 <X> lc_trk_g1_6 +(24 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(24 7) routing sp4_v_b_22 <X> lc_trk_g1_6 +(24 8) routing sp12_v_t_0 <X> lc_trk_g2_3 +(24 8) routing sp4_h_l_30 <X> lc_trk_g2_3 +(24 8) routing sp4_h_r_27 <X> lc_trk_g2_3 +(24 8) routing sp4_h_r_35 <X> lc_trk_g2_3 +(24 8) routing sp4_v_b_43 <X> lc_trk_g2_3 +(24 8) routing tnl_op_3 <X> lc_trk_g2_3 +(24 8) routing tnr_op_3 <X> lc_trk_g2_3 +(24 9) routing rgt_op_2 <X> lc_trk_g2_2 +(24 9) routing sp12_v_t_1 <X> lc_trk_g2_2 +(24 9) routing sp4_h_l_15 <X> lc_trk_g2_2 +(24 9) routing sp4_h_r_34 <X> lc_trk_g2_2 +(24 9) routing sp4_h_r_42 <X> lc_trk_g2_2 +(24 9) routing sp4_v_t_31 <X> lc_trk_g2_2 +(24 9) routing tnl_op_2 <X> lc_trk_g2_2 +(24 9) routing tnr_op_2 <X> lc_trk_g2_2 +(25 0) routing bnr_op_2 <X> lc_trk_g0_2 +(25 0) routing lft_op_2 <X> lc_trk_g0_2 +(25 0) routing sp12_h_r_2 <X> lc_trk_g0_2 +(25 0) routing sp4_h_l_7 <X> lc_trk_g0_2 +(25 0) routing sp4_h_r_10 <X> lc_trk_g0_2 +(25 0) routing sp4_v_b_10 <X> lc_trk_g0_2 +(25 0) routing sp4_v_b_2 <X> lc_trk_g0_2 +(25 1) routing bnr_op_2 <X> lc_trk_g0_2 +(25 1) routing sp12_h_l_17 <X> lc_trk_g0_2 +(25 1) routing sp12_h_r_2 <X> lc_trk_g0_2 +(25 1) routing sp4_h_l_7 <X> lc_trk_g0_2 +(25 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(25 1) routing sp4_r_v_b_33 <X> lc_trk_g0_2 +(25 1) routing sp4_v_b_10 <X> lc_trk_g0_2 +(25 10) routing bnl_op_6 <X> lc_trk_g2_6 +(25 10) routing rgt_op_6 <X> lc_trk_g2_6 +(25 10) routing sp12_v_b_6 <X> lc_trk_g2_6 +(25 10) routing sp4_h_l_27 <X> lc_trk_g2_6 +(25 10) routing sp4_h_r_46 <X> lc_trk_g2_6 +(25 10) routing sp4_v_t_19 <X> lc_trk_g2_6 +(25 10) routing sp4_v_t_27 <X> lc_trk_g2_6 +(25 11) routing bnl_op_6 <X> lc_trk_g2_6 +(25 11) routing sp12_v_b_22 <X> lc_trk_g2_6 +(25 11) routing sp12_v_b_6 <X> lc_trk_g2_6 +(25 11) routing sp4_h_r_30 <X> lc_trk_g2_6 +(25 11) routing sp4_h_r_46 <X> lc_trk_g2_6 +(25 11) routing sp4_r_v_b_38 <X> lc_trk_g2_6 +(25 11) routing sp4_v_t_27 <X> lc_trk_g2_6 +(25 11) routing tnl_op_6 <X> lc_trk_g2_6 +(25 12) routing bnl_op_2 <X> lc_trk_g3_2 +(25 12) routing rgt_op_2 <X> lc_trk_g3_2 +(25 12) routing sp12_v_t_1 <X> lc_trk_g3_2 +(25 12) routing sp4_h_r_34 <X> lc_trk_g3_2 +(25 12) routing sp4_h_r_42 <X> lc_trk_g3_2 +(25 12) routing sp4_v_b_26 <X> lc_trk_g3_2 +(25 12) routing sp4_v_t_23 <X> lc_trk_g3_2 +(25 13) routing bnl_op_2 <X> lc_trk_g3_2 +(25 13) routing sp12_v_t_1 <X> lc_trk_g3_2 +(25 13) routing sp12_v_t_17 <X> lc_trk_g3_2 +(25 13) routing sp4_h_l_15 <X> lc_trk_g3_2 +(25 13) routing sp4_h_r_42 <X> lc_trk_g3_2 +(25 13) routing sp4_r_v_b_42 <X> lc_trk_g3_2 +(25 13) routing sp4_v_t_23 <X> lc_trk_g3_2 +(25 13) routing tnl_op_2 <X> lc_trk_g3_2 +(25 14) routing bnl_op_6 <X> lc_trk_g3_6 +(25 14) routing rgt_op_6 <X> lc_trk_g3_6 +(25 14) routing sp12_v_b_6 <X> lc_trk_g3_6 +(25 14) routing sp4_h_l_27 <X> lc_trk_g3_6 +(25 14) routing sp4_h_r_46 <X> lc_trk_g3_6 +(25 14) routing sp4_v_t_19 <X> lc_trk_g3_6 +(25 14) routing sp4_v_t_27 <X> lc_trk_g3_6 +(25 15) routing bnl_op_6 <X> lc_trk_g3_6 +(25 15) routing sp12_v_b_22 <X> lc_trk_g3_6 +(25 15) routing sp12_v_b_6 <X> lc_trk_g3_6 +(25 15) routing sp4_h_r_30 <X> lc_trk_g3_6 +(25 15) routing sp4_h_r_46 <X> lc_trk_g3_6 +(25 15) routing sp4_r_v_b_46 <X> lc_trk_g3_6 +(25 15) routing sp4_v_t_27 <X> lc_trk_g3_6 +(25 15) routing tnl_op_6 <X> lc_trk_g3_6 +(25 2) routing bnr_op_6 <X> lc_trk_g0_6 +(25 2) routing lft_op_6 <X> lc_trk_g0_6 +(25 2) routing sp12_h_l_5 <X> lc_trk_g0_6 +(25 2) routing sp4_h_l_11 <X> lc_trk_g0_6 +(25 2) routing sp4_h_l_3 <X> lc_trk_g0_6 +(25 2) routing sp4_v_b_14 <X> lc_trk_g0_6 +(25 2) routing sp4_v_b_6 <X> lc_trk_g0_6 +(25 3) routing bnr_op_6 <X> lc_trk_g0_6 +(25 3) routing sp12_h_l_5 <X> lc_trk_g0_6 +(25 3) routing sp12_h_r_22 <X> lc_trk_g0_6 +(25 3) routing sp4_h_l_11 <X> lc_trk_g0_6 +(25 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(25 3) routing sp4_r_v_b_30 <X> lc_trk_g0_6 +(25 3) routing sp4_v_b_14 <X> lc_trk_g0_6 +(25 4) routing bnr_op_2 <X> lc_trk_g1_2 +(25 4) routing lft_op_2 <X> lc_trk_g1_2 +(25 4) routing sp12_h_r_2 <X> lc_trk_g1_2 +(25 4) routing sp4_h_l_7 <X> lc_trk_g1_2 +(25 4) routing sp4_h_r_10 <X> lc_trk_g1_2 +(25 4) routing sp4_v_b_10 <X> lc_trk_g1_2 +(25 4) routing sp4_v_b_2 <X> lc_trk_g1_2 +(25 5) routing bnr_op_2 <X> lc_trk_g1_2 +(25 5) routing sp12_h_l_17 <X> lc_trk_g1_2 +(25 5) routing sp12_h_r_2 <X> lc_trk_g1_2 +(25 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(25 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(25 5) routing sp4_r_v_b_26 <X> lc_trk_g1_2 +(25 5) routing sp4_v_b_10 <X> lc_trk_g1_2 +(25 6) routing bnr_op_6 <X> lc_trk_g1_6 +(25 6) routing lft_op_6 <X> lc_trk_g1_6 +(25 6) routing sp12_h_l_5 <X> lc_trk_g1_6 +(25 6) routing sp4_h_l_11 <X> lc_trk_g1_6 +(25 6) routing sp4_h_l_3 <X> lc_trk_g1_6 +(25 6) routing sp4_v_b_14 <X> lc_trk_g1_6 +(25 6) routing sp4_v_b_6 <X> lc_trk_g1_6 +(25 7) routing bnr_op_6 <X> lc_trk_g1_6 +(25 7) routing sp12_h_l_5 <X> lc_trk_g1_6 +(25 7) routing sp12_h_r_22 <X> lc_trk_g1_6 +(25 7) routing sp4_h_l_11 <X> lc_trk_g1_6 +(25 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6 +(25 7) routing sp4_v_b_14 <X> lc_trk_g1_6 +(25 8) routing bnl_op_2 <X> lc_trk_g2_2 +(25 8) routing rgt_op_2 <X> lc_trk_g2_2 +(25 8) routing sp12_v_t_1 <X> lc_trk_g2_2 +(25 8) routing sp4_h_r_34 <X> lc_trk_g2_2 +(25 8) routing sp4_h_r_42 <X> lc_trk_g2_2 +(25 8) routing sp4_v_b_26 <X> lc_trk_g2_2 +(25 8) routing sp4_v_t_23 <X> lc_trk_g2_2 +(25 9) routing bnl_op_2 <X> lc_trk_g2_2 +(25 9) routing sp12_v_t_1 <X> lc_trk_g2_2 +(25 9) routing sp12_v_t_17 <X> lc_trk_g2_2 +(25 9) routing sp4_h_l_15 <X> lc_trk_g2_2 +(25 9) routing sp4_h_r_42 <X> lc_trk_g2_2 +(25 9) routing sp4_r_v_b_34 <X> lc_trk_g2_2 +(25 9) routing sp4_v_t_23 <X> lc_trk_g2_2 +(25 9) routing tnl_op_2 <X> lc_trk_g2_2 +(26 0) routing lc_trk_g0_4 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g0_6 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_5 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g1_7 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_4 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g2_6 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_5 <X> wire_mult/lc_0/in_0 +(26 0) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_2 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g0_6 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_3 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g1_7 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_2 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g2_6 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_3 <X> wire_mult/lc_0/in_0 +(26 1) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(26 2) routing lc_trk_g0_5 <X> wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g0_7 <X> wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g1_4 <X> wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g1_6 <X> wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g2_5 <X> wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g2_7 <X> wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g3_4 <X> wire_mult/lc_1/in_0 +(26 2) routing lc_trk_g3_6 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g0_3 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g0_7 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g1_2 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g1_6 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g2_3 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g2_7 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g3_2 <X> wire_mult/lc_1/in_0 +(26 3) routing lc_trk_g3_6 <X> wire_mult/lc_1/in_0 +(26 4) routing lc_trk_g0_4 <X> wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g0_6 <X> wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g1_5 <X> wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g1_7 <X> wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g2_4 <X> wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g2_6 <X> wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g3_5 <X> wire_mult/lc_2/in_0 +(26 4) routing lc_trk_g3_7 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g0_2 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g0_6 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g1_3 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g1_7 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g2_2 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g2_6 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g3_3 <X> wire_mult/lc_2/in_0 +(26 5) routing lc_trk_g3_7 <X> wire_mult/lc_2/in_0 +(26 6) routing lc_trk_g0_5 <X> wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g0_7 <X> wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g1_4 <X> wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g1_6 <X> wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g2_5 <X> wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g2_7 <X> wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g3_4 <X> wire_mult/lc_3/in_0 +(26 6) routing lc_trk_g3_6 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g0_3 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g0_7 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g1_2 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g1_6 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g2_3 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g2_7 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g3_2 <X> wire_mult/lc_3/in_0 +(26 7) routing lc_trk_g3_6 <X> wire_mult/lc_3/in_0 +(27 0) routing lc_trk_g1_0 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_1 +(27 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(27 1) routing lc_trk_g1_1 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_3 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_5 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g1_7 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_1 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_3 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_5 <X> wire_mult/lc_0/in_0 +(27 1) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(27 10) routing lc_trk_g1_1 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_1 +(27 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(27 12) routing lc_trk_g1_0 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_1 +(27 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(27 14) routing lc_trk_g1_1 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_1 +(27 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(27 2) routing lc_trk_g1_1 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_1 +(27 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(27 3) routing lc_trk_g1_0 <X> wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g1_2 <X> wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g1_4 <X> wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g1_6 <X> wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_0 <X> wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_2 <X> wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_4 <X> wire_mult/lc_1/in_0 +(27 3) routing lc_trk_g3_6 <X> wire_mult/lc_1/in_0 +(27 4) routing lc_trk_g1_0 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_1 +(27 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(27 5) routing lc_trk_g1_1 <X> wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g1_3 <X> wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g1_5 <X> wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g1_7 <X> wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_1 <X> wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_3 <X> wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_5 <X> wire_mult/lc_2/in_0 +(27 5) routing lc_trk_g3_7 <X> wire_mult/lc_2/in_0 +(27 6) routing lc_trk_g1_1 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_1 +(27 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(27 7) routing lc_trk_g1_0 <X> wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g1_2 <X> wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g1_4 <X> wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g1_6 <X> wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_0 <X> wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_2 <X> wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_4 <X> wire_mult/lc_3/in_0 +(27 7) routing lc_trk_g3_6 <X> wire_mult/lc_3/in_0 +(27 8) routing lc_trk_g1_0 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_1 +(27 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(28 0) routing lc_trk_g2_1 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_1 +(28 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(28 1) routing lc_trk_g2_0 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_2 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_4 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g2_6 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_1 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_3 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_5 <X> wire_mult/lc_0/in_0 +(28 1) routing lc_trk_g3_7 <X> wire_mult/lc_0/in_0 +(28 10) routing lc_trk_g2_0 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_1 +(28 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(28 12) routing lc_trk_g2_1 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_1 +(28 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(28 14) routing lc_trk_g2_0 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_1 +(28 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(28 2) routing lc_trk_g2_0 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_1 +(28 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(28 3) routing lc_trk_g2_1 <X> wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g2_3 <X> wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g2_5 <X> wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g2_7 <X> wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_0 <X> wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_2 <X> wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_4 <X> wire_mult/lc_1/in_0 +(28 3) routing lc_trk_g3_6 <X> wire_mult/lc_1/in_0 +(28 4) routing lc_trk_g2_1 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_1 +(28 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(28 5) routing lc_trk_g2_0 <X> wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g2_2 <X> wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g2_4 <X> wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g2_6 <X> wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_1 <X> wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_3 <X> wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_5 <X> wire_mult/lc_2/in_0 +(28 5) routing lc_trk_g3_7 <X> wire_mult/lc_2/in_0 +(28 6) routing lc_trk_g2_0 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_1 +(28 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(28 7) routing lc_trk_g2_1 <X> wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g2_3 <X> wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g2_5 <X> wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g2_7 <X> wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_0 <X> wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_2 <X> wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_4 <X> wire_mult/lc_3/in_0 +(28 7) routing lc_trk_g3_6 <X> wire_mult/lc_3/in_0 +(28 8) routing lc_trk_g2_1 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_1 +(28 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g0_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g1_6 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_1 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_3 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_5 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g2_7 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_0 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_2 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_4 wire_mult/lc_0/in_1 +(29 0) Enable bit of Mux _mult/lcb1_0 => lc_trk_g3_6 wire_mult/lc_0/in_1 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g0_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g1_7 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_0 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_2 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_4 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g2_6 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_1 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_3 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_5 wire_mult/lc_0/in_0 +(29 1) Enable bit of Mux _mult/lcb0_0 => lc_trk_g3_7 wire_mult/lc_0/in_0 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g0_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g1_7 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_0 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_2 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_4 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g2_6 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_1 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_3 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_5 wire_mult/lc_5/in_1 +(29 10) Enable bit of Mux _mult/lcb1_5 => lc_trk_g3_7 wire_mult/lc_5/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g0_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g1_6 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_1 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_3 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_5 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g2_7 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_0 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_2 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_4 wire_mult/lc_6/in_1 +(29 12) Enable bit of Mux _mult/lcb1_6 => lc_trk_g3_6 wire_mult/lc_6/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g0_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g1_7 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_0 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_2 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_4 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g2_6 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_1 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_3 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_5 wire_mult/lc_7/in_1 +(29 14) Enable bit of Mux _mult/lcb1_7 => lc_trk_g3_7 wire_mult/lc_7/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g0_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g1_7 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_0 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_2 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_4 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g2_6 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_1 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_3 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_5 wire_mult/lc_1/in_1 +(29 2) Enable bit of Mux _mult/lcb1_1 => lc_trk_g3_7 wire_mult/lc_1/in_1 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_1 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_3 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_5 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g0_7 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_0 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_2 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_4 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g1_6 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_1 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_3 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_5 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g2_7 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_0 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_2 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_4 wire_mult/lc_1/in_0 +(29 3) Enable bit of Mux _mult/lcb0_1 => lc_trk_g3_6 wire_mult/lc_1/in_0 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g0_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g1_6 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_1 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_3 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_5 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g2_7 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_0 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_2 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_4 wire_mult/lc_2/in_1 +(29 4) Enable bit of Mux _mult/lcb1_2 => lc_trk_g3_6 wire_mult/lc_2/in_1 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_0 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_2 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_4 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g0_6 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_1 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_3 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_5 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g1_7 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_0 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_2 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_4 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g2_6 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_1 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_3 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_5 wire_mult/lc_2/in_0 +(29 5) Enable bit of Mux _mult/lcb0_2 => lc_trk_g3_7 wire_mult/lc_2/in_0 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g0_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g1_7 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_0 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_2 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_4 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g2_6 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_1 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_3 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_5 wire_mult/lc_3/in_1 +(29 6) Enable bit of Mux _mult/lcb1_3 => lc_trk_g3_7 wire_mult/lc_3/in_1 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_1 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_3 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_5 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g0_7 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_0 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_2 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_4 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g1_6 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_1 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_3 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_5 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g2_7 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_0 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_2 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_4 wire_mult/lc_3/in_0 +(29 7) Enable bit of Mux _mult/lcb0_3 => lc_trk_g3_6 wire_mult/lc_3/in_0 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g0_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g1_6 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_1 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_3 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_5 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g2_7 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_0 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_2 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_4 wire_mult/lc_4/in_1 +(29 8) Enable bit of Mux _mult/lcb1_4 => lc_trk_g3_6 wire_mult/lc_4/in_1 +(3 0) routing sp12_h_r_0 <X> sp12_v_b_0 +(3 0) routing sp12_v_t_23 <X> sp12_v_b_0 +(3 1) routing sp12_h_l_23 <X> sp12_v_b_0 +(3 1) routing sp12_h_r_0 <X> sp12_v_b_0 +(3 10) routing sp12_v_t_22 <X> sp12_h_l_22 +(3 11) routing sp12_v_b_1 <X> sp12_h_l_22 +(3 12) routing sp12_v_b_1 <X> sp12_h_r_1 +(3 12) routing sp12_v_t_22 <X> sp12_h_r_1 +(3 13) routing sp12_h_l_22 <X> sp12_h_r_1 +(3 13) routing sp12_v_b_1 <X> sp12_h_r_1 +(3 14) routing sp12_h_r_1 <X> sp12_v_t_22 +(3 14) routing sp12_v_b_1 <X> sp12_v_t_22 +(3 15) routing sp12_h_l_22 <X> sp12_v_t_22 +(3 15) routing sp12_h_r_1 <X> sp12_v_t_22 +(3 2) routing sp12_h_r_0 <X> sp12_h_l_23 +(3 2) routing sp12_v_t_23 <X> sp12_h_l_23 +(3 3) routing sp12_h_r_0 <X> sp12_h_l_23 +(3 3) routing sp12_v_b_0 <X> sp12_h_l_23 +(3 4) routing sp12_v_b_0 <X> sp12_h_r_0 +(3 4) routing sp12_v_t_23 <X> sp12_h_r_0 +(3 5) routing sp12_h_l_23 <X> sp12_h_r_0 +(3 5) routing sp12_v_b_0 <X> sp12_h_r_0 +(3 6) routing sp12_h_r_0 <X> sp12_v_t_23 +(3 6) routing sp12_v_b_0 <X> sp12_v_t_23 +(3 7) routing sp12_h_l_23 <X> sp12_v_t_23 +(3 7) routing sp12_h_r_0 <X> sp12_v_t_23 +(3 8) routing sp12_h_r_1 <X> sp12_v_b_1 +(3 8) routing sp12_v_t_22 <X> sp12_v_b_1 +(3 9) routing sp12_h_l_22 <X> sp12_v_b_1 +(3 9) routing sp12_h_r_1 <X> sp12_v_b_1 +(30 0) routing lc_trk_g0_5 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_1 +(30 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_3 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_1 +(30 1) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_1 +(30 10) routing lc_trk_g0_4 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_1 +(30 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_2 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_1 +(30 11) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_1 +(30 12) routing lc_trk_g0_5 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_1 +(30 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_3 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_1 +(30 13) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_1 +(30 14) routing lc_trk_g0_4 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_1 +(30 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_2 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_1 +(30 15) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_1 +(30 2) routing lc_trk_g0_4 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_1 +(30 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_2 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_1 +(30 3) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_1 +(30 4) routing lc_trk_g0_5 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_1 +(30 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_3 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_1 +(30 5) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_1 +(30 6) routing lc_trk_g0_4 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_1 +(30 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_2 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_1 +(30 7) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_1 +(30 8) routing lc_trk_g0_5 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_1 +(30 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_3 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_1 +(30 9) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_1 +(31 0) routing lc_trk_g0_5 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_3 +(31 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_3 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g0_7 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_3 +(31 1) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(31 10) routing lc_trk_g0_4 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_3 +(31 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_2 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g0_6 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_3 +(31 11) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(31 12) routing lc_trk_g0_5 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_3 +(31 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_3 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g0_7 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_3 +(31 13) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(31 14) routing lc_trk_g0_4 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_3 +(31 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_2 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g0_6 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_3 +(31 15) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(31 2) routing lc_trk_g0_4 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_3 +(31 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_2 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g0_6 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_3 +(31 3) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(31 4) routing lc_trk_g0_5 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_3 +(31 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_3 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g0_7 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_3 +(31 5) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(31 6) routing lc_trk_g0_4 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_3 +(31 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_2 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g0_6 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_3 +(31 7) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(31 8) routing lc_trk_g0_5 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_3 +(31 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_3 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g0_7 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_3 +(31 9) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g0_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g1_6 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_1 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_3 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_5 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g2_7 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_0 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_2 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_4 wire_mult/lc_0/in_3 +(32 0) Enable bit of Mux _mult/lcb3_0 => lc_trk_g3_6 wire_mult/lc_0/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g0_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g1_7 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_0 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_2 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_4 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g2_6 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_1 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_3 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_5 wire_mult/lc_5/in_3 +(32 10) Enable bit of Mux _mult/lcb3_5 => lc_trk_g3_7 wire_mult/lc_5/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g0_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g1_6 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_1 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_3 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_5 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g2_7 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_0 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_2 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_4 wire_mult/lc_6/in_3 +(32 12) Enable bit of Mux _mult/lcb3_6 => lc_trk_g3_6 wire_mult/lc_6/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g0_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g1_7 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_0 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_2 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_4 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g2_6 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_1 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_3 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_5 wire_mult/lc_7/in_3 +(32 14) Enable bit of Mux _mult/lcb3_7 => lc_trk_g3_7 wire_mult/lc_7/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g0_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g1_7 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_0 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_2 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_4 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g2_6 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_1 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_3 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_5 wire_mult/lc_1/in_3 +(32 2) Enable bit of Mux _mult/lcb3_1 => lc_trk_g3_7 wire_mult/lc_1/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g0_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g1_6 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_1 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_3 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_5 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g2_7 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_0 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_2 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_4 wire_mult/lc_2/in_3 +(32 4) Enable bit of Mux _mult/lcb3_2 => lc_trk_g3_6 wire_mult/lc_2/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g0_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g1_7 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_0 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_2 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_4 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g2_6 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_1 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_3 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_5 wire_mult/lc_3/in_3 +(32 6) Enable bit of Mux _mult/lcb3_3 => lc_trk_g3_7 wire_mult/lc_3/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g0_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g1_6 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_1 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_3 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_5 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g2_7 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_0 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_2 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_4 wire_mult/lc_4/in_3 +(32 8) Enable bit of Mux _mult/lcb3_4 => lc_trk_g3_6 wire_mult/lc_4/in_3 +(33 0) routing lc_trk_g2_1 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_3 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_5 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g2_7 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_3 +(33 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(33 10) routing lc_trk_g2_0 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_2 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_4 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g2_6 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_3 +(33 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(33 12) routing lc_trk_g2_1 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_3 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_5 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g2_7 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_3 +(33 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(33 14) routing lc_trk_g2_0 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_2 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_4 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g2_6 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_3 +(33 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(33 2) routing lc_trk_g2_0 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_2 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_4 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g2_6 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_3 +(33 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(33 4) routing lc_trk_g2_1 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_3 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_5 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g2_7 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_3 +(33 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(33 6) routing lc_trk_g2_0 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_2 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_4 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g2_6 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_3 +(33 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(33 8) routing lc_trk_g2_1 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_3 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_5 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g2_7 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_3 +(33 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(34 0) routing lc_trk_g1_0 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_2 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_4 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g1_6 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_0 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_2 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_4 <X> wire_mult/lc_0/in_3 +(34 0) routing lc_trk_g3_6 <X> wire_mult/lc_0/in_3 +(34 10) routing lc_trk_g1_1 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_3 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_5 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g1_7 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_1 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_3 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_5 <X> wire_mult/lc_5/in_3 +(34 10) routing lc_trk_g3_7 <X> wire_mult/lc_5/in_3 +(34 12) routing lc_trk_g1_0 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_2 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_4 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g1_6 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_0 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_2 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_4 <X> wire_mult/lc_6/in_3 +(34 12) routing lc_trk_g3_6 <X> wire_mult/lc_6/in_3 +(34 14) routing lc_trk_g1_1 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_3 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_5 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g1_7 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_1 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_3 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_5 <X> wire_mult/lc_7/in_3 +(34 14) routing lc_trk_g3_7 <X> wire_mult/lc_7/in_3 +(34 2) routing lc_trk_g1_1 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_3 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_5 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g1_7 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_1 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_3 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_5 <X> wire_mult/lc_1/in_3 +(34 2) routing lc_trk_g3_7 <X> wire_mult/lc_1/in_3 +(34 4) routing lc_trk_g1_0 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_2 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_4 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g1_6 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_0 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_2 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_4 <X> wire_mult/lc_2/in_3 +(34 4) routing lc_trk_g3_6 <X> wire_mult/lc_2/in_3 +(34 6) routing lc_trk_g1_1 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_3 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_5 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g1_7 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_1 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_3 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_5 <X> wire_mult/lc_3/in_3 +(34 6) routing lc_trk_g3_7 <X> wire_mult/lc_3/in_3 +(34 8) routing lc_trk_g1_0 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_2 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_4 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g1_6 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_0 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_2 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_4 <X> wire_mult/lc_4/in_3 +(34 8) routing lc_trk_g3_6 <X> wire_mult/lc_4/in_3 +(36 0) LC_0 Logic Functioning bit +(36 1) LC_0 Logic Functioning bit +(36 10) LC_5 Logic Functioning bit +(36 11) LC_5 Logic Functioning bit +(36 12) LC_6 Logic Functioning bit +(36 13) LC_6 Logic Functioning bit +(36 14) LC_7 Logic Functioning bit +(36 15) LC_7 Logic Functioning bit +(36 2) LC_1 Logic Functioning bit +(36 3) LC_1 Logic Functioning bit +(36 4) LC_2 Logic Functioning bit +(36 5) LC_2 Logic Functioning bit +(36 6) LC_3 Logic Functioning bit +(36 7) LC_3 Logic Functioning bit +(36 8) LC_4 Logic Functioning bit +(36 9) LC_4 Logic Functioning bit +(37 0) LC_0 Logic Functioning bit +(37 1) LC_0 Logic Functioning bit +(37 10) LC_5 Logic Functioning bit +(37 11) LC_5 Logic Functioning bit +(37 12) LC_6 Logic Functioning bit +(37 13) LC_6 Logic Functioning bit +(37 14) LC_7 Logic Functioning bit +(37 15) LC_7 Logic Functioning bit +(37 2) LC_1 Logic Functioning bit +(37 3) LC_1 Logic Functioning bit +(37 4) LC_2 Logic Functioning bit +(37 5) LC_2 Logic Functioning bit +(37 6) LC_3 Logic Functioning bit +(37 7) LC_3 Logic Functioning bit +(37 8) LC_4 Logic Functioning bit +(37 9) LC_4 Logic Functioning bit +(4 0) routing sp4_h_l_37 <X> sp4_v_b_0 +(4 0) routing sp4_h_l_43 <X> sp4_v_b_0 +(4 0) routing sp4_v_t_37 <X> sp4_v_b_0 +(4 0) routing sp4_v_t_41 <X> sp4_v_b_0 +(4 1) routing sp4_h_l_41 <X> sp4_h_r_0 +(4 1) routing sp4_v_b_6 <X> sp4_h_r_0 +(4 1) routing sp4_v_t_42 <X> sp4_h_r_0 +(4 10) routing sp4_h_r_0 <X> sp4_v_t_43 +(4 10) routing sp4_h_r_6 <X> sp4_v_t_43 +(4 10) routing sp4_v_b_10 <X> sp4_v_t_43 +(4 10) routing sp4_v_b_6 <X> sp4_v_t_43 +(4 11) routing sp4_h_r_10 <X> sp4_h_l_43 +(4 11) routing sp4_v_b_1 <X> sp4_h_l_43 +(4 11) routing sp4_v_t_37 <X> sp4_h_l_43 +(4 12) routing sp4_h_l_38 <X> sp4_v_b_9 +(4 12) routing sp4_h_l_44 <X> sp4_v_b_9 +(4 12) routing sp4_v_t_36 <X> sp4_v_b_9 +(4 12) routing sp4_v_t_44 <X> sp4_v_b_9 +(4 13) routing sp4_v_b_3 <X> sp4_h_r_9 +(4 13) routing sp4_v_t_41 <X> sp4_h_r_9 +(4 14) routing sp4_h_r_3 <X> sp4_v_t_44 +(4 14) routing sp4_h_r_9 <X> sp4_v_t_44 +(4 14) routing sp4_v_b_1 <X> sp4_v_t_44 +(4 14) routing sp4_v_b_9 <X> sp4_v_t_44 +(4 15) routing sp4_h_r_1 <X> sp4_h_l_44 +(4 15) routing sp4_h_r_6 <X> sp4_h_l_44 +(4 15) routing sp4_v_b_4 <X> sp4_h_l_44 +(4 15) routing sp4_v_t_38 <X> sp4_h_l_44 +(4 2) routing sp4_h_r_0 <X> sp4_v_t_37 +(4 2) routing sp4_h_r_6 <X> sp4_v_t_37 +(4 2) routing sp4_v_b_0 <X> sp4_v_t_37 +(4 2) routing sp4_v_b_4 <X> sp4_v_t_37 +(4 3) routing sp4_h_r_4 <X> sp4_h_l_37 +(4 3) routing sp4_v_b_7 <X> sp4_h_l_37 +(4 3) routing sp4_v_t_43 <X> sp4_h_l_37 +(4 4) routing sp4_h_l_38 <X> sp4_v_b_3 +(4 4) routing sp4_h_l_44 <X> sp4_v_b_3 +(4 4) routing sp4_v_t_38 <X> sp4_v_b_3 +(4 4) routing sp4_v_t_42 <X> sp4_v_b_3 +(4 5) routing sp4_v_b_9 <X> sp4_h_r_3 +(4 5) routing sp4_v_t_47 <X> sp4_h_r_3 +(4 6) routing sp4_h_r_3 <X> sp4_v_t_38 +(4 6) routing sp4_h_r_9 <X> sp4_v_t_38 +(4 6) routing sp4_v_b_3 <X> sp4_v_t_38 +(4 6) routing sp4_v_b_7 <X> sp4_v_t_38 +(4 7) routing sp4_h_r_0 <X> sp4_h_l_38 +(4 7) routing sp4_v_b_10 <X> sp4_h_l_38 +(4 7) routing sp4_v_t_44 <X> sp4_h_l_38 +(4 8) routing sp4_h_l_37 <X> sp4_v_b_6 +(4 8) routing sp4_h_l_43 <X> sp4_v_b_6 +(4 8) routing sp4_v_t_43 <X> sp4_v_b_6 +(4 8) routing sp4_v_t_47 <X> sp4_v_b_6 +(4 9) routing sp4_v_b_0 <X> sp4_h_r_6 +(4 9) routing sp4_v_t_36 <X> sp4_h_r_6 +(42 0) LC_0 Logic Functioning bit +(42 1) LC_0 Logic Functioning bit +(42 10) LC_5 Logic Functioning bit +(42 11) LC_5 Logic Functioning bit +(42 12) LC_6 Logic Functioning bit +(42 13) LC_6 Logic Functioning bit +(42 14) LC_7 Logic Functioning bit +(42 15) LC_7 Logic Functioning bit +(42 2) LC_1 Logic Functioning bit +(42 3) LC_1 Logic Functioning bit +(42 4) LC_2 Logic Functioning bit +(42 5) LC_2 Logic Functioning bit +(42 6) LC_3 Logic Functioning bit +(42 7) LC_3 Logic Functioning bit +(42 8) LC_4 Logic Functioning bit +(42 9) LC_4 Logic Functioning bit +(43 0) LC_0 Logic Functioning bit +(43 1) LC_0 Logic Functioning bit +(43 10) LC_5 Logic Functioning bit +(43 11) LC_5 Logic Functioning bit +(43 12) LC_6 Logic Functioning bit +(43 13) LC_6 Logic Functioning bit +(43 14) LC_7 Logic Functioning bit +(43 15) LC_7 Logic Functioning bit +(43 2) LC_1 Logic Functioning bit +(43 3) LC_1 Logic Functioning bit +(43 4) LC_2 Logic Functioning bit +(43 5) LC_2 Logic Functioning bit +(43 6) LC_3 Logic Functioning bit +(43 7) LC_3 Logic Functioning bit +(43 8) LC_4 Logic Functioning bit +(43 9) LC_4 Logic Functioning bit +(46 0) Enable bit of Mux _out_links/OutMux7_0 => wire_mult/mult/O_24 sp4_h_l_5 +(46 1) Enable bit of Mux _out_links/OutMux6_0 => wire_mult/mult/O_24 sp4_h_r_0 +(46 10) Enable bit of Mux _out_links/OutMux7_5 => wire_mult/mult/O_29 sp4_h_l_15 +(46 11) Enable bit of Mux _out_links/OutMux6_5 => wire_mult/mult/O_29 sp4_h_r_10 +(46 12) Enable bit of Mux _out_links/OutMux7_6 => wire_mult/mult/O_30 sp4_h_l_17 +(46 13) Enable bit of Mux _out_links/OutMux6_6 => wire_mult/mult/O_30 sp4_h_r_12 +(46 14) Enable bit of Mux _out_links/OutMux7_7 => wire_mult/mult/O_31 sp4_h_r_30 +(46 15) Enable bit of Mux _out_links/OutMux6_7 => wire_mult/mult/O_31 sp4_h_l_3 +(46 2) Enable bit of Mux _out_links/OutMux7_1 => wire_mult/mult/O_25 sp4_h_l_7 +(46 3) Enable bit of Mux _out_links/OutMux6_1 => wire_mult/mult/O_25 sp4_h_r_2 +(46 4) Enable bit of Mux _out_links/OutMux7_2 => wire_mult/mult/O_26 sp4_h_r_20 +(46 5) Enable bit of Mux _out_links/OutMux6_2 => wire_mult/mult/O_26 sp4_h_r_4 +(46 6) Enable bit of Mux _out_links/OutMux7_3 => wire_mult/mult/O_27 sp4_h_l_11 +(46 7) Enable bit of Mux _out_links/OutMux6_3 => wire_mult/mult/O_27 sp4_h_r_6 +(46 8) Enable bit of Mux _out_links/OutMux7_4 => wire_mult/mult/O_28 sp4_h_l_13 +(46 9) Enable bit of Mux _out_links/OutMux6_4 => wire_mult/mult/O_28 sp4_h_r_8 +(47 0) Enable bit of Mux _out_links/OutMux5_0 => wire_mult/mult/O_24 sp12_h_r_8 +(47 1) Enable bit of Mux _out_links/OutMux8_0 => wire_mult/mult/O_24 sp4_h_r_32 +(47 10) Enable bit of Mux _out_links/OutMux4_5 => wire_mult/mult/O_29 sp12_h_r_2 +(47 11) Enable bit of Mux _out_links/OutMux8_5 => wire_mult/mult/O_29 sp4_h_r_42 +(47 12) Enable bit of Mux _out_links/OutMux4_6 => wire_mult/mult/O_30 sp12_h_r_4 +(47 13) Enable bit of Mux _out_links/OutMux8_6 => wire_mult/mult/O_30 sp4_h_l_33 +(47 14) Enable bit of Mux _out_links/OutMux4_7 => wire_mult/mult/O_31 sp12_h_l_5 +(47 15) Enable bit of Mux _out_links/OutMux8_7 => wire_mult/mult/O_31 sp4_h_r_46 +(47 2) Enable bit of Mux _out_links/OutMux5_1 => wire_mult/mult/O_25 sp12_h_l_9 +(47 3) Enable bit of Mux _out_links/OutMux8_1 => wire_mult/mult/O_25 sp4_h_r_34 +(47 4) Enable bit of Mux _out_links/OutMux5_2 => wire_mult/mult/O_26 sp12_h_l_11 +(47 5) Enable bit of Mux _out_links/OutMux8_2 => wire_mult/mult/O_26 sp4_h_l_25 +(47 6) Enable bit of Mux _out_links/OutMux5_3 => wire_mult/mult/O_27 sp12_h_r_14 +(47 7) Enable bit of Mux _out_links/OutMux8_3 => wire_mult/mult/O_27 sp4_h_l_27 +(47 8) Enable bit of Mux _out_links/OutMux4_4 => wire_mult/mult/O_28 sp12_h_r_0 +(47 9) Enable bit of Mux _out_links/OutMux8_4 => wire_mult/mult/O_28 sp4_h_r_40 +(48 0) Enable bit of Mux _out_links/OutMux0_0 => wire_mult/mult/O_24 sp4_v_b_0 +(48 1) Enable bit of Mux _out_links/OutMux1_0 => wire_mult/mult/O_24 sp4_v_t_5 +(48 10) Enable bit of Mux _out_links/OutMux5_5 => wire_mult/mult/O_29 sp12_h_l_17 +(48 11) Enable bit of Mux _out_links/OutMux0_5 => wire_mult/mult/O_29 sp4_v_b_10 +(48 12) Enable bit of Mux _out_links/OutMux5_6 => wire_mult/mult/O_30 sp12_h_r_20 +(48 13) Enable bit of Mux _out_links/OutMux0_6 => wire_mult/mult/O_30 sp4_v_t_1 +(48 14) Enable bit of Mux _out_links/OutMux5_7 => wire_mult/mult/O_31 sp12_h_r_22 +(48 15) Enable bit of Mux _out_links/OutMux0_7 => wire_mult/mult/O_31 sp4_v_b_14 +(48 2) Enable bit of Mux _out_links/OutMux0_1 => wire_mult/mult/O_25 sp4_v_b_2 +(48 3) Enable bit of Mux _out_links/OutMux1_1 => wire_mult/mult/O_25 sp4_v_b_18 +(48 4) Enable bit of Mux _out_links/OutMux0_2 => wire_mult/mult/O_26 sp4_v_b_4 +(48 5) Enable bit of Mux _out_links/OutMux1_2 => wire_mult/mult/O_26 sp4_v_b_20 +(48 6) Enable bit of Mux _out_links/OutMux0_3 => wire_mult/mult/O_27 sp4_v_b_6 +(48 7) Enable bit of Mux _out_links/OutMux1_3 => wire_mult/mult/O_27 sp4_v_b_22 +(48 8) Enable bit of Mux _out_links/OutMux5_4 => wire_mult/mult/O_28 sp12_h_r_16 +(48 9) Enable bit of Mux _out_links/OutMux0_4 => wire_mult/mult/O_28 sp4_v_b_8 +(5 0) routing sp4_v_b_0 <X> sp4_h_r_0 +(5 0) routing sp4_v_b_6 <X> sp4_h_r_0 +(5 1) routing sp4_h_l_37 <X> sp4_v_b_0 +(5 1) routing sp4_h_l_43 <X> sp4_v_b_0 +(5 1) routing sp4_h_r_0 <X> sp4_v_b_0 +(5 1) routing sp4_v_t_44 <X> sp4_v_b_0 +(5 10) routing sp4_v_b_6 <X> sp4_h_l_43 +(5 10) routing sp4_v_t_37 <X> sp4_h_l_43 +(5 10) routing sp4_v_t_43 <X> sp4_h_l_43 +(5 11) routing sp4_h_l_43 <X> sp4_v_t_43 +(5 11) routing sp4_h_r_0 <X> sp4_v_t_43 +(5 11) routing sp4_h_r_6 <X> sp4_v_t_43 +(5 11) routing sp4_v_b_3 <X> sp4_v_t_43 +(5 12) routing sp4_v_b_3 <X> sp4_h_r_9 +(5 12) routing sp4_v_b_9 <X> sp4_h_r_9 +(5 12) routing sp4_v_t_44 <X> sp4_h_r_9 +(5 13) routing sp4_h_l_38 <X> sp4_v_b_9 +(5 13) routing sp4_h_l_44 <X> sp4_v_b_9 +(5 13) routing sp4_v_t_43 <X> sp4_v_b_9 +(5 14) routing sp4_h_r_6 <X> sp4_h_l_44 +(5 14) routing sp4_v_b_9 <X> sp4_h_l_44 +(5 14) routing sp4_v_t_38 <X> sp4_h_l_44 +(5 15) routing sp4_h_l_44 <X> sp4_v_t_44 +(5 15) routing sp4_h_r_3 <X> sp4_v_t_44 +(5 15) routing sp4_h_r_9 <X> sp4_v_t_44 +(5 15) routing sp4_v_b_6 <X> sp4_v_t_44 +(5 2) routing sp4_v_b_0 <X> sp4_h_l_37 +(5 2) routing sp4_v_t_37 <X> sp4_h_l_37 +(5 2) routing sp4_v_t_43 <X> sp4_h_l_37 +(5 3) routing sp4_h_l_37 <X> sp4_v_t_37 +(5 3) routing sp4_h_r_0 <X> sp4_v_t_37 +(5 3) routing sp4_h_r_6 <X> sp4_v_t_37 +(5 3) routing sp4_v_b_9 <X> sp4_v_t_37 +(5 4) routing sp4_v_b_3 <X> sp4_h_r_3 +(5 4) routing sp4_v_b_9 <X> sp4_h_r_3 +(5 4) routing sp4_v_t_38 <X> sp4_h_r_3 +(5 5) routing sp4_h_l_38 <X> sp4_v_b_3 +(5 5) routing sp4_h_l_44 <X> sp4_v_b_3 +(5 5) routing sp4_h_r_3 <X> sp4_v_b_3 +(5 5) routing sp4_v_t_37 <X> sp4_v_b_3 +(5 6) routing sp4_h_r_0 <X> sp4_h_l_38 +(5 6) routing sp4_v_b_3 <X> sp4_h_l_38 +(5 6) routing sp4_v_t_38 <X> sp4_h_l_38 +(5 6) routing sp4_v_t_44 <X> sp4_h_l_38 +(5 7) routing sp4_h_l_38 <X> sp4_v_t_38 +(5 7) routing sp4_h_r_3 <X> sp4_v_t_38 +(5 7) routing sp4_h_r_9 <X> sp4_v_t_38 +(5 7) routing sp4_v_b_0 <X> sp4_v_t_38 +(5 8) routing sp4_v_b_0 <X> sp4_h_r_6 +(5 8) routing sp4_v_b_6 <X> sp4_h_r_6 +(5 8) routing sp4_v_t_43 <X> sp4_h_r_6 +(5 9) routing sp4_h_l_37 <X> sp4_v_b_6 +(5 9) routing sp4_h_l_43 <X> sp4_v_b_6 +(5 9) routing sp4_h_r_6 <X> sp4_v_b_6 +(5 9) routing sp4_v_t_38 <X> sp4_v_b_6 +(50 0) Cascade buffer Enable bit: MULT3_LC00_inmux02_5 +(50 10) Cascade buffer Enable bit: MULT3_LC05_inmux02_5 +(50 12) Cascade buffer Enable bit: MULT3_LC06_inmux02_5 +(50 14) Cascade buffer Enable bit: MULT3_LC07_inmux02_5 +(50 2) Cascade buffer Enable bit: MULT3_LC01_inmux02_5 +(50 4) Cascade buffer Enable bit: MULT3_LC02_inmux02_5 +(50 6) Cascade buffer Enable bit: MULT3_LC03_inmux02_5 +(50 8) Cascade buffer Enable bit: MULT3_LC04_inmux02_5 +(51 0) Enable bit of Mux _out_links/OutMux3_0 => wire_mult/mult/O_24 sp12_v_b_0 +(51 1) Enable bit of Mux _out_links/OutMux2_0 => wire_mult/mult/O_24 sp4_v_b_32 +(51 10) Enable bit of Mux _out_links/OutMux2_5 => wire_mult/mult/O_29 sp4_v_t_31 +(51 11) Enable bit of Mux _out_links/OutMux1_5 => wire_mult/mult/O_29 sp4_v_b_26 +(51 12) Enable bit of Mux _out_links/OutMux2_6 => wire_mult/mult/O_30 sp4_v_b_44 +(51 13) Enable bit of Mux _out_links/OutMux1_6 => wire_mult/mult/O_30 sp4_v_b_28 +(51 14) Enable bit of Mux _out_links/OutMux2_7 => wire_mult/mult/O_31 sp4_v_b_46 +(51 15) Enable bit of Mux _out_links/OutMux1_7 => wire_mult/mult/O_31 sp4_v_t_19 +(51 2) Enable bit of Mux _out_links/OutMux3_1 => wire_mult/mult/O_25 sp12_v_t_1 +(51 3) Enable bit of Mux _out_links/OutMux2_1 => wire_mult/mult/O_25 sp4_v_t_23 +(51 4) Enable bit of Mux _out_links/OutMux3_2 => wire_mult/mult/O_26 sp12_v_t_3 +(51 5) Enable bit of Mux _out_links/OutMux2_2 => wire_mult/mult/O_26 sp4_v_t_25 +(51 6) Enable bit of Mux _out_links/OutMux3_3 => wire_mult/mult/O_27 sp12_v_b_6 +(51 7) Enable bit of Mux _out_links/OutMux2_3 => wire_mult/mult/O_27 sp4_v_t_27 +(51 8) Enable bit of Mux _out_links/OutMux2_4 => wire_mult/mult/O_28 sp4_v_t_29 +(51 9) Enable bit of Mux _out_links/OutMux1_4 => wire_mult/mult/O_28 sp4_v_t_13 +(52 0) Enable bit of Mux _out_links/OutMux4_0 => wire_mult/mult/O_24 sp12_v_b_16 +(52 1) Enable bit of Mux _out_links/OutMux9_0 => wire_mult/mult/O_24 sp4_r_v_b_1 +(52 10) Enable bit of Mux _out_links/OutMux3_5 => wire_mult/mult/O_29 sp12_v_t_9 +(52 11) Enable bit of Mux _out_links/OutMux9_5 => wire_mult/mult/O_29 sp4_r_v_b_11 +(52 12) Enable bit of Mux _out_links/OutMux3_6 => wire_mult/mult/O_30 sp12_v_b_12 +(52 13) Enable bit of Mux _out_links/OutMux9_6 => wire_mult/mult/O_30 sp4_r_v_b_13 +(52 14) Enable bit of Mux _out_links/OutMux3_7 => wire_mult/mult/O_31 sp12_v_t_13 +(52 15) Enable bit of Mux _out_links/OutMux9_7 => wire_mult/mult/O_31 sp4_r_v_b_15 +(52 2) Enable bit of Mux _out_links/OutMux4_1 => wire_mult/mult/O_25 sp12_v_t_17 +(52 3) Enable bit of Mux _out_links/OutMux9_1 => wire_mult/mult/O_25 sp4_r_v_b_3 +(52 4) Enable bit of Mux _out_links/OutMux4_2 => wire_mult/mult/O_26 sp12_v_b_20 +(52 5) Enable bit of Mux _out_links/OutMux9_2 => wire_mult/mult/O_26 sp4_r_v_b_5 +(52 6) Enable bit of Mux _out_links/OutMux4_3 => wire_mult/mult/O_27 sp12_v_b_22 +(52 7) Enable bit of Mux _out_links/OutMux9_3 => wire_mult/mult/O_27 sp4_r_v_b_7 +(52 8) Enable bit of Mux _out_links/OutMux3_4 => wire_mult/mult/O_28 sp12_v_t_7 +(52 9) Enable bit of Mux _out_links/OutMux9_4 => wire_mult/mult/O_28 sp4_r_v_b_9 +(53 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_mult/mult/O_24 sp4_r_v_b_17 +(53 1) Enable bit of Mux _out_links/OutMuxb_0 => wire_mult/mult/O_24 sp4_r_v_b_33 +(53 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_mult/mult/O_29 sp4_r_v_b_27 +(53 11) Enable bit of Mux _out_links/OutMuxb_5 => wire_mult/mult/O_29 sp4_r_v_b_43 +(53 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_mult/mult/O_30 sp4_r_v_b_29 +(53 13) Enable bit of Mux _out_links/OutMuxb_6 => wire_mult/mult/O_30 sp4_r_v_b_45 +(53 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_mult/mult/O_31 sp4_r_v_b_31 +(53 15) Enable bit of Mux _out_links/OutMuxb_7 => wire_mult/mult/O_31 sp4_r_v_b_47 +(53 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_mult/mult/O_25 sp4_r_v_b_19 +(53 3) Enable bit of Mux _out_links/OutMuxb_1 => wire_mult/mult/O_25 sp4_r_v_b_35 +(53 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_mult/mult/O_26 sp4_r_v_b_21 +(53 5) Enable bit of Mux _out_links/OutMuxb_2 => wire_mult/mult/O_26 sp4_r_v_b_37 +(53 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_mult/mult/O_27 sp4_r_v_b_23 +(53 7) Enable bit of Mux _out_links/OutMuxb_3 => wire_mult/mult/O_27 sp4_r_v_b_39 +(53 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_mult/mult/O_28 sp4_r_v_b_25 +(53 9) Enable bit of Mux _out_links/OutMuxb_4 => wire_mult/mult/O_28 sp4_r_v_b_41 +(6 0) routing sp4_h_l_43 <X> sp4_v_b_0 +(6 0) routing sp4_h_r_7 <X> sp4_v_b_0 +(6 0) routing sp4_v_t_41 <X> sp4_v_b_0 +(6 0) routing sp4_v_t_44 <X> sp4_v_b_0 +(6 1) routing sp4_h_l_41 <X> sp4_h_r_0 +(6 1) routing sp4_v_b_0 <X> sp4_h_r_0 +(6 1) routing sp4_v_b_6 <X> sp4_h_r_0 +(6 10) routing sp4_h_l_36 <X> sp4_v_t_43 +(6 10) routing sp4_h_r_0 <X> sp4_v_t_43 +(6 10) routing sp4_v_b_10 <X> sp4_v_t_43 +(6 10) routing sp4_v_b_3 <X> sp4_v_t_43 +(6 11) routing sp4_h_r_10 <X> sp4_h_l_43 +(6 11) routing sp4_h_r_6 <X> sp4_h_l_43 +(6 11) routing sp4_v_t_37 <X> sp4_h_l_43 +(6 11) routing sp4_v_t_43 <X> sp4_h_l_43 +(6 12) routing sp4_h_l_38 <X> sp4_v_b_9 +(6 12) routing sp4_h_r_4 <X> sp4_v_b_9 +(6 12) routing sp4_v_t_36 <X> sp4_v_b_9 +(6 12) routing sp4_v_t_43 <X> sp4_v_b_9 +(6 13) routing sp4_v_b_3 <X> sp4_h_r_9 +(6 13) routing sp4_v_b_9 <X> sp4_h_r_9 +(6 14) routing sp4_h_l_41 <X> sp4_v_t_44 +(6 14) routing sp4_h_r_3 <X> sp4_v_t_44 +(6 14) routing sp4_v_b_1 <X> sp4_v_t_44 +(6 14) routing sp4_v_b_6 <X> sp4_v_t_44 +(6 15) routing sp4_h_r_1 <X> sp4_h_l_44 +(6 15) routing sp4_v_t_38 <X> sp4_h_l_44 +(6 2) routing sp4_h_l_42 <X> sp4_v_t_37 +(6 2) routing sp4_h_r_6 <X> sp4_v_t_37 +(6 2) routing sp4_v_b_4 <X> sp4_v_t_37 +(6 2) routing sp4_v_b_9 <X> sp4_v_t_37 +(6 3) routing sp4_h_r_0 <X> sp4_h_l_37 +(6 3) routing sp4_h_r_4 <X> sp4_h_l_37 +(6 3) routing sp4_v_t_37 <X> sp4_h_l_37 +(6 3) routing sp4_v_t_43 <X> sp4_h_l_37 +(6 4) routing sp4_h_l_44 <X> sp4_v_b_3 +(6 4) routing sp4_h_r_10 <X> sp4_v_b_3 +(6 4) routing sp4_v_t_37 <X> sp4_v_b_3 +(6 4) routing sp4_v_t_42 <X> sp4_v_b_3 +(6 5) routing sp4_v_b_3 <X> sp4_h_r_3 +(6 5) routing sp4_v_b_9 <X> sp4_h_r_3 +(6 6) routing sp4_h_l_47 <X> sp4_v_t_38 +(6 6) routing sp4_h_r_9 <X> sp4_v_t_38 +(6 6) routing sp4_v_b_0 <X> sp4_v_t_38 +(6 6) routing sp4_v_b_7 <X> sp4_v_t_38 +(6 7) routing sp4_v_t_38 <X> sp4_h_l_38 +(6 7) routing sp4_v_t_44 <X> sp4_h_l_38 +(6 8) routing sp4_h_l_37 <X> sp4_v_b_6 +(6 8) routing sp4_h_r_1 <X> sp4_v_b_6 +(6 8) routing sp4_v_t_38 <X> sp4_v_b_6 +(6 8) routing sp4_v_t_47 <X> sp4_v_b_6 +(6 9) routing sp4_v_b_0 <X> sp4_h_r_6 +(6 9) routing sp4_v_b_6 <X> sp4_h_r_6 +(7 1) MAC16 functional bit: MULT3_bram_cbit_0 +(7 10) Column buffer control bit: MULT3_colbuf_cntl_3 +(7 11) Column buffer control bit: MULT3_colbuf_cntl_2 +(7 12) Column buffer control bit: MULT3_colbuf_cntl_5 +(7 13) Column buffer control bit: MULT3_colbuf_cntl_4 +(7 14) Column buffer control bit: MULT3_colbuf_cntl_7 +(7 15) Column buffer control bit: MULT3_colbuf_cntl_6 +(7 8) Column buffer control bit: MULT3_colbuf_cntl_1 +(7 9) Column buffer control bit: MULT3_colbuf_cntl_0 +(8 0) routing sp4_h_l_40 <X> sp4_h_r_1 +(8 0) routing sp4_v_b_1 <X> sp4_h_r_1 +(8 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(8 1) routing sp4_h_l_36 <X> sp4_v_b_1 +(8 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(8 1) routing sp4_h_r_1 <X> sp4_v_b_1 +(8 1) routing sp4_v_t_47 <X> sp4_v_b_1 +(8 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(8 10) routing sp4_v_t_42 <X> sp4_h_l_42 +(8 11) routing sp4_h_l_42 <X> sp4_v_t_42 +(8 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(8 11) routing sp4_h_r_7 <X> sp4_v_t_42 +(8 11) routing sp4_v_b_4 <X> sp4_v_t_42 +(8 12) routing sp4_v_b_10 <X> sp4_h_r_10 +(8 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(8 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(8 13) routing sp4_h_l_47 <X> sp4_v_b_10 +(8 13) routing sp4_h_r_10 <X> sp4_v_b_10 +(8 13) routing sp4_v_t_42 <X> sp4_v_b_10 +(8 14) routing sp4_h_r_10 <X> sp4_h_l_47 +(8 14) routing sp4_h_r_2 <X> sp4_h_l_47 +(8 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(8 14) routing sp4_v_t_47 <X> sp4_h_l_47 +(8 15) routing sp4_h_l_47 <X> sp4_v_t_47 +(8 15) routing sp4_h_r_10 <X> sp4_v_t_47 +(8 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(8 15) routing sp4_v_b_7 <X> sp4_v_t_47 +(8 2) routing sp4_h_r_1 <X> sp4_h_l_36 +(8 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(8 3) routing sp4_h_l_36 <X> sp4_v_t_36 +(8 3) routing sp4_h_r_1 <X> sp4_v_t_36 +(8 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(8 3) routing sp4_v_b_10 <X> sp4_v_t_36 +(8 4) routing sp4_h_l_45 <X> sp4_h_r_4 +(8 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(8 4) routing sp4_v_b_4 <X> sp4_h_r_4 +(8 5) routing sp4_h_l_41 <X> sp4_v_b_4 +(8 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(8 5) routing sp4_h_r_4 <X> sp4_v_b_4 +(8 5) routing sp4_v_t_36 <X> sp4_v_b_4 +(8 6) routing sp4_h_r_4 <X> sp4_h_l_41 +(8 6) routing sp4_h_r_8 <X> sp4_h_l_41 +(8 6) routing sp4_v_t_41 <X> sp4_h_l_41 +(8 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(8 7) routing sp4_h_l_41 <X> sp4_v_t_41 +(8 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(8 7) routing sp4_h_r_4 <X> sp4_v_t_41 +(8 7) routing sp4_v_b_1 <X> sp4_v_t_41 +(8 8) routing sp4_h_l_46 <X> sp4_h_r_7 +(8 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(8 8) routing sp4_v_b_7 <X> sp4_h_r_7 +(8 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(8 9) routing sp4_h_l_42 <X> sp4_v_b_7 +(8 9) routing sp4_h_r_7 <X> sp4_v_b_7 +(8 9) routing sp4_v_t_41 <X> sp4_v_b_7 +(9 0) routing sp4_v_b_1 <X> sp4_h_r_1 +(9 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(9 0) routing sp4_v_t_36 <X> sp4_h_r_1 +(9 1) routing sp4_h_l_36 <X> sp4_v_b_1 +(9 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(9 1) routing sp4_v_t_36 <X> sp4_v_b_1 +(9 1) routing sp4_v_t_40 <X> sp4_v_b_1 +(9 10) routing sp4_h_r_4 <X> sp4_h_l_42 +(9 10) routing sp4_v_b_7 <X> sp4_h_l_42 +(9 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(9 10) routing sp4_v_t_42 <X> sp4_h_l_42 +(9 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(9 11) routing sp4_h_r_7 <X> sp4_v_t_42 +(9 11) routing sp4_v_b_11 <X> sp4_v_t_42 +(9 11) routing sp4_v_b_7 <X> sp4_v_t_42 +(9 12) routing sp4_h_l_42 <X> sp4_h_r_10 +(9 12) routing sp4_v_b_10 <X> sp4_h_r_10 +(9 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(9 12) routing sp4_v_t_47 <X> sp4_h_r_10 +(9 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(9 13) routing sp4_h_l_47 <X> sp4_v_b_10 +(9 13) routing sp4_v_t_39 <X> sp4_v_b_10 +(9 13) routing sp4_v_t_47 <X> sp4_v_b_10 +(9 14) routing sp4_v_b_10 <X> sp4_h_l_47 +(9 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(9 14) routing sp4_v_t_47 <X> sp4_h_l_47 +(9 15) routing sp4_h_r_10 <X> sp4_v_t_47 +(9 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(9 15) routing sp4_v_b_10 <X> sp4_v_t_47 +(9 15) routing sp4_v_b_2 <X> sp4_v_t_47 +(9 2) routing sp4_h_r_10 <X> sp4_h_l_36 +(9 2) routing sp4_v_b_1 <X> sp4_h_l_36 +(9 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(9 3) routing sp4_h_r_1 <X> sp4_v_t_36 +(9 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(9 3) routing sp4_v_b_1 <X> sp4_v_t_36 +(9 3) routing sp4_v_b_5 <X> sp4_v_t_36 +(9 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(9 4) routing sp4_v_b_4 <X> sp4_h_r_4 +(9 4) routing sp4_v_t_41 <X> sp4_h_r_4 +(9 5) routing sp4_h_l_41 <X> sp4_v_b_4 +(9 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(9 5) routing sp4_v_t_41 <X> sp4_v_b_4 +(9 5) routing sp4_v_t_45 <X> sp4_v_b_4 +(9 6) routing sp4_v_b_4 <X> sp4_h_l_41 +(9 6) routing sp4_v_t_41 <X> sp4_h_l_41 +(9 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(9 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(9 7) routing sp4_h_r_4 <X> sp4_v_t_41 +(9 7) routing sp4_v_b_4 <X> sp4_v_t_41 +(9 7) routing sp4_v_b_8 <X> sp4_v_t_41 +(9 8) routing sp4_h_l_41 <X> sp4_h_r_7 +(9 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(9 8) routing sp4_v_b_7 <X> sp4_h_r_7 +(9 8) routing sp4_v_t_42 <X> sp4_h_r_7 +(9 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(9 9) routing sp4_h_l_42 <X> sp4_v_b_7 +(9 9) routing sp4_v_t_42 <X> sp4_v_b_7 +(9 9) routing sp4_v_t_46 <X> sp4_v_b_7 diff --git a/icefuzz/cached_ipcon_5k.txt b/icefuzz/cached_ipcon_5k.txt index e69de29..6667a0a 100644 --- a/icefuzz/cached_ipcon_5k.txt +++ b/icefuzz/cached_ipcon_5k.txt @@ -0,0 +1,3471 @@ +(0 10) routing glb_netwk_2 <X> glb2local_2 +(0 10) routing glb_netwk_3 <X> glb2local_2 +(0 10) routing glb_netwk_6 <X> glb2local_2 +(0 10) routing glb_netwk_7 <X> glb2local_2 +(0 11) routing glb_netwk_1 <X> glb2local_2 +(0 11) routing glb_netwk_3 <X> glb2local_2 +(0 11) routing glb_netwk_5 <X> glb2local_2 +(0 11) routing glb_netwk_7 <X> glb2local_2 +(0 12) routing glb_netwk_2 <X> glb2local_3 +(0 12) routing glb_netwk_3 <X> glb2local_3 +(0 12) routing glb_netwk_6 <X> glb2local_3 +(0 12) routing glb_netwk_7 <X> glb2local_3 +(0 13) routing glb_netwk_1 <X> glb2local_3 +(0 13) routing glb_netwk_3 <X> glb2local_3 +(0 13) routing glb_netwk_5 <X> glb2local_3 +(0 13) routing glb_netwk_7 <X> glb2local_3 +(0 2) routing glb_netwk_2 <X> clk +(0 2) routing glb_netwk_3 <X> clk +(0 2) routing glb_netwk_6 <X> clk +(0 2) routing glb_netwk_7 <X> clk +(0 2) routing lc_trk_g2_0 <X> clk +(0 2) routing lc_trk_g3_1 <X> clk +(0 3) routing glb_netwk_1 <X> clk +(0 3) routing glb_netwk_3 <X> clk +(0 3) routing glb_netwk_5 <X> clk +(0 3) routing glb_netwk_7 <X> clk +(0 3) routing lc_trk_g1_1 <X> clk +(0 3) routing lc_trk_g3_1 <X> clk +(0 6) routing glb_netwk_2 <X> glb2local_0 +(0 6) routing glb_netwk_3 <X> glb2local_0 +(0 6) routing glb_netwk_6 <X> glb2local_0 +(0 6) routing glb_netwk_7 <X> glb2local_0 +(0 7) routing glb_netwk_1 <X> glb2local_0 +(0 7) routing glb_netwk_3 <X> glb2local_0 +(0 7) routing glb_netwk_5 <X> glb2local_0 +(0 7) routing glb_netwk_7 <X> glb2local_0 +(0 8) routing glb_netwk_2 <X> glb2local_1 +(0 8) routing glb_netwk_3 <X> glb2local_1 +(0 8) routing glb_netwk_6 <X> glb2local_1 +(0 8) routing glb_netwk_7 <X> glb2local_1 +(0 9) routing glb_netwk_1 <X> glb2local_1 +(0 9) routing glb_netwk_3 <X> glb2local_1 +(0 9) routing glb_netwk_5 <X> glb2local_1 +(0 9) routing glb_netwk_7 <X> glb2local_1 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 +(1 11) routing glb_netwk_4 <X> glb2local_2 +(1 11) routing glb_netwk_5 <X> glb2local_2 +(1 11) routing glb_netwk_6 <X> glb2local_2 +(1 11) routing glb_netwk_7 <X> glb2local_2 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 +(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 +(1 13) routing glb_netwk_4 <X> glb2local_3 +(1 13) routing glb_netwk_5 <X> glb2local_3 +(1 13) routing glb_netwk_6 <X> glb2local_3 +(1 13) routing glb_netwk_7 <X> glb2local_3 +(1 2) routing glb_netwk_4 <X> clk +(1 2) routing glb_netwk_5 <X> clk +(1 2) routing glb_netwk_6 <X> clk +(1 2) routing glb_netwk_7 <X> clk +(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 +(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 +(1 7) routing glb_netwk_4 <X> glb2local_0 +(1 7) routing glb_netwk_5 <X> glb2local_0 +(1 7) routing glb_netwk_6 <X> glb2local_0 +(1 7) routing glb_netwk_7 <X> glb2local_0 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 +(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 +(1 9) routing glb_netwk_4 <X> glb2local_1 +(1 9) routing glb_netwk_5 <X> glb2local_1 +(1 9) routing glb_netwk_6 <X> glb2local_1 +(1 9) routing glb_netwk_7 <X> glb2local_1 +(10 0) routing sp4_h_l_40 <X> sp4_h_r_1 +(10 0) routing sp4_h_l_47 <X> sp4_h_r_1 +(10 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(10 0) routing sp4_v_t_45 <X> sp4_h_r_1 +(10 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(10 1) routing sp4_h_r_8 <X> sp4_v_b_1 +(10 1) routing sp4_v_t_40 <X> sp4_v_b_1 +(10 1) routing sp4_v_t_47 <X> sp4_v_b_1 +(10 10) routing sp4_h_r_11 <X> sp4_h_l_42 +(10 10) routing sp4_h_r_4 <X> sp4_h_l_42 +(10 10) routing sp4_v_b_2 <X> sp4_h_l_42 +(10 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(10 11) routing sp4_h_l_39 <X> sp4_v_t_42 +(10 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(10 11) routing sp4_v_b_11 <X> sp4_v_t_42 +(10 11) routing sp4_v_b_4 <X> sp4_v_t_42 +(10 12) routing sp4_h_l_42 <X> sp4_h_r_10 +(10 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(10 12) routing sp4_v_t_40 <X> sp4_h_r_10 +(10 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(10 13) routing sp4_h_r_5 <X> sp4_v_b_10 +(10 13) routing sp4_v_t_39 <X> sp4_v_b_10 +(10 13) routing sp4_v_t_42 <X> sp4_v_b_10 +(10 14) routing sp4_h_r_2 <X> sp4_h_l_47 +(10 14) routing sp4_v_b_5 <X> sp4_h_l_47 +(10 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(10 15) routing sp4_h_l_40 <X> sp4_v_t_47 +(10 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(10 15) routing sp4_v_b_2 <X> sp4_v_t_47 +(10 15) routing sp4_v_b_7 <X> sp4_v_t_47 +(10 2) routing sp4_h_r_10 <X> sp4_h_l_36 +(10 2) routing sp4_h_r_5 <X> sp4_h_l_36 +(10 2) routing sp4_v_b_8 <X> sp4_h_l_36 +(10 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(10 3) routing sp4_h_l_45 <X> sp4_v_t_36 +(10 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(10 3) routing sp4_v_b_10 <X> sp4_v_t_36 +(10 3) routing sp4_v_b_5 <X> sp4_v_t_36 +(10 4) routing sp4_h_l_36 <X> sp4_h_r_4 +(10 4) routing sp4_h_l_45 <X> sp4_h_r_4 +(10 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(10 4) routing sp4_v_t_46 <X> sp4_h_r_4 +(10 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(10 5) routing sp4_h_r_11 <X> sp4_v_b_4 +(10 5) routing sp4_v_t_36 <X> sp4_v_b_4 +(10 5) routing sp4_v_t_45 <X> sp4_v_b_4 +(10 6) routing sp4_h_r_1 <X> sp4_h_l_41 +(10 6) routing sp4_h_r_8 <X> sp4_h_l_41 +(10 6) routing sp4_v_b_11 <X> sp4_h_l_41 +(10 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(10 7) routing sp4_h_l_46 <X> sp4_v_t_41 +(10 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(10 7) routing sp4_v_b_1 <X> sp4_v_t_41 +(10 7) routing sp4_v_b_8 <X> sp4_v_t_41 +(10 8) routing sp4_h_l_41 <X> sp4_h_r_7 +(10 8) routing sp4_h_l_46 <X> sp4_h_r_7 +(10 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(10 8) routing sp4_v_t_39 <X> sp4_h_r_7 +(10 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(10 9) routing sp4_h_r_2 <X> sp4_v_b_7 +(10 9) routing sp4_v_t_41 <X> sp4_v_b_7 +(10 9) routing sp4_v_t_46 <X> sp4_v_b_7 +(11 0) routing sp4_h_l_45 <X> sp4_v_b_2 +(11 0) routing sp4_h_r_9 <X> sp4_v_b_2 +(11 0) routing sp4_v_t_43 <X> sp4_v_b_2 +(11 0) routing sp4_v_t_46 <X> sp4_v_b_2 +(11 1) routing sp4_h_l_39 <X> sp4_h_r_2 +(11 1) routing sp4_h_l_43 <X> sp4_h_r_2 +(11 1) routing sp4_v_b_2 <X> sp4_h_r_2 +(11 1) routing sp4_v_b_8 <X> sp4_h_r_2 +(11 10) routing sp4_h_l_38 <X> sp4_v_t_45 +(11 10) routing sp4_h_r_2 <X> sp4_v_t_45 +(11 10) routing sp4_v_b_0 <X> sp4_v_t_45 +(11 10) routing sp4_v_b_5 <X> sp4_v_t_45 +(11 11) routing sp4_h_r_0 <X> sp4_h_l_45 +(11 11) routing sp4_h_r_8 <X> sp4_h_l_45 +(11 11) routing sp4_v_t_39 <X> sp4_h_l_45 +(11 11) routing sp4_v_t_45 <X> sp4_h_l_45 +(11 12) routing sp4_h_l_40 <X> sp4_v_b_11 +(11 12) routing sp4_h_r_6 <X> sp4_v_b_11 +(11 12) routing sp4_v_t_38 <X> sp4_v_b_11 +(11 12) routing sp4_v_t_45 <X> sp4_v_b_11 +(11 13) routing sp4_h_l_46 <X> sp4_h_r_11 +(11 13) routing sp4_v_b_11 <X> sp4_h_r_11 +(11 13) routing sp4_v_b_5 <X> sp4_h_r_11 +(11 14) routing sp4_h_l_43 <X> sp4_v_t_46 +(11 14) routing sp4_h_r_5 <X> sp4_v_t_46 +(11 14) routing sp4_v_b_3 <X> sp4_v_t_46 +(11 14) routing sp4_v_b_8 <X> sp4_v_t_46 +(11 15) routing sp4_h_r_11 <X> sp4_h_l_46 +(11 15) routing sp4_h_r_3 <X> sp4_h_l_46 +(11 15) routing sp4_v_t_40 <X> sp4_h_l_46 +(11 15) routing sp4_v_t_46 <X> sp4_h_l_46 +(11 2) routing sp4_h_l_44 <X> sp4_v_t_39 +(11 2) routing sp4_h_r_8 <X> sp4_v_t_39 +(11 2) routing sp4_v_b_11 <X> sp4_v_t_39 +(11 2) routing sp4_v_b_6 <X> sp4_v_t_39 +(11 3) routing sp4_h_r_2 <X> sp4_h_l_39 +(11 3) routing sp4_h_r_6 <X> sp4_h_l_39 +(11 3) routing sp4_v_t_39 <X> sp4_h_l_39 +(11 3) routing sp4_v_t_45 <X> sp4_h_l_39 +(11 4) routing sp4_h_l_46 <X> sp4_v_b_5 +(11 4) routing sp4_h_r_0 <X> sp4_v_b_5 +(11 4) routing sp4_v_t_39 <X> sp4_v_b_5 +(11 4) routing sp4_v_t_44 <X> sp4_v_b_5 +(11 5) routing sp4_h_l_40 <X> sp4_h_r_5 +(11 5) routing sp4_h_l_44 <X> sp4_h_r_5 +(11 5) routing sp4_v_b_11 <X> sp4_h_r_5 +(11 5) routing sp4_v_b_5 <X> sp4_h_r_5 +(11 6) routing sp4_h_l_37 <X> sp4_v_t_40 +(11 6) routing sp4_h_r_11 <X> sp4_v_t_40 +(11 6) routing sp4_v_b_2 <X> sp4_v_t_40 +(11 6) routing sp4_v_b_9 <X> sp4_v_t_40 +(11 7) routing sp4_v_t_40 <X> sp4_h_l_40 +(11 7) routing sp4_v_t_46 <X> sp4_h_l_40 +(11 8) routing sp4_h_l_39 <X> sp4_v_b_8 +(11 8) routing sp4_h_r_3 <X> sp4_v_b_8 +(11 8) routing sp4_v_t_37 <X> sp4_v_b_8 +(11 8) routing sp4_v_t_40 <X> sp4_v_b_8 +(11 9) routing sp4_h_l_37 <X> sp4_h_r_8 +(11 9) routing sp4_h_l_45 <X> sp4_h_r_8 +(11 9) routing sp4_v_b_2 <X> sp4_h_r_8 +(11 9) routing sp4_v_b_8 <X> sp4_h_r_8 +(12 0) routing sp4_h_l_46 <X> sp4_h_r_2 +(12 0) routing sp4_v_b_2 <X> sp4_h_r_2 +(12 0) routing sp4_v_b_8 <X> sp4_h_r_2 +(12 0) routing sp4_v_t_39 <X> sp4_h_r_2 +(12 1) routing sp4_h_l_39 <X> sp4_v_b_2 +(12 1) routing sp4_h_l_45 <X> sp4_v_b_2 +(12 1) routing sp4_h_r_2 <X> sp4_v_b_2 +(12 1) routing sp4_v_t_46 <X> sp4_v_b_2 +(12 10) routing sp4_v_b_8 <X> sp4_h_l_45 +(12 10) routing sp4_v_t_39 <X> sp4_h_l_45 +(12 10) routing sp4_v_t_45 <X> sp4_h_l_45 +(12 11) routing sp4_h_l_45 <X> sp4_v_t_45 +(12 11) routing sp4_h_r_2 <X> sp4_v_t_45 +(12 11) routing sp4_h_r_8 <X> sp4_v_t_45 +(12 11) routing sp4_v_b_5 <X> sp4_v_t_45 +(12 12) routing sp4_h_l_45 <X> sp4_h_r_11 +(12 12) routing sp4_v_b_11 <X> sp4_h_r_11 +(12 12) routing sp4_v_b_5 <X> sp4_h_r_11 +(12 12) routing sp4_v_t_46 <X> sp4_h_r_11 +(12 13) routing sp4_h_l_40 <X> sp4_v_b_11 +(12 13) routing sp4_h_l_46 <X> sp4_v_b_11 +(12 13) routing sp4_h_r_11 <X> sp4_v_b_11 +(12 13) routing sp4_v_t_45 <X> sp4_v_b_11 +(12 14) routing sp4_h_r_8 <X> sp4_h_l_46 +(12 14) routing sp4_v_b_11 <X> sp4_h_l_46 +(12 14) routing sp4_v_t_40 <X> sp4_h_l_46 +(12 14) routing sp4_v_t_46 <X> sp4_h_l_46 +(12 15) routing sp4_h_l_46 <X> sp4_v_t_46 +(12 15) routing sp4_h_r_11 <X> sp4_v_t_46 +(12 15) routing sp4_h_r_5 <X> sp4_v_t_46 +(12 15) routing sp4_v_b_8 <X> sp4_v_t_46 +(12 2) routing sp4_v_b_2 <X> sp4_h_l_39 +(12 2) routing sp4_v_t_39 <X> sp4_h_l_39 +(12 2) routing sp4_v_t_45 <X> sp4_h_l_39 +(12 3) routing sp4_h_l_39 <X> sp4_v_t_39 +(12 3) routing sp4_h_r_2 <X> sp4_v_t_39 +(12 3) routing sp4_h_r_8 <X> sp4_v_t_39 +(12 3) routing sp4_v_b_11 <X> sp4_v_t_39 +(12 4) routing sp4_h_l_39 <X> sp4_h_r_5 +(12 4) routing sp4_v_b_11 <X> sp4_h_r_5 +(12 4) routing sp4_v_b_5 <X> sp4_h_r_5 +(12 4) routing sp4_v_t_40 <X> sp4_h_r_5 +(12 5) routing sp4_h_l_40 <X> sp4_v_b_5 +(12 5) routing sp4_h_l_46 <X> sp4_v_b_5 +(12 5) routing sp4_h_r_5 <X> sp4_v_b_5 +(12 5) routing sp4_v_t_39 <X> sp4_v_b_5 +(12 6) routing sp4_h_r_2 <X> sp4_h_l_40 +(12 6) routing sp4_v_b_5 <X> sp4_h_l_40 +(12 6) routing sp4_v_t_40 <X> sp4_h_l_40 +(12 6) routing sp4_v_t_46 <X> sp4_h_l_40 +(12 7) routing sp4_h_l_40 <X> sp4_v_t_40 +(12 7) routing sp4_h_r_11 <X> sp4_v_t_40 +(12 7) routing sp4_h_r_5 <X> sp4_v_t_40 +(12 7) routing sp4_v_b_2 <X> sp4_v_t_40 +(12 8) routing sp4_h_l_40 <X> sp4_h_r_8 +(12 8) routing sp4_v_b_2 <X> sp4_h_r_8 +(12 8) routing sp4_v_b_8 <X> sp4_h_r_8 +(12 8) routing sp4_v_t_45 <X> sp4_h_r_8 +(12 9) routing sp4_h_l_39 <X> sp4_v_b_8 +(12 9) routing sp4_h_l_45 <X> sp4_v_b_8 +(12 9) routing sp4_h_r_8 <X> sp4_v_b_8 +(12 9) routing sp4_v_t_40 <X> sp4_v_b_8 +(13 0) routing sp4_h_l_39 <X> sp4_v_b_2 +(13 0) routing sp4_h_l_45 <X> sp4_v_b_2 +(13 0) routing sp4_v_t_39 <X> sp4_v_b_2 +(13 0) routing sp4_v_t_43 <X> sp4_v_b_2 +(13 1) routing sp4_h_l_43 <X> sp4_h_r_2 +(13 1) routing sp4_h_l_46 <X> sp4_h_r_2 +(13 1) routing sp4_v_b_8 <X> sp4_h_r_2 +(13 1) routing sp4_v_t_44 <X> sp4_h_r_2 +(13 10) routing sp4_h_r_2 <X> sp4_v_t_45 +(13 10) routing sp4_h_r_8 <X> sp4_v_t_45 +(13 10) routing sp4_v_b_0 <X> sp4_v_t_45 +(13 10) routing sp4_v_b_8 <X> sp4_v_t_45 +(13 11) routing sp4_h_r_0 <X> sp4_h_l_45 +(13 11) routing sp4_v_b_3 <X> sp4_h_l_45 +(13 11) routing sp4_v_t_39 <X> sp4_h_l_45 +(13 12) routing sp4_h_l_40 <X> sp4_v_b_11 +(13 12) routing sp4_h_l_46 <X> sp4_v_b_11 +(13 12) routing sp4_v_t_38 <X> sp4_v_b_11 +(13 12) routing sp4_v_t_46 <X> sp4_v_b_11 +(13 13) routing sp4_h_l_45 <X> sp4_h_r_11 +(13 13) routing sp4_v_b_5 <X> sp4_h_r_11 +(13 13) routing sp4_v_t_43 <X> sp4_h_r_11 +(13 14) routing sp4_h_r_11 <X> sp4_v_t_46 +(13 14) routing sp4_h_r_5 <X> sp4_v_t_46 +(13 14) routing sp4_v_b_11 <X> sp4_v_t_46 +(13 14) routing sp4_v_b_3 <X> sp4_v_t_46 +(13 15) routing sp4_h_r_3 <X> sp4_h_l_46 +(13 15) routing sp4_h_r_8 <X> sp4_h_l_46 +(13 15) routing sp4_v_b_6 <X> sp4_h_l_46 +(13 15) routing sp4_v_t_40 <X> sp4_h_l_46 +(13 2) routing sp4_h_r_2 <X> sp4_v_t_39 +(13 2) routing sp4_h_r_8 <X> sp4_v_t_39 +(13 2) routing sp4_v_b_2 <X> sp4_v_t_39 +(13 2) routing sp4_v_b_6 <X> sp4_v_t_39 +(13 3) routing sp4_h_r_6 <X> sp4_h_l_39 +(13 3) routing sp4_v_b_9 <X> sp4_h_l_39 +(13 3) routing sp4_v_t_45 <X> sp4_h_l_39 +(13 4) routing sp4_h_l_40 <X> sp4_v_b_5 +(13 4) routing sp4_h_l_46 <X> sp4_v_b_5 +(13 4) routing sp4_v_t_40 <X> sp4_v_b_5 +(13 4) routing sp4_v_t_44 <X> sp4_v_b_5 +(13 5) routing sp4_h_l_39 <X> sp4_h_r_5 +(13 5) routing sp4_h_l_44 <X> sp4_h_r_5 +(13 5) routing sp4_v_b_11 <X> sp4_h_r_5 +(13 5) routing sp4_v_t_37 <X> sp4_h_r_5 +(13 6) routing sp4_h_r_11 <X> sp4_v_t_40 +(13 6) routing sp4_h_r_5 <X> sp4_v_t_40 +(13 6) routing sp4_v_b_5 <X> sp4_v_t_40 +(13 6) routing sp4_v_b_9 <X> sp4_v_t_40 +(13 7) routing sp4_h_r_2 <X> sp4_h_l_40 +(13 7) routing sp4_v_b_0 <X> sp4_h_l_40 +(13 7) routing sp4_v_t_46 <X> sp4_h_l_40 +(13 8) routing sp4_h_l_39 <X> sp4_v_b_8 +(13 8) routing sp4_h_l_45 <X> sp4_v_b_8 +(13 8) routing sp4_v_t_37 <X> sp4_v_b_8 +(13 8) routing sp4_v_t_45 <X> sp4_v_b_8 +(13 9) routing sp4_h_l_37 <X> sp4_h_r_8 +(13 9) routing sp4_h_l_40 <X> sp4_h_r_8 +(13 9) routing sp4_v_b_2 <X> sp4_h_r_8 +(13 9) routing sp4_v_t_38 <X> sp4_h_r_8 +(14 0) routing bnr_op_0 <X> lc_trk_g0_0 +(14 0) routing lft_op_0 <X> lc_trk_g0_0 +(14 0) routing sp12_h_r_0 <X> lc_trk_g0_0 +(14 0) routing sp4_h_r_16 <X> lc_trk_g0_0 +(14 0) routing sp4_h_r_8 <X> lc_trk_g0_0 +(14 0) routing sp4_v_b_0 <X> lc_trk_g0_0 +(14 0) routing sp4_v_b_8 <X> lc_trk_g0_0 +(14 1) routing bnr_op_0 <X> lc_trk_g0_0 +(14 1) routing sp12_h_l_15 <X> lc_trk_g0_0 +(14 1) routing sp12_h_r_0 <X> lc_trk_g0_0 +(14 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(14 1) routing sp4_h_r_16 <X> lc_trk_g0_0 +(14 1) routing sp4_r_v_b_35 <X> lc_trk_g0_0 +(14 1) routing sp4_v_b_8 <X> lc_trk_g0_0 +(14 10) routing bnl_op_4 <X> lc_trk_g2_4 +(14 10) routing rgt_op_4 <X> lc_trk_g2_4 +(14 10) routing sp12_v_b_4 <X> lc_trk_g2_4 +(14 10) routing sp4_h_l_33 <X> lc_trk_g2_4 +(14 10) routing sp4_h_r_36 <X> lc_trk_g2_4 +(14 10) routing sp4_v_b_36 <X> lc_trk_g2_4 +(14 10) routing sp4_v_t_17 <X> lc_trk_g2_4 +(14 11) routing bnl_op_4 <X> lc_trk_g2_4 +(14 11) routing sp12_v_b_20 <X> lc_trk_g2_4 +(14 11) routing sp12_v_b_4 <X> lc_trk_g2_4 +(14 11) routing sp4_h_l_33 <X> lc_trk_g2_4 +(14 11) routing sp4_h_r_28 <X> lc_trk_g2_4 +(14 11) routing sp4_r_v_b_36 <X> lc_trk_g2_4 +(14 11) routing sp4_v_b_36 <X> lc_trk_g2_4 +(14 12) routing bnl_op_0 <X> lc_trk_g3_0 +(14 12) routing rgt_op_0 <X> lc_trk_g3_0 +(14 12) routing sp12_v_b_0 <X> lc_trk_g3_0 +(14 12) routing sp4_h_l_21 <X> lc_trk_g3_0 +(14 12) routing sp4_h_l_29 <X> lc_trk_g3_0 +(14 12) routing sp4_v_t_13 <X> lc_trk_g3_0 +(14 12) routing sp4_v_t_21 <X> lc_trk_g3_0 +(14 13) routing bnl_op_0 <X> lc_trk_g3_0 +(14 13) routing sp12_v_b_0 <X> lc_trk_g3_0 +(14 13) routing sp12_v_b_16 <X> lc_trk_g3_0 +(14 13) routing sp4_h_l_29 <X> lc_trk_g3_0 +(14 13) routing sp4_h_r_24 <X> lc_trk_g3_0 +(14 13) routing sp4_r_v_b_40 <X> lc_trk_g3_0 +(14 13) routing sp4_v_t_21 <X> lc_trk_g3_0 +(14 13) routing tnl_op_0 <X> lc_trk_g3_0 +(14 14) routing bnl_op_4 <X> lc_trk_g3_4 +(14 14) routing rgt_op_4 <X> lc_trk_g3_4 +(14 14) routing slf_op_4 <X> lc_trk_g3_4 +(14 14) routing sp12_v_b_4 <X> lc_trk_g3_4 +(14 14) routing sp4_h_l_33 <X> lc_trk_g3_4 +(14 14) routing sp4_h_r_36 <X> lc_trk_g3_4 +(14 14) routing sp4_v_b_36 <X> lc_trk_g3_4 +(14 14) routing sp4_v_t_17 <X> lc_trk_g3_4 +(14 15) routing bnl_op_4 <X> lc_trk_g3_4 +(14 15) routing sp12_v_b_20 <X> lc_trk_g3_4 +(14 15) routing sp12_v_b_4 <X> lc_trk_g3_4 +(14 15) routing sp4_h_l_33 <X> lc_trk_g3_4 +(14 15) routing sp4_h_r_28 <X> lc_trk_g3_4 +(14 15) routing sp4_r_v_b_44 <X> lc_trk_g3_4 +(14 15) routing sp4_v_b_36 <X> lc_trk_g3_4 +(14 2) routing bnr_op_4 <X> lc_trk_g0_4 +(14 2) routing lft_op_4 <X> lc_trk_g0_4 +(14 2) routing sp12_h_r_4 <X> lc_trk_g0_4 +(14 2) routing sp4_h_l_1 <X> lc_trk_g0_4 +(14 2) routing sp4_h_r_20 <X> lc_trk_g0_4 +(14 2) routing sp4_v_b_12 <X> lc_trk_g0_4 +(14 2) routing sp4_v_b_4 <X> lc_trk_g0_4 +(14 3) routing bnr_op_4 <X> lc_trk_g0_4 +(14 3) routing sp12_h_r_20 <X> lc_trk_g0_4 +(14 3) routing sp12_h_r_4 <X> lc_trk_g0_4 +(14 3) routing sp4_h_r_20 <X> lc_trk_g0_4 +(14 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(14 3) routing sp4_r_v_b_28 <X> lc_trk_g0_4 +(14 3) routing sp4_v_b_12 <X> lc_trk_g0_4 +(14 4) routing bnr_op_0 <X> lc_trk_g1_0 +(14 4) routing lft_op_0 <X> lc_trk_g1_0 +(14 4) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 4) routing sp4_h_r_16 <X> lc_trk_g1_0 +(14 4) routing sp4_h_r_8 <X> lc_trk_g1_0 +(14 4) routing sp4_v_b_0 <X> lc_trk_g1_0 +(14 4) routing sp4_v_b_8 <X> lc_trk_g1_0 +(14 5) routing bnr_op_0 <X> lc_trk_g1_0 +(14 5) routing sp12_h_l_15 <X> lc_trk_g1_0 +(14 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(14 5) routing sp4_h_r_16 <X> lc_trk_g1_0 +(14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0 +(14 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(14 5) routing top_op_0 <X> lc_trk_g1_0 +(14 6) routing bnr_op_4 <X> lc_trk_g1_4 +(14 6) routing lft_op_4 <X> lc_trk_g1_4 +(14 6) routing sp12_h_r_4 <X> lc_trk_g1_4 +(14 6) routing sp4_h_l_1 <X> lc_trk_g1_4 +(14 6) routing sp4_h_r_20 <X> lc_trk_g1_4 +(14 6) routing sp4_v_b_12 <X> lc_trk_g1_4 +(14 6) routing sp4_v_b_4 <X> lc_trk_g1_4 +(14 7) routing bnr_op_4 <X> lc_trk_g1_4 +(14 7) routing sp12_h_r_20 <X> lc_trk_g1_4 +(14 7) routing sp12_h_r_4 <X> lc_trk_g1_4 +(14 7) routing sp4_h_r_20 <X> lc_trk_g1_4 +(14 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4 +(14 7) routing sp4_v_b_12 <X> lc_trk_g1_4 +(14 8) routing bnl_op_0 <X> lc_trk_g2_0 +(14 8) routing rgt_op_0 <X> lc_trk_g2_0 +(14 8) routing slf_op_0 <X> lc_trk_g2_0 +(14 8) routing sp12_v_b_0 <X> lc_trk_g2_0 +(14 8) routing sp4_h_l_21 <X> lc_trk_g2_0 +(14 8) routing sp4_h_l_29 <X> lc_trk_g2_0 +(14 8) routing sp4_v_t_13 <X> lc_trk_g2_0 +(14 8) routing sp4_v_t_21 <X> lc_trk_g2_0 +(14 9) routing bnl_op_0 <X> lc_trk_g2_0 +(14 9) routing sp12_v_b_0 <X> lc_trk_g2_0 +(14 9) routing sp12_v_b_16 <X> lc_trk_g2_0 +(14 9) routing sp4_h_l_29 <X> lc_trk_g2_0 +(14 9) routing sp4_h_r_24 <X> lc_trk_g2_0 +(14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0 +(14 9) routing sp4_v_t_21 <X> lc_trk_g2_0 +(14 9) routing tnl_op_0 <X> lc_trk_g2_0 +(15 0) routing lft_op_1 <X> lc_trk_g0_1 +(15 0) routing sp12_h_r_1 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_1 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(15 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(15 0) routing sp4_v_b_17 <X> lc_trk_g0_1 +(15 0) routing top_op_1 <X> lc_trk_g0_1 +(15 1) routing lft_op_0 <X> lc_trk_g0_0 +(15 1) routing sp12_h_r_0 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_16 <X> lc_trk_g0_0 +(15 1) routing sp4_h_r_8 <X> lc_trk_g0_0 +(15 1) routing sp4_v_t_5 <X> lc_trk_g0_0 +(15 10) routing rgt_op_5 <X> lc_trk_g2_5 +(15 10) routing sp12_v_b_5 <X> lc_trk_g2_5 +(15 10) routing sp4_h_l_16 <X> lc_trk_g2_5 +(15 10) routing sp4_h_r_37 <X> lc_trk_g2_5 +(15 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(15 10) routing sp4_v_b_45 <X> lc_trk_g2_5 +(15 11) routing rgt_op_4 <X> lc_trk_g2_4 +(15 11) routing sp12_v_b_4 <X> lc_trk_g2_4 +(15 11) routing sp4_h_l_33 <X> lc_trk_g2_4 +(15 11) routing sp4_h_r_28 <X> lc_trk_g2_4 +(15 11) routing sp4_h_r_36 <X> lc_trk_g2_4 +(15 11) routing sp4_v_t_33 <X> lc_trk_g2_4 +(15 11) routing tnr_op_4 <X> lc_trk_g2_4 +(15 12) routing rgt_op_1 <X> lc_trk_g3_1 +(15 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(15 12) routing sp4_h_l_28 <X> lc_trk_g3_1 +(15 12) routing sp4_h_r_25 <X> lc_trk_g3_1 +(15 12) routing sp4_h_r_33 <X> lc_trk_g3_1 +(15 12) routing sp4_v_b_41 <X> lc_trk_g3_1 +(15 13) routing rgt_op_0 <X> lc_trk_g3_0 +(15 13) routing sp12_v_b_0 <X> lc_trk_g3_0 +(15 13) routing sp4_h_l_21 <X> lc_trk_g3_0 +(15 13) routing sp4_h_l_29 <X> lc_trk_g3_0 +(15 13) routing sp4_h_r_24 <X> lc_trk_g3_0 +(15 13) routing sp4_v_b_40 <X> lc_trk_g3_0 +(15 13) routing tnl_op_0 <X> lc_trk_g3_0 +(15 13) routing tnr_op_0 <X> lc_trk_g3_0 +(15 14) routing rgt_op_5 <X> lc_trk_g3_5 +(15 14) routing sp12_v_b_5 <X> lc_trk_g3_5 +(15 14) routing sp4_h_l_16 <X> lc_trk_g3_5 +(15 14) routing sp4_h_r_37 <X> lc_trk_g3_5 +(15 14) routing sp4_h_r_45 <X> lc_trk_g3_5 +(15 14) routing sp4_v_b_45 <X> lc_trk_g3_5 +(15 14) routing tnl_op_5 <X> lc_trk_g3_5 +(15 14) routing tnr_op_5 <X> lc_trk_g3_5 +(15 15) routing rgt_op_4 <X> lc_trk_g3_4 +(15 15) routing sp12_v_b_4 <X> lc_trk_g3_4 +(15 15) routing sp4_h_l_33 <X> lc_trk_g3_4 +(15 15) routing sp4_h_r_28 <X> lc_trk_g3_4 +(15 15) routing sp4_h_r_36 <X> lc_trk_g3_4 +(15 15) routing sp4_v_t_33 <X> lc_trk_g3_4 +(15 2) routing lft_op_5 <X> lc_trk_g0_5 +(15 2) routing sp12_h_r_5 <X> lc_trk_g0_5 +(15 2) routing sp4_h_l_8 <X> lc_trk_g0_5 +(15 2) routing sp4_h_r_13 <X> lc_trk_g0_5 +(15 2) routing sp4_h_r_5 <X> lc_trk_g0_5 +(15 2) routing sp4_v_t_8 <X> lc_trk_g0_5 +(15 3) routing bot_op_4 <X> lc_trk_g0_4 +(15 3) routing lft_op_4 <X> lc_trk_g0_4 +(15 3) routing sp12_h_r_4 <X> lc_trk_g0_4 +(15 3) routing sp4_h_l_1 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_20 <X> lc_trk_g0_4 +(15 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(15 3) routing sp4_v_t_9 <X> lc_trk_g0_4 +(15 4) routing bot_op_1 <X> lc_trk_g1_1 +(15 4) routing lft_op_1 <X> lc_trk_g1_1 +(15 4) routing sp12_h_r_1 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_1 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(15 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(15 4) routing sp4_v_b_17 <X> lc_trk_g1_1 +(15 5) routing bot_op_0 <X> lc_trk_g1_0 +(15 5) routing lft_op_0 <X> lc_trk_g1_0 +(15 5) routing sp12_h_r_0 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_16 <X> lc_trk_g1_0 +(15 5) routing sp4_h_r_8 <X> lc_trk_g1_0 +(15 5) routing sp4_v_t_5 <X> lc_trk_g1_0 +(15 5) routing top_op_0 <X> lc_trk_g1_0 +(15 6) routing bot_op_5 <X> lc_trk_g1_5 +(15 6) routing lft_op_5 <X> lc_trk_g1_5 +(15 6) routing sp12_h_r_5 <X> lc_trk_g1_5 +(15 6) routing sp4_h_l_8 <X> lc_trk_g1_5 +(15 6) routing sp4_h_r_13 <X> lc_trk_g1_5 +(15 6) routing sp4_h_r_5 <X> lc_trk_g1_5 +(15 6) routing sp4_v_t_8 <X> lc_trk_g1_5 +(15 6) routing top_op_5 <X> lc_trk_g1_5 +(15 7) routing bot_op_4 <X> lc_trk_g1_4 +(15 7) routing lft_op_4 <X> lc_trk_g1_4 +(15 7) routing sp12_h_r_4 <X> lc_trk_g1_4 +(15 7) routing sp4_h_l_1 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_20 <X> lc_trk_g1_4 +(15 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(15 7) routing sp4_v_t_9 <X> lc_trk_g1_4 +(15 8) routing rgt_op_1 <X> lc_trk_g2_1 +(15 8) routing sp12_v_b_1 <X> lc_trk_g2_1 +(15 8) routing sp4_h_l_28 <X> lc_trk_g2_1 +(15 8) routing sp4_h_r_25 <X> lc_trk_g2_1 +(15 8) routing sp4_h_r_33 <X> lc_trk_g2_1 +(15 8) routing sp4_v_b_41 <X> lc_trk_g2_1 +(15 8) routing tnl_op_1 <X> lc_trk_g2_1 +(15 8) routing tnr_op_1 <X> lc_trk_g2_1 +(15 9) routing rgt_op_0 <X> lc_trk_g2_0 +(15 9) routing sp12_v_b_0 <X> lc_trk_g2_0 +(15 9) routing sp4_h_l_21 <X> lc_trk_g2_0 +(15 9) routing sp4_h_l_29 <X> lc_trk_g2_0 +(15 9) routing sp4_h_r_24 <X> lc_trk_g2_0 +(15 9) routing sp4_v_b_40 <X> lc_trk_g2_0 +(15 9) routing tnl_op_0 <X> lc_trk_g2_0 +(16 0) routing sp12_h_r_17 <X> lc_trk_g0_1 +(16 0) routing sp12_h_r_9 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_1 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(16 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_1 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_17 <X> lc_trk_g0_1 +(16 0) routing sp4_v_b_9 <X> lc_trk_g0_1 +(16 1) routing sp12_h_l_15 <X> lc_trk_g0_0 +(16 1) routing sp12_h_l_7 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_0 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_16 <X> lc_trk_g0_0 +(16 1) routing sp4_h_r_8 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_0 <X> lc_trk_g0_0 +(16 1) routing sp4_v_b_8 <X> lc_trk_g0_0 +(16 1) routing sp4_v_t_5 <X> lc_trk_g0_0 +(16 10) routing sp12_v_b_21 <X> lc_trk_g2_5 +(16 10) routing sp12_v_t_10 <X> lc_trk_g2_5 +(16 10) routing sp4_h_l_16 <X> lc_trk_g2_5 +(16 10) routing sp4_h_r_37 <X> lc_trk_g2_5 +(16 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_29 <X> lc_trk_g2_5 +(16 10) routing sp4_v_b_45 <X> lc_trk_g2_5 +(16 10) routing sp4_v_t_24 <X> lc_trk_g2_5 +(16 11) routing sp12_v_b_12 <X> lc_trk_g2_4 +(16 11) routing sp12_v_b_20 <X> lc_trk_g2_4 +(16 11) routing sp4_h_l_33 <X> lc_trk_g2_4 +(16 11) routing sp4_h_r_28 <X> lc_trk_g2_4 +(16 11) routing sp4_h_r_36 <X> lc_trk_g2_4 +(16 11) routing sp4_v_b_36 <X> lc_trk_g2_4 +(16 11) routing sp4_v_t_17 <X> lc_trk_g2_4 +(16 11) routing sp4_v_t_33 <X> lc_trk_g2_4 +(16 12) routing sp12_v_b_9 <X> lc_trk_g3_1 +(16 12) routing sp12_v_t_14 <X> lc_trk_g3_1 +(16 12) routing sp4_h_l_28 <X> lc_trk_g3_1 +(16 12) routing sp4_h_r_25 <X> lc_trk_g3_1 +(16 12) routing sp4_h_r_33 <X> lc_trk_g3_1 +(16 12) routing sp4_v_b_33 <X> lc_trk_g3_1 +(16 12) routing sp4_v_b_41 <X> lc_trk_g3_1 +(16 12) routing sp4_v_t_12 <X> lc_trk_g3_1 +(16 13) routing sp12_v_b_16 <X> lc_trk_g3_0 +(16 13) routing sp12_v_t_7 <X> lc_trk_g3_0 +(16 13) routing sp4_h_l_21 <X> lc_trk_g3_0 +(16 13) routing sp4_h_l_29 <X> lc_trk_g3_0 +(16 13) routing sp4_h_r_24 <X> lc_trk_g3_0 +(16 13) routing sp4_v_b_40 <X> lc_trk_g3_0 +(16 13) routing sp4_v_t_13 <X> lc_trk_g3_0 +(16 13) routing sp4_v_t_21 <X> lc_trk_g3_0 +(16 14) routing sp12_v_b_21 <X> lc_trk_g3_5 +(16 14) routing sp12_v_t_10 <X> lc_trk_g3_5 +(16 14) routing sp4_h_l_16 <X> lc_trk_g3_5 +(16 14) routing sp4_h_r_37 <X> lc_trk_g3_5 +(16 14) routing sp4_h_r_45 <X> lc_trk_g3_5 +(16 14) routing sp4_v_b_29 <X> lc_trk_g3_5 +(16 14) routing sp4_v_b_45 <X> lc_trk_g3_5 +(16 14) routing sp4_v_t_24 <X> lc_trk_g3_5 +(16 15) routing sp12_v_b_12 <X> lc_trk_g3_4 +(16 15) routing sp12_v_b_20 <X> lc_trk_g3_4 +(16 15) routing sp4_h_l_33 <X> lc_trk_g3_4 +(16 15) routing sp4_h_r_28 <X> lc_trk_g3_4 +(16 15) routing sp4_h_r_36 <X> lc_trk_g3_4 +(16 15) routing sp4_v_b_36 <X> lc_trk_g3_4 +(16 15) routing sp4_v_t_17 <X> lc_trk_g3_4 +(16 15) routing sp4_v_t_33 <X> lc_trk_g3_4 +(16 2) routing sp12_h_l_10 <X> lc_trk_g0_5 +(16 2) routing sp12_h_r_21 <X> lc_trk_g0_5 +(16 2) routing sp4_h_l_8 <X> lc_trk_g0_5 +(16 2) routing sp4_h_r_13 <X> lc_trk_g0_5 +(16 2) routing sp4_h_r_5 <X> lc_trk_g0_5 +(16 2) routing sp4_v_b_5 <X> lc_trk_g0_5 +(16 2) routing sp4_v_t_0 <X> lc_trk_g0_5 +(16 2) routing sp4_v_t_8 <X> lc_trk_g0_5 +(16 3) routing sp12_h_l_11 <X> lc_trk_g0_4 +(16 3) routing sp12_h_r_20 <X> lc_trk_g0_4 +(16 3) routing sp4_h_l_1 <X> lc_trk_g0_4 +(16 3) routing sp4_h_r_20 <X> lc_trk_g0_4 +(16 3) routing sp4_h_r_4 <X> lc_trk_g0_4 +(16 3) routing sp4_v_b_12 <X> lc_trk_g0_4 +(16 3) routing sp4_v_b_4 <X> lc_trk_g0_4 +(16 3) routing sp4_v_t_9 <X> lc_trk_g0_4 +(16 4) routing sp12_h_r_17 <X> lc_trk_g1_1 +(16 4) routing sp12_h_r_9 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_1 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(16 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_1 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_17 <X> lc_trk_g1_1 +(16 4) routing sp4_v_b_9 <X> lc_trk_g1_1 +(16 5) routing sp12_h_l_15 <X> lc_trk_g1_0 +(16 5) routing sp12_h_l_7 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_0 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_16 <X> lc_trk_g1_0 +(16 5) routing sp4_h_r_8 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_0 <X> lc_trk_g1_0 +(16 5) routing sp4_v_b_8 <X> lc_trk_g1_0 +(16 5) routing sp4_v_t_5 <X> lc_trk_g1_0 +(16 6) routing sp12_h_l_10 <X> lc_trk_g1_5 +(16 6) routing sp12_h_r_21 <X> lc_trk_g1_5 +(16 6) routing sp4_h_l_8 <X> lc_trk_g1_5 +(16 6) routing sp4_h_r_13 <X> lc_trk_g1_5 +(16 6) routing sp4_h_r_5 <X> lc_trk_g1_5 +(16 6) routing sp4_v_b_5 <X> lc_trk_g1_5 +(16 6) routing sp4_v_t_0 <X> lc_trk_g1_5 +(16 6) routing sp4_v_t_8 <X> lc_trk_g1_5 +(16 7) routing sp12_h_l_11 <X> lc_trk_g1_4 +(16 7) routing sp12_h_r_20 <X> lc_trk_g1_4 +(16 7) routing sp4_h_l_1 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_20 <X> lc_trk_g1_4 +(16 7) routing sp4_h_r_4 <X> lc_trk_g1_4 +(16 7) routing sp4_v_b_12 <X> lc_trk_g1_4 +(16 7) routing sp4_v_b_4 <X> lc_trk_g1_4 +(16 7) routing sp4_v_t_9 <X> lc_trk_g1_4 +(16 8) routing sp12_v_b_9 <X> lc_trk_g2_1 +(16 8) routing sp12_v_t_14 <X> lc_trk_g2_1 +(16 8) routing sp4_h_l_28 <X> lc_trk_g2_1 +(16 8) routing sp4_h_r_25 <X> lc_trk_g2_1 +(16 8) routing sp4_h_r_33 <X> lc_trk_g2_1 +(16 8) routing sp4_v_b_33 <X> lc_trk_g2_1 +(16 8) routing sp4_v_b_41 <X> lc_trk_g2_1 +(16 8) routing sp4_v_t_12 <X> lc_trk_g2_1 +(16 9) routing sp12_v_b_16 <X> lc_trk_g2_0 +(16 9) routing sp12_v_t_7 <X> lc_trk_g2_0 +(16 9) routing sp4_h_l_21 <X> lc_trk_g2_0 +(16 9) routing sp4_h_l_29 <X> lc_trk_g2_0 +(16 9) routing sp4_h_r_24 <X> lc_trk_g2_0 +(16 9) routing sp4_v_b_40 <X> lc_trk_g2_0 +(16 9) routing sp4_v_t_13 <X> lc_trk_g2_0 +(16 9) routing sp4_v_t_21 <X> lc_trk_g2_0 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 +(17 0) Enable bit of Mux _local_links/g0_mux_1 => top_op_1 lc_trk_g0_1 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_7 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_16 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 +(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_t_5 lc_trk_g0_0 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 +(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_24 lc_trk_g2_5 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_4 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_33 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_28 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_36 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_17 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_33 lc_trk_g2_4 +(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => slf_op_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_33 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_33 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 +(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_12 lc_trk_g3_1 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_29 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_24 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_21 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 +(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_24 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 +(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => slf_op_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_4 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_33 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_28 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_36 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_17 lc_trk_g3_4 +(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_33 lc_trk_g3_4 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_8 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_0 lc_trk_g0_5 +(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => bot_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_11 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_1 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_12 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 +(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_9 lc_trk_g0_4 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => bot_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1 +(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => bot_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_7 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_t_5 lc_trk_g1_0 +(17 5) Enable bit of Mux _local_links/g1_mux_0 => top_op_0 lc_trk_g1_0 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => bot_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_0 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 +(17 6) Enable bit of Mux _local_links/g1_mux_5 => top_op_5 lc_trk_g1_5 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => bot_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_11 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_1 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_12 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 +(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_9 lc_trk_g1_4 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_33 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_12 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 +(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => slf_op_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_21 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_29 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0 +(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 +(18 0) routing bnr_op_1 <X> lc_trk_g0_1 +(18 0) routing lft_op_1 <X> lc_trk_g0_1 +(18 0) routing sp12_h_r_1 <X> lc_trk_g0_1 +(18 0) routing sp4_h_r_17 <X> lc_trk_g0_1 +(18 0) routing sp4_h_r_9 <X> lc_trk_g0_1 +(18 0) routing sp4_v_b_1 <X> lc_trk_g0_1 +(18 0) routing sp4_v_b_9 <X> lc_trk_g0_1 +(18 1) routing bnr_op_1 <X> lc_trk_g0_1 +(18 1) routing sp12_h_r_1 <X> lc_trk_g0_1 +(18 1) routing sp12_h_r_17 <X> lc_trk_g0_1 +(18 1) routing sp4_h_r_1 <X> lc_trk_g0_1 +(18 1) routing sp4_h_r_17 <X> lc_trk_g0_1 +(18 1) routing sp4_r_v_b_34 <X> lc_trk_g0_1 +(18 1) routing sp4_v_b_9 <X> lc_trk_g0_1 +(18 1) routing top_op_1 <X> lc_trk_g0_1 +(18 10) routing bnl_op_5 <X> lc_trk_g2_5 +(18 10) routing rgt_op_5 <X> lc_trk_g2_5 +(18 10) routing sp12_v_b_5 <X> lc_trk_g2_5 +(18 10) routing sp4_h_r_37 <X> lc_trk_g2_5 +(18 10) routing sp4_h_r_45 <X> lc_trk_g2_5 +(18 10) routing sp4_v_b_29 <X> lc_trk_g2_5 +(18 10) routing sp4_v_t_24 <X> lc_trk_g2_5 +(18 11) routing bnl_op_5 <X> lc_trk_g2_5 +(18 11) routing sp12_v_b_21 <X> lc_trk_g2_5 +(18 11) routing sp12_v_b_5 <X> lc_trk_g2_5 +(18 11) routing sp4_h_l_16 <X> lc_trk_g2_5 +(18 11) routing sp4_h_r_45 <X> lc_trk_g2_5 +(18 11) routing sp4_r_v_b_37 <X> lc_trk_g2_5 +(18 11) routing sp4_v_t_24 <X> lc_trk_g2_5 +(18 12) routing bnl_op_1 <X> lc_trk_g3_1 +(18 12) routing rgt_op_1 <X> lc_trk_g3_1 +(18 12) routing slf_op_1 <X> lc_trk_g3_1 +(18 12) routing sp12_v_b_1 <X> lc_trk_g3_1 +(18 12) routing sp4_h_l_28 <X> lc_trk_g3_1 +(18 12) routing sp4_h_r_33 <X> lc_trk_g3_1 +(18 12) routing sp4_v_b_33 <X> lc_trk_g3_1 +(18 12) routing sp4_v_t_12 <X> lc_trk_g3_1 +(18 13) routing bnl_op_1 <X> lc_trk_g3_1 +(18 13) routing sp12_v_b_1 <X> lc_trk_g3_1 +(18 13) routing sp12_v_t_14 <X> lc_trk_g3_1 +(18 13) routing sp4_h_l_28 <X> lc_trk_g3_1 +(18 13) routing sp4_h_r_25 <X> lc_trk_g3_1 +(18 13) routing sp4_r_v_b_41 <X> lc_trk_g3_1 +(18 13) routing sp4_v_b_33 <X> lc_trk_g3_1 +(18 14) routing bnl_op_5 <X> lc_trk_g3_5 +(18 14) routing rgt_op_5 <X> lc_trk_g3_5 +(18 14) routing sp12_v_b_5 <X> lc_trk_g3_5 +(18 14) routing sp4_h_r_37 <X> lc_trk_g3_5 +(18 14) routing sp4_h_r_45 <X> lc_trk_g3_5 +(18 14) routing sp4_v_b_29 <X> lc_trk_g3_5 +(18 14) routing sp4_v_t_24 <X> lc_trk_g3_5 +(18 15) routing bnl_op_5 <X> lc_trk_g3_5 +(18 15) routing sp12_v_b_21 <X> lc_trk_g3_5 +(18 15) routing sp12_v_b_5 <X> lc_trk_g3_5 +(18 15) routing sp4_h_l_16 <X> lc_trk_g3_5 +(18 15) routing sp4_h_r_45 <X> lc_trk_g3_5 +(18 15) routing sp4_r_v_b_45 <X> lc_trk_g3_5 +(18 15) routing sp4_v_t_24 <X> lc_trk_g3_5 +(18 15) routing tnl_op_5 <X> lc_trk_g3_5 +(18 2) routing bnr_op_5 <X> lc_trk_g0_5 +(18 2) routing lft_op_5 <X> lc_trk_g0_5 +(18 2) routing sp12_h_r_5 <X> lc_trk_g0_5 +(18 2) routing sp4_h_l_8 <X> lc_trk_g0_5 +(18 2) routing sp4_h_r_13 <X> lc_trk_g0_5 +(18 2) routing sp4_v_b_5 <X> lc_trk_g0_5 +(18 2) routing sp4_v_t_0 <X> lc_trk_g0_5 +(18 3) routing bnr_op_5 <X> lc_trk_g0_5 +(18 3) routing sp12_h_r_21 <X> lc_trk_g0_5 +(18 3) routing sp12_h_r_5 <X> lc_trk_g0_5 +(18 3) routing sp4_h_l_8 <X> lc_trk_g0_5 +(18 3) routing sp4_h_r_5 <X> lc_trk_g0_5 +(18 3) routing sp4_r_v_b_29 <X> lc_trk_g0_5 +(18 3) routing sp4_v_t_0 <X> lc_trk_g0_5 +(18 4) routing bnr_op_1 <X> lc_trk_g1_1 +(18 4) routing lft_op_1 <X> lc_trk_g1_1 +(18 4) routing sp12_h_r_1 <X> lc_trk_g1_1 +(18 4) routing sp4_h_r_17 <X> lc_trk_g1_1 +(18 4) routing sp4_h_r_9 <X> lc_trk_g1_1 +(18 4) routing sp4_v_b_1 <X> lc_trk_g1_1 +(18 4) routing sp4_v_b_9 <X> lc_trk_g1_1 +(18 5) routing bnr_op_1 <X> lc_trk_g1_1 +(18 5) routing sp12_h_r_1 <X> lc_trk_g1_1 +(18 5) routing sp12_h_r_17 <X> lc_trk_g1_1 +(18 5) routing sp4_h_r_1 <X> lc_trk_g1_1 +(18 5) routing sp4_h_r_17 <X> lc_trk_g1_1 +(18 5) routing sp4_r_v_b_25 <X> lc_trk_g1_1 +(18 5) routing sp4_v_b_9 <X> lc_trk_g1_1 +(18 6) routing bnr_op_5 <X> lc_trk_g1_5 +(18 6) routing lft_op_5 <X> lc_trk_g1_5 +(18 6) routing sp12_h_r_5 <X> lc_trk_g1_5 +(18 6) routing sp4_h_l_8 <X> lc_trk_g1_5 +(18 6) routing sp4_h_r_13 <X> lc_trk_g1_5 +(18 6) routing sp4_v_b_5 <X> lc_trk_g1_5 +(18 6) routing sp4_v_t_0 <X> lc_trk_g1_5 +(18 7) routing bnr_op_5 <X> lc_trk_g1_5 +(18 7) routing sp12_h_r_21 <X> lc_trk_g1_5 +(18 7) routing sp12_h_r_5 <X> lc_trk_g1_5 +(18 7) routing sp4_h_l_8 <X> lc_trk_g1_5 +(18 7) routing sp4_h_r_5 <X> lc_trk_g1_5 +(18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5 +(18 7) routing sp4_v_t_0 <X> lc_trk_g1_5 +(18 7) routing top_op_5 <X> lc_trk_g1_5 +(18 8) routing bnl_op_1 <X> lc_trk_g2_1 +(18 8) routing rgt_op_1 <X> lc_trk_g2_1 +(18 8) routing sp12_v_b_1 <X> lc_trk_g2_1 +(18 8) routing sp4_h_l_28 <X> lc_trk_g2_1 +(18 8) routing sp4_h_r_33 <X> lc_trk_g2_1 +(18 8) routing sp4_v_b_33 <X> lc_trk_g2_1 +(18 8) routing sp4_v_t_12 <X> lc_trk_g2_1 +(18 9) routing bnl_op_1 <X> lc_trk_g2_1 +(18 9) routing sp12_v_b_1 <X> lc_trk_g2_1 +(18 9) routing sp12_v_t_14 <X> lc_trk_g2_1 +(18 9) routing sp4_h_l_28 <X> lc_trk_g2_1 +(18 9) routing sp4_h_r_25 <X> lc_trk_g2_1 +(18 9) routing sp4_r_v_b_33 <X> lc_trk_g2_1 +(18 9) routing sp4_v_b_33 <X> lc_trk_g2_1 +(18 9) routing tnl_op_1 <X> lc_trk_g2_1 +(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_b_3 sp4_v_t_0 +(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_b_12 +(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_b_23 +(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_b_22 +(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_l_1 sp4_h_r_13 +(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_l_1 +(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_l_2 +(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_r_4 sp4_h_l_3 +(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_t_4 sp4_v_b_15 +(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_t_3 +(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_b_11 sp4_v_b_17 +(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_t_5 +(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_t_6 +(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_b_18 +(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_b_19 sp4_v_t_8 +(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_t_9 +(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_l_7 sp4_h_r_16 +(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_l_8 +(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_l_11 +(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_l_10 +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 clk +(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 clk +(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 clk +(2 3) routing lc_trk_g0_0 <X> clk +(2 3) routing lc_trk_g1_1 <X> clk +(2 3) routing lc_trk_g2_0 <X> clk +(2 3) routing lc_trk_g3_1 <X> clk +(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_l_11 sp4_h_l_7 +(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_r_14 sp4_h_r_19 +(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_l_15 sp4_h_r_20 +(21 0) routing bnr_op_3 <X> lc_trk_g0_3 +(21 0) routing lft_op_3 <X> lc_trk_g0_3 +(21 0) routing slf_op_3 <X> lc_trk_g0_3 +(21 0) routing sp12_h_r_3 <X> lc_trk_g0_3 +(21 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(21 0) routing sp4_h_r_19 <X> lc_trk_g0_3 +(21 0) routing sp4_v_b_11 <X> lc_trk_g0_3 +(21 0) routing sp4_v_b_3 <X> lc_trk_g0_3 +(21 1) routing bnr_op_3 <X> lc_trk_g0_3 +(21 1) routing sp12_h_l_16 <X> lc_trk_g0_3 +(21 1) routing sp12_h_r_3 <X> lc_trk_g0_3 +(21 1) routing sp4_h_r_19 <X> lc_trk_g0_3 +(21 1) routing sp4_h_r_3 <X> lc_trk_g0_3 +(21 1) routing sp4_r_v_b_32 <X> lc_trk_g0_3 +(21 1) routing sp4_v_b_11 <X> lc_trk_g0_3 +(21 10) routing bnl_op_7 <X> lc_trk_g2_7 +(21 10) routing rgt_op_7 <X> lc_trk_g2_7 +(21 10) routing slf_op_7 <X> lc_trk_g2_7 +(21 10) routing sp12_v_t_4 <X> lc_trk_g2_7 +(21 10) routing sp4_h_l_26 <X> lc_trk_g2_7 +(21 10) routing sp4_h_l_34 <X> lc_trk_g2_7 +(21 10) routing sp4_v_b_39 <X> lc_trk_g2_7 +(21 10) routing sp4_v_t_18 <X> lc_trk_g2_7 +(21 11) routing bnl_op_7 <X> lc_trk_g2_7 +(21 11) routing sp12_v_b_23 <X> lc_trk_g2_7 +(21 11) routing sp12_v_t_4 <X> lc_trk_g2_7 +(21 11) routing sp4_h_l_34 <X> lc_trk_g2_7 +(21 11) routing sp4_h_r_31 <X> lc_trk_g2_7 +(21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7 +(21 11) routing sp4_v_b_39 <X> lc_trk_g2_7 +(21 12) routing bnl_op_3 <X> lc_trk_g3_3 +(21 12) routing rgt_op_3 <X> lc_trk_g3_3 +(21 12) routing sp12_v_b_3 <X> lc_trk_g3_3 +(21 12) routing sp4_h_r_35 <X> lc_trk_g3_3 +(21 12) routing sp4_h_r_43 <X> lc_trk_g3_3 +(21 12) routing sp4_v_b_27 <X> lc_trk_g3_3 +(21 12) routing sp4_v_t_22 <X> lc_trk_g3_3 +(21 13) routing bnl_op_3 <X> lc_trk_g3_3 +(21 13) routing sp12_v_b_19 <X> lc_trk_g3_3 +(21 13) routing sp12_v_b_3 <X> lc_trk_g3_3 +(21 13) routing sp4_h_l_14 <X> lc_trk_g3_3 +(21 13) routing sp4_h_r_43 <X> lc_trk_g3_3 +(21 13) routing sp4_r_v_b_43 <X> lc_trk_g3_3 +(21 13) routing sp4_v_t_22 <X> lc_trk_g3_3 +(21 13) routing tnl_op_3 <X> lc_trk_g3_3 +(21 14) routing bnl_op_7 <X> lc_trk_g3_7 +(21 14) routing rgt_op_7 <X> lc_trk_g3_7 +(21 14) routing sp12_v_t_4 <X> lc_trk_g3_7 +(21 14) routing sp4_h_l_26 <X> lc_trk_g3_7 +(21 14) routing sp4_h_l_34 <X> lc_trk_g3_7 +(21 14) routing sp4_v_b_39 <X> lc_trk_g3_7 +(21 14) routing sp4_v_t_18 <X> lc_trk_g3_7 +(21 15) routing bnl_op_7 <X> lc_trk_g3_7 +(21 15) routing sp12_v_b_23 <X> lc_trk_g3_7 +(21 15) routing sp12_v_t_4 <X> lc_trk_g3_7 +(21 15) routing sp4_h_l_34 <X> lc_trk_g3_7 +(21 15) routing sp4_h_r_31 <X> lc_trk_g3_7 +(21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7 +(21 15) routing sp4_v_b_39 <X> lc_trk_g3_7 +(21 15) routing tnl_op_7 <X> lc_trk_g3_7 +(21 2) routing bnr_op_7 <X> lc_trk_g0_7 +(21 2) routing lft_op_7 <X> lc_trk_g0_7 +(21 2) routing sp12_h_r_7 <X> lc_trk_g0_7 +(21 2) routing sp4_h_l_10 <X> lc_trk_g0_7 +(21 2) routing sp4_h_l_2 <X> lc_trk_g0_7 +(21 2) routing sp4_v_b_15 <X> lc_trk_g0_7 +(21 2) routing sp4_v_b_7 <X> lc_trk_g0_7 +(21 3) routing bnr_op_7 <X> lc_trk_g0_7 +(21 3) routing sp12_h_l_20 <X> lc_trk_g0_7 +(21 3) routing sp12_h_r_7 <X> lc_trk_g0_7 +(21 3) routing sp4_h_l_10 <X> lc_trk_g0_7 +(21 3) routing sp4_h_r_7 <X> lc_trk_g0_7 +(21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7 +(21 3) routing sp4_v_b_15 <X> lc_trk_g0_7 +(21 3) routing top_op_7 <X> lc_trk_g0_7 +(21 4) routing bnr_op_3 <X> lc_trk_g1_3 +(21 4) routing lft_op_3 <X> lc_trk_g1_3 +(21 4) routing sp12_h_r_3 <X> lc_trk_g1_3 +(21 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(21 4) routing sp4_h_r_19 <X> lc_trk_g1_3 +(21 4) routing sp4_v_b_11 <X> lc_trk_g1_3 +(21 4) routing sp4_v_b_3 <X> lc_trk_g1_3 +(21 5) routing bnr_op_3 <X> lc_trk_g1_3 +(21 5) routing sp12_h_l_16 <X> lc_trk_g1_3 +(21 5) routing sp12_h_r_3 <X> lc_trk_g1_3 +(21 5) routing sp4_h_r_19 <X> lc_trk_g1_3 +(21 5) routing sp4_h_r_3 <X> lc_trk_g1_3 +(21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3 +(21 5) routing sp4_v_b_11 <X> lc_trk_g1_3 +(21 5) routing top_op_3 <X> lc_trk_g1_3 +(21 6) routing bnr_op_7 <X> lc_trk_g1_7 +(21 6) routing lft_op_7 <X> lc_trk_g1_7 +(21 6) routing sp12_h_r_7 <X> lc_trk_g1_7 +(21 6) routing sp4_h_l_10 <X> lc_trk_g1_7 +(21 6) routing sp4_h_l_2 <X> lc_trk_g1_7 +(21 6) routing sp4_v_b_15 <X> lc_trk_g1_7 +(21 6) routing sp4_v_b_7 <X> lc_trk_g1_7 +(21 7) routing bnr_op_7 <X> lc_trk_g1_7 +(21 7) routing sp12_h_l_20 <X> lc_trk_g1_7 +(21 7) routing sp12_h_r_7 <X> lc_trk_g1_7 +(21 7) routing sp4_h_l_10 <X> lc_trk_g1_7 +(21 7) routing sp4_h_r_7 <X> lc_trk_g1_7 +(21 7) routing sp4_r_v_b_31 <X> lc_trk_g1_7 +(21 7) routing sp4_v_b_15 <X> lc_trk_g1_7 +(21 7) routing top_op_7 <X> lc_trk_g1_7 +(21 8) routing bnl_op_3 <X> lc_trk_g2_3 +(21 8) routing rgt_op_3 <X> lc_trk_g2_3 +(21 8) routing sp12_v_b_3 <X> lc_trk_g2_3 +(21 8) routing sp4_h_r_35 <X> lc_trk_g2_3 +(21 8) routing sp4_h_r_43 <X> lc_trk_g2_3 +(21 8) routing sp4_v_b_27 <X> lc_trk_g2_3 +(21 8) routing sp4_v_t_22 <X> lc_trk_g2_3 +(21 9) routing bnl_op_3 <X> lc_trk_g2_3 +(21 9) routing sp12_v_b_19 <X> lc_trk_g2_3 +(21 9) routing sp12_v_b_3 <X> lc_trk_g2_3 +(21 9) routing sp4_h_l_14 <X> lc_trk_g2_3 +(21 9) routing sp4_h_r_43 <X> lc_trk_g2_3 +(21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3 +(21 9) routing sp4_v_t_22 <X> lc_trk_g2_3 +(21 9) routing tnl_op_3 <X> lc_trk_g2_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => bot_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => slf_op_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 +(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_t_6 lc_trk_g0_3 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_1 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_18 lc_trk_g0_2 +(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => slf_op_7 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_39 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 +(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_21 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_19 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_35 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_19 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_27 lc_trk_g2_6 +(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_11 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_14 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_35 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_22 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_30 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 +(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => slf_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_10 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_1 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_17 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_26 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 +(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_34 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_39 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 +(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_19 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_35 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_38 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_27 lc_trk_g3_6 +(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => bot_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_15 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_23 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 +(22 2) Enable bit of Mux _local_links/g0_mux_7 => top_op_7 lc_trk_g0_7 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => slf_op_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_3 lc_trk_g0_6 +(22 3) Enable bit of Mux _local_links/g0_mux_6 => top_op_6 lc_trk_g0_6 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_t_6 lc_trk_g1_3 +(22 4) Enable bit of Mux _local_links/g1_mux_3 => top_op_3 lc_trk_g1_3 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => bot_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_1 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_17 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_18 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 +(22 5) Enable bit of Mux _local_links/g1_mux_2 => top_op_2 lc_trk_g1_2 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_15 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_23 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 +(22 6) Enable bit of Mux _local_links/g1_mux_7 => top_op_7 lc_trk_g1_7 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => bot_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => slf_op_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 +(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_3 lc_trk_g1_6 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_14 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_27 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_22 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_30 lc_trk_g2_3 +(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_1 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_17 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_26 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 +(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 +(23 0) routing sp12_h_l_16 <X> lc_trk_g0_3 +(23 0) routing sp12_h_r_11 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_19 <X> lc_trk_g0_3 +(23 0) routing sp4_h_r_3 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_11 <X> lc_trk_g0_3 +(23 0) routing sp4_v_b_3 <X> lc_trk_g0_3 +(23 0) routing sp4_v_t_6 <X> lc_trk_g0_3 +(23 1) routing sp12_h_l_17 <X> lc_trk_g0_2 +(23 1) routing sp12_h_l_9 <X> lc_trk_g0_2 +(23 1) routing sp4_h_l_7 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_10 <X> lc_trk_g0_2 +(23 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_10 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_18 <X> lc_trk_g0_2 +(23 1) routing sp4_v_b_2 <X> lc_trk_g0_2 +(23 10) routing sp12_v_b_23 <X> lc_trk_g2_7 +(23 10) routing sp12_v_t_12 <X> lc_trk_g2_7 +(23 10) routing sp4_h_l_26 <X> lc_trk_g2_7 +(23 10) routing sp4_h_l_34 <X> lc_trk_g2_7 +(23 10) routing sp4_h_r_31 <X> lc_trk_g2_7 +(23 10) routing sp4_v_b_39 <X> lc_trk_g2_7 +(23 10) routing sp4_v_t_18 <X> lc_trk_g2_7 +(23 10) routing sp4_v_t_34 <X> lc_trk_g2_7 +(23 11) routing sp12_v_b_14 <X> lc_trk_g2_6 +(23 11) routing sp12_v_t_21 <X> lc_trk_g2_6 +(23 11) routing sp4_h_l_19 <X> lc_trk_g2_6 +(23 11) routing sp4_h_l_35 <X> lc_trk_g2_6 +(23 11) routing sp4_h_r_38 <X> lc_trk_g2_6 +(23 11) routing sp4_v_b_46 <X> lc_trk_g2_6 +(23 11) routing sp4_v_t_19 <X> lc_trk_g2_6 +(23 11) routing sp4_v_t_27 <X> lc_trk_g2_6 +(23 12) routing sp12_v_b_11 <X> lc_trk_g3_3 +(23 12) routing sp12_v_b_19 <X> lc_trk_g3_3 +(23 12) routing sp4_h_l_14 <X> lc_trk_g3_3 +(23 12) routing sp4_h_r_35 <X> lc_trk_g3_3 +(23 12) routing sp4_h_r_43 <X> lc_trk_g3_3 +(23 12) routing sp4_v_b_27 <X> lc_trk_g3_3 +(23 12) routing sp4_v_t_22 <X> lc_trk_g3_3 +(23 12) routing sp4_v_t_30 <X> lc_trk_g3_3 +(23 13) routing sp12_v_b_10 <X> lc_trk_g3_2 +(23 13) routing sp12_v_t_17 <X> lc_trk_g3_2 +(23 13) routing sp4_h_r_26 <X> lc_trk_g3_2 +(23 13) routing sp4_h_r_34 <X> lc_trk_g3_2 +(23 13) routing sp4_h_r_42 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_15 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_23 <X> lc_trk_g3_2 +(23 13) routing sp4_v_t_31 <X> lc_trk_g3_2 +(23 14) routing sp12_v_b_23 <X> lc_trk_g3_7 +(23 14) routing sp12_v_t_12 <X> lc_trk_g3_7 +(23 14) routing sp4_h_l_26 <X> lc_trk_g3_7 +(23 14) routing sp4_h_l_34 <X> lc_trk_g3_7 +(23 14) routing sp4_h_r_31 <X> lc_trk_g3_7 +(23 14) routing sp4_v_b_39 <X> lc_trk_g3_7 +(23 14) routing sp4_v_t_18 <X> lc_trk_g3_7 +(23 14) routing sp4_v_t_34 <X> lc_trk_g3_7 +(23 15) routing sp12_v_b_14 <X> lc_trk_g3_6 +(23 15) routing sp12_v_t_21 <X> lc_trk_g3_6 +(23 15) routing sp4_h_l_19 <X> lc_trk_g3_6 +(23 15) routing sp4_h_l_35 <X> lc_trk_g3_6 +(23 15) routing sp4_h_r_38 <X> lc_trk_g3_6 +(23 15) routing sp4_v_b_46 <X> lc_trk_g3_6 +(23 15) routing sp4_v_t_19 <X> lc_trk_g3_6 +(23 15) routing sp4_v_t_27 <X> lc_trk_g3_6 +(23 2) routing sp12_h_l_12 <X> lc_trk_g0_7 +(23 2) routing sp12_h_l_20 <X> lc_trk_g0_7 +(23 2) routing sp4_h_l_10 <X> lc_trk_g0_7 +(23 2) routing sp4_h_l_2 <X> lc_trk_g0_7 +(23 2) routing sp4_h_r_7 <X> lc_trk_g0_7 +(23 2) routing sp4_v_b_15 <X> lc_trk_g0_7 +(23 2) routing sp4_v_b_23 <X> lc_trk_g0_7 +(23 2) routing sp4_v_b_7 <X> lc_trk_g0_7 +(23 3) routing sp12_h_r_14 <X> lc_trk_g0_6 +(23 3) routing sp12_h_r_22 <X> lc_trk_g0_6 +(23 3) routing sp4_h_l_11 <X> lc_trk_g0_6 +(23 3) routing sp4_h_l_3 <X> lc_trk_g0_6 +(23 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(23 3) routing sp4_v_b_22 <X> lc_trk_g0_6 +(23 3) routing sp4_v_b_6 <X> lc_trk_g0_6 +(23 3) routing sp4_v_t_3 <X> lc_trk_g0_6 +(23 4) routing sp12_h_l_16 <X> lc_trk_g1_3 +(23 4) routing sp12_h_r_11 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_19 <X> lc_trk_g1_3 +(23 4) routing sp4_h_r_3 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_11 <X> lc_trk_g1_3 +(23 4) routing sp4_v_b_3 <X> lc_trk_g1_3 +(23 4) routing sp4_v_t_6 <X> lc_trk_g1_3 +(23 5) routing sp12_h_l_17 <X> lc_trk_g1_2 +(23 5) routing sp12_h_l_9 <X> lc_trk_g1_2 +(23 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(23 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_10 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_18 <X> lc_trk_g1_2 +(23 5) routing sp4_v_b_2 <X> lc_trk_g1_2 +(23 6) routing sp12_h_l_12 <X> lc_trk_g1_7 +(23 6) routing sp12_h_l_20 <X> lc_trk_g1_7 +(23 6) routing sp4_h_l_10 <X> lc_trk_g1_7 +(23 6) routing sp4_h_l_2 <X> lc_trk_g1_7 +(23 6) routing sp4_h_r_7 <X> lc_trk_g1_7 +(23 6) routing sp4_v_b_15 <X> lc_trk_g1_7 +(23 6) routing sp4_v_b_23 <X> lc_trk_g1_7 +(23 6) routing sp4_v_b_7 <X> lc_trk_g1_7 +(23 7) routing sp12_h_r_14 <X> lc_trk_g1_6 +(23 7) routing sp12_h_r_22 <X> lc_trk_g1_6 +(23 7) routing sp4_h_l_11 <X> lc_trk_g1_6 +(23 7) routing sp4_h_l_3 <X> lc_trk_g1_6 +(23 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_22 <X> lc_trk_g1_6 +(23 7) routing sp4_v_b_6 <X> lc_trk_g1_6 +(23 7) routing sp4_v_t_3 <X> lc_trk_g1_6 +(23 8) routing sp12_v_b_11 <X> lc_trk_g2_3 +(23 8) routing sp12_v_b_19 <X> lc_trk_g2_3 +(23 8) routing sp4_h_l_14 <X> lc_trk_g2_3 +(23 8) routing sp4_h_r_35 <X> lc_trk_g2_3 +(23 8) routing sp4_h_r_43 <X> lc_trk_g2_3 +(23 8) routing sp4_v_b_27 <X> lc_trk_g2_3 +(23 8) routing sp4_v_t_22 <X> lc_trk_g2_3 +(23 8) routing sp4_v_t_30 <X> lc_trk_g2_3 +(23 9) routing sp12_v_b_10 <X> lc_trk_g2_2 +(23 9) routing sp12_v_t_17 <X> lc_trk_g2_2 +(23 9) routing sp4_h_r_26 <X> lc_trk_g2_2 +(23 9) routing sp4_h_r_34 <X> lc_trk_g2_2 +(23 9) routing sp4_h_r_42 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_15 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_23 <X> lc_trk_g2_2 +(23 9) routing sp4_v_t_31 <X> lc_trk_g2_2 +(24 0) routing bot_op_3 <X> lc_trk_g0_3 +(24 0) routing lft_op_3 <X> lc_trk_g0_3 +(24 0) routing sp12_h_r_3 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_11 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_19 <X> lc_trk_g0_3 +(24 0) routing sp4_h_r_3 <X> lc_trk_g0_3 +(24 0) routing sp4_v_t_6 <X> lc_trk_g0_3 +(24 1) routing lft_op_2 <X> lc_trk_g0_2 +(24 1) routing sp12_h_l_1 <X> lc_trk_g0_2 +(24 1) routing sp4_h_l_7 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_10 <X> lc_trk_g0_2 +(24 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(24 1) routing sp4_v_b_18 <X> lc_trk_g0_2 +(24 10) routing rgt_op_7 <X> lc_trk_g2_7 +(24 10) routing sp12_v_t_4 <X> lc_trk_g2_7 +(24 10) routing sp4_h_l_26 <X> lc_trk_g2_7 +(24 10) routing sp4_h_l_34 <X> lc_trk_g2_7 +(24 10) routing sp4_h_r_31 <X> lc_trk_g2_7 +(24 10) routing sp4_v_t_34 <X> lc_trk_g2_7 +(24 10) routing tnr_op_7 <X> lc_trk_g2_7 +(24 11) routing rgt_op_6 <X> lc_trk_g2_6 +(24 11) routing sp12_v_b_6 <X> lc_trk_g2_6 +(24 11) routing sp4_h_l_19 <X> lc_trk_g2_6 +(24 11) routing sp4_h_l_35 <X> lc_trk_g2_6 +(24 11) routing sp4_h_r_38 <X> lc_trk_g2_6 +(24 11) routing sp4_v_b_46 <X> lc_trk_g2_6 +(24 11) routing tnl_op_6 <X> lc_trk_g2_6 +(24 12) routing rgt_op_3 <X> lc_trk_g3_3 +(24 12) routing sp12_v_b_3 <X> lc_trk_g3_3 +(24 12) routing sp4_h_l_14 <X> lc_trk_g3_3 +(24 12) routing sp4_h_r_35 <X> lc_trk_g3_3 +(24 12) routing sp4_h_r_43 <X> lc_trk_g3_3 +(24 12) routing sp4_v_t_30 <X> lc_trk_g3_3 +(24 12) routing tnl_op_3 <X> lc_trk_g3_3 +(24 12) routing tnr_op_3 <X> lc_trk_g3_3 +(24 13) routing rgt_op_2 <X> lc_trk_g3_2 +(24 13) routing sp12_v_t_1 <X> lc_trk_g3_2 +(24 13) routing sp4_h_r_26 <X> lc_trk_g3_2 +(24 13) routing sp4_h_r_34 <X> lc_trk_g3_2 +(24 13) routing sp4_h_r_42 <X> lc_trk_g3_2 +(24 13) routing sp4_v_t_31 <X> lc_trk_g3_2 +(24 13) routing tnl_op_2 <X> lc_trk_g3_2 +(24 13) routing tnr_op_2 <X> lc_trk_g3_2 +(24 14) routing rgt_op_7 <X> lc_trk_g3_7 +(24 14) routing sp12_v_t_4 <X> lc_trk_g3_7 +(24 14) routing sp4_h_l_26 <X> lc_trk_g3_7 +(24 14) routing sp4_h_l_34 <X> lc_trk_g3_7 +(24 14) routing sp4_h_r_31 <X> lc_trk_g3_7 +(24 14) routing sp4_v_t_34 <X> lc_trk_g3_7 +(24 14) routing tnl_op_7 <X> lc_trk_g3_7 +(24 14) routing tnr_op_7 <X> lc_trk_g3_7 +(24 15) routing rgt_op_6 <X> lc_trk_g3_6 +(24 15) routing sp12_v_b_6 <X> lc_trk_g3_6 +(24 15) routing sp4_h_l_19 <X> lc_trk_g3_6 +(24 15) routing sp4_h_l_35 <X> lc_trk_g3_6 +(24 15) routing sp4_h_r_38 <X> lc_trk_g3_6 +(24 15) routing sp4_v_b_46 <X> lc_trk_g3_6 +(24 15) routing tnr_op_6 <X> lc_trk_g3_6 +(24 2) routing bot_op_7 <X> lc_trk_g0_7 +(24 2) routing lft_op_7 <X> lc_trk_g0_7 +(24 2) routing sp12_h_r_7 <X> lc_trk_g0_7 +(24 2) routing sp4_h_l_10 <X> lc_trk_g0_7 +(24 2) routing sp4_h_l_2 <X> lc_trk_g0_7 +(24 2) routing sp4_h_r_7 <X> lc_trk_g0_7 +(24 2) routing sp4_v_b_23 <X> lc_trk_g0_7 +(24 2) routing top_op_7 <X> lc_trk_g0_7 +(24 3) routing lft_op_6 <X> lc_trk_g0_6 +(24 3) routing sp12_h_l_5 <X> lc_trk_g0_6 +(24 3) routing sp4_h_l_11 <X> lc_trk_g0_6 +(24 3) routing sp4_h_l_3 <X> lc_trk_g0_6 +(24 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(24 3) routing sp4_v_b_22 <X> lc_trk_g0_6 +(24 3) routing top_op_6 <X> lc_trk_g0_6 +(24 4) routing lft_op_3 <X> lc_trk_g1_3 +(24 4) routing sp12_h_r_3 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_11 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_19 <X> lc_trk_g1_3 +(24 4) routing sp4_h_r_3 <X> lc_trk_g1_3 +(24 4) routing sp4_v_t_6 <X> lc_trk_g1_3 +(24 4) routing top_op_3 <X> lc_trk_g1_3 +(24 5) routing bot_op_2 <X> lc_trk_g1_2 +(24 5) routing lft_op_2 <X> lc_trk_g1_2 +(24 5) routing sp12_h_l_1 <X> lc_trk_g1_2 +(24 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_10 <X> lc_trk_g1_2 +(24 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(24 5) routing sp4_v_b_18 <X> lc_trk_g1_2 +(24 5) routing top_op_2 <X> lc_trk_g1_2 +(24 6) routing lft_op_7 <X> lc_trk_g1_7 +(24 6) routing sp12_h_r_7 <X> lc_trk_g1_7 +(24 6) routing sp4_h_l_10 <X> lc_trk_g1_7 +(24 6) routing sp4_h_l_2 <X> lc_trk_g1_7 +(24 6) routing sp4_h_r_7 <X> lc_trk_g1_7 +(24 6) routing sp4_v_b_23 <X> lc_trk_g1_7 +(24 6) routing top_op_7 <X> lc_trk_g1_7 +(24 7) routing bot_op_6 <X> lc_trk_g1_6 +(24 7) routing lft_op_6 <X> lc_trk_g1_6 +(24 7) routing sp12_h_l_5 <X> lc_trk_g1_6 +(24 7) routing sp4_h_l_11 <X> lc_trk_g1_6 +(24 7) routing sp4_h_l_3 <X> lc_trk_g1_6 +(24 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(24 7) routing sp4_v_b_22 <X> lc_trk_g1_6 +(24 8) routing rgt_op_3 <X> lc_trk_g2_3 +(24 8) routing sp12_v_b_3 <X> lc_trk_g2_3 +(24 8) routing sp4_h_l_14 <X> lc_trk_g2_3 +(24 8) routing sp4_h_r_35 <X> lc_trk_g2_3 +(24 8) routing sp4_h_r_43 <X> lc_trk_g2_3 +(24 8) routing sp4_v_t_30 <X> lc_trk_g2_3 +(24 8) routing tnl_op_3 <X> lc_trk_g2_3 +(24 9) routing rgt_op_2 <X> lc_trk_g2_2 +(24 9) routing sp12_v_t_1 <X> lc_trk_g2_2 +(24 9) routing sp4_h_r_26 <X> lc_trk_g2_2 +(24 9) routing sp4_h_r_34 <X> lc_trk_g2_2 +(24 9) routing sp4_h_r_42 <X> lc_trk_g2_2 +(24 9) routing sp4_v_t_31 <X> lc_trk_g2_2 +(24 9) routing tnl_op_2 <X> lc_trk_g2_2 +(24 9) routing tnr_op_2 <X> lc_trk_g2_2 +(25 0) routing bnr_op_2 <X> lc_trk_g0_2 +(25 0) routing lft_op_2 <X> lc_trk_g0_2 +(25 0) routing sp12_h_l_1 <X> lc_trk_g0_2 +(25 0) routing sp4_h_l_7 <X> lc_trk_g0_2 +(25 0) routing sp4_h_r_10 <X> lc_trk_g0_2 +(25 0) routing sp4_v_b_10 <X> lc_trk_g0_2 +(25 0) routing sp4_v_b_2 <X> lc_trk_g0_2 +(25 1) routing bnr_op_2 <X> lc_trk_g0_2 +(25 1) routing sp12_h_l_1 <X> lc_trk_g0_2 +(25 1) routing sp12_h_l_17 <X> lc_trk_g0_2 +(25 1) routing sp4_h_l_7 <X> lc_trk_g0_2 +(25 1) routing sp4_h_r_2 <X> lc_trk_g0_2 +(25 1) routing sp4_r_v_b_33 <X> lc_trk_g0_2 +(25 1) routing sp4_v_b_10 <X> lc_trk_g0_2 +(25 10) routing bnl_op_6 <X> lc_trk_g2_6 +(25 10) routing rgt_op_6 <X> lc_trk_g2_6 +(25 10) routing sp12_v_b_6 <X> lc_trk_g2_6 +(25 10) routing sp4_h_l_35 <X> lc_trk_g2_6 +(25 10) routing sp4_h_r_38 <X> lc_trk_g2_6 +(25 10) routing sp4_v_t_19 <X> lc_trk_g2_6 +(25 10) routing sp4_v_t_27 <X> lc_trk_g2_6 +(25 11) routing bnl_op_6 <X> lc_trk_g2_6 +(25 11) routing sp12_v_b_6 <X> lc_trk_g2_6 +(25 11) routing sp12_v_t_21 <X> lc_trk_g2_6 +(25 11) routing sp4_h_l_19 <X> lc_trk_g2_6 +(25 11) routing sp4_h_l_35 <X> lc_trk_g2_6 +(25 11) routing sp4_r_v_b_38 <X> lc_trk_g2_6 +(25 11) routing sp4_v_t_27 <X> lc_trk_g2_6 +(25 11) routing tnl_op_6 <X> lc_trk_g2_6 +(25 12) routing bnl_op_2 <X> lc_trk_g3_2 +(25 12) routing rgt_op_2 <X> lc_trk_g3_2 +(25 12) routing slf_op_2 <X> lc_trk_g3_2 +(25 12) routing sp12_v_t_1 <X> lc_trk_g3_2 +(25 12) routing sp4_h_r_34 <X> lc_trk_g3_2 +(25 12) routing sp4_h_r_42 <X> lc_trk_g3_2 +(25 12) routing sp4_v_t_15 <X> lc_trk_g3_2 +(25 12) routing sp4_v_t_23 <X> lc_trk_g3_2 +(25 13) routing bnl_op_2 <X> lc_trk_g3_2 +(25 13) routing sp12_v_t_1 <X> lc_trk_g3_2 +(25 13) routing sp12_v_t_17 <X> lc_trk_g3_2 +(25 13) routing sp4_h_r_26 <X> lc_trk_g3_2 +(25 13) routing sp4_h_r_42 <X> lc_trk_g3_2 +(25 13) routing sp4_r_v_b_42 <X> lc_trk_g3_2 +(25 13) routing sp4_v_t_23 <X> lc_trk_g3_2 +(25 13) routing tnl_op_2 <X> lc_trk_g3_2 +(25 14) routing bnl_op_6 <X> lc_trk_g3_6 +(25 14) routing rgt_op_6 <X> lc_trk_g3_6 +(25 14) routing sp12_v_b_6 <X> lc_trk_g3_6 +(25 14) routing sp4_h_l_35 <X> lc_trk_g3_6 +(25 14) routing sp4_h_r_38 <X> lc_trk_g3_6 +(25 14) routing sp4_v_t_19 <X> lc_trk_g3_6 +(25 14) routing sp4_v_t_27 <X> lc_trk_g3_6 +(25 15) routing bnl_op_6 <X> lc_trk_g3_6 +(25 15) routing sp12_v_b_6 <X> lc_trk_g3_6 +(25 15) routing sp12_v_t_21 <X> lc_trk_g3_6 +(25 15) routing sp4_h_l_19 <X> lc_trk_g3_6 +(25 15) routing sp4_h_l_35 <X> lc_trk_g3_6 +(25 15) routing sp4_r_v_b_46 <X> lc_trk_g3_6 +(25 15) routing sp4_v_t_27 <X> lc_trk_g3_6 +(25 2) routing bnr_op_6 <X> lc_trk_g0_6 +(25 2) routing lft_op_6 <X> lc_trk_g0_6 +(25 2) routing slf_op_6 <X> lc_trk_g0_6 +(25 2) routing sp12_h_l_5 <X> lc_trk_g0_6 +(25 2) routing sp4_h_l_11 <X> lc_trk_g0_6 +(25 2) routing sp4_h_l_3 <X> lc_trk_g0_6 +(25 2) routing sp4_v_b_6 <X> lc_trk_g0_6 +(25 2) routing sp4_v_t_3 <X> lc_trk_g0_6 +(25 3) routing bnr_op_6 <X> lc_trk_g0_6 +(25 3) routing sp12_h_l_5 <X> lc_trk_g0_6 +(25 3) routing sp12_h_r_22 <X> lc_trk_g0_6 +(25 3) routing sp4_h_l_11 <X> lc_trk_g0_6 +(25 3) routing sp4_h_r_6 <X> lc_trk_g0_6 +(25 3) routing sp4_r_v_b_30 <X> lc_trk_g0_6 +(25 3) routing sp4_v_t_3 <X> lc_trk_g0_6 +(25 3) routing top_op_6 <X> lc_trk_g0_6 +(25 4) routing bnr_op_2 <X> lc_trk_g1_2 +(25 4) routing lft_op_2 <X> lc_trk_g1_2 +(25 4) routing sp12_h_l_1 <X> lc_trk_g1_2 +(25 4) routing sp4_h_l_7 <X> lc_trk_g1_2 +(25 4) routing sp4_h_r_10 <X> lc_trk_g1_2 +(25 4) routing sp4_v_b_10 <X> lc_trk_g1_2 +(25 4) routing sp4_v_b_2 <X> lc_trk_g1_2 +(25 5) routing bnr_op_2 <X> lc_trk_g1_2 +(25 5) routing sp12_h_l_1 <X> lc_trk_g1_2 +(25 5) routing sp12_h_l_17 <X> lc_trk_g1_2 +(25 5) routing sp4_h_l_7 <X> lc_trk_g1_2 +(25 5) routing sp4_h_r_2 <X> lc_trk_g1_2 +(25 5) routing sp4_r_v_b_26 <X> lc_trk_g1_2 +(25 5) routing sp4_v_b_10 <X> lc_trk_g1_2 +(25 5) routing top_op_2 <X> lc_trk_g1_2 +(25 6) routing bnr_op_6 <X> lc_trk_g1_6 +(25 6) routing lft_op_6 <X> lc_trk_g1_6 +(25 6) routing slf_op_6 <X> lc_trk_g1_6 +(25 6) routing sp12_h_l_5 <X> lc_trk_g1_6 +(25 6) routing sp4_h_l_11 <X> lc_trk_g1_6 +(25 6) routing sp4_h_l_3 <X> lc_trk_g1_6 +(25 6) routing sp4_v_b_6 <X> lc_trk_g1_6 +(25 6) routing sp4_v_t_3 <X> lc_trk_g1_6 +(25 7) routing bnr_op_6 <X> lc_trk_g1_6 +(25 7) routing sp12_h_l_5 <X> lc_trk_g1_6 +(25 7) routing sp12_h_r_22 <X> lc_trk_g1_6 +(25 7) routing sp4_h_l_11 <X> lc_trk_g1_6 +(25 7) routing sp4_h_r_6 <X> lc_trk_g1_6 +(25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6 +(25 7) routing sp4_v_t_3 <X> lc_trk_g1_6 +(25 8) routing bnl_op_2 <X> lc_trk_g2_2 +(25 8) routing rgt_op_2 <X> lc_trk_g2_2 +(25 8) routing sp12_v_t_1 <X> lc_trk_g2_2 +(25 8) routing sp4_h_r_34 <X> lc_trk_g2_2 +(25 8) routing sp4_h_r_42 <X> lc_trk_g2_2 +(25 8) routing sp4_v_t_15 <X> lc_trk_g2_2 +(25 8) routing sp4_v_t_23 <X> lc_trk_g2_2 +(25 9) routing bnl_op_2 <X> lc_trk_g2_2 +(25 9) routing sp12_v_t_1 <X> lc_trk_g2_2 +(25 9) routing sp12_v_t_17 <X> lc_trk_g2_2 +(25 9) routing sp4_h_r_26 <X> lc_trk_g2_2 +(25 9) routing sp4_h_r_42 <X> lc_trk_g2_2 +(25 9) routing sp4_r_v_b_34 <X> lc_trk_g2_2 +(25 9) routing sp4_v_t_23 <X> lc_trk_g2_2 +(25 9) routing tnl_op_2 <X> lc_trk_g2_2 +(26 0) routing lc_trk_g0_4 <X> wire_con_box/lc_0/in_0 +(26 0) routing lc_trk_g0_6 <X> wire_con_box/lc_0/in_0 +(26 0) routing lc_trk_g1_5 <X> wire_con_box/lc_0/in_0 +(26 0) routing lc_trk_g1_7 <X> wire_con_box/lc_0/in_0 +(26 0) routing lc_trk_g2_4 <X> wire_con_box/lc_0/in_0 +(26 0) routing lc_trk_g2_6 <X> wire_con_box/lc_0/in_0 +(26 0) routing lc_trk_g3_5 <X> wire_con_box/lc_0/in_0 +(26 0) routing lc_trk_g3_7 <X> wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g0_2 <X> wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g0_6 <X> wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g1_3 <X> wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g1_7 <X> wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g2_2 <X> wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g2_6 <X> wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g3_3 <X> wire_con_box/lc_0/in_0 +(26 1) routing lc_trk_g3_7 <X> wire_con_box/lc_0/in_0 +(26 10) routing lc_trk_g0_5 <X> wire_con_box/lc_5/in_0 +(26 10) routing lc_trk_g0_7 <X> wire_con_box/lc_5/in_0 +(26 10) routing lc_trk_g1_4 <X> wire_con_box/lc_5/in_0 +(26 10) routing lc_trk_g1_6 <X> wire_con_box/lc_5/in_0 +(26 10) routing lc_trk_g2_5 <X> wire_con_box/lc_5/in_0 +(26 10) routing lc_trk_g2_7 <X> wire_con_box/lc_5/in_0 +(26 10) routing lc_trk_g3_4 <X> wire_con_box/lc_5/in_0 +(26 10) routing lc_trk_g3_6 <X> wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g0_3 <X> wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g0_7 <X> wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g1_2 <X> wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g1_6 <X> wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g2_3 <X> wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g2_7 <X> wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g3_2 <X> wire_con_box/lc_5/in_0 +(26 11) routing lc_trk_g3_6 <X> wire_con_box/lc_5/in_0 +(26 12) routing lc_trk_g0_4 <X> wire_con_box/lc_6/in_0 +(26 12) routing lc_trk_g0_6 <X> wire_con_box/lc_6/in_0 +(26 12) routing lc_trk_g1_5 <X> wire_con_box/lc_6/in_0 +(26 12) routing lc_trk_g1_7 <X> wire_con_box/lc_6/in_0 +(26 12) routing lc_trk_g2_4 <X> wire_con_box/lc_6/in_0 +(26 12) routing lc_trk_g2_6 <X> wire_con_box/lc_6/in_0 +(26 12) routing lc_trk_g3_5 <X> wire_con_box/lc_6/in_0 +(26 12) routing lc_trk_g3_7 <X> wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g0_2 <X> wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g0_6 <X> wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g1_3 <X> wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g1_7 <X> wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g2_2 <X> wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g2_6 <X> wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g3_3 <X> wire_con_box/lc_6/in_0 +(26 13) routing lc_trk_g3_7 <X> wire_con_box/lc_6/in_0 +(26 14) routing lc_trk_g0_5 <X> wire_con_box/lc_7/in_0 +(26 14) routing lc_trk_g0_7 <X> wire_con_box/lc_7/in_0 +(26 14) routing lc_trk_g1_4 <X> wire_con_box/lc_7/in_0 +(26 14) routing lc_trk_g1_6 <X> wire_con_box/lc_7/in_0 +(26 14) routing lc_trk_g2_5 <X> wire_con_box/lc_7/in_0 +(26 14) routing lc_trk_g2_7 <X> wire_con_box/lc_7/in_0 +(26 14) routing lc_trk_g3_4 <X> wire_con_box/lc_7/in_0 +(26 14) routing lc_trk_g3_6 <X> wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g0_3 <X> wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g0_7 <X> wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g1_2 <X> wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g1_6 <X> wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g2_3 <X> wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g2_7 <X> wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g3_2 <X> wire_con_box/lc_7/in_0 +(26 15) routing lc_trk_g3_6 <X> wire_con_box/lc_7/in_0 +(26 2) routing lc_trk_g0_5 <X> wire_con_box/lc_1/in_0 +(26 2) routing lc_trk_g0_7 <X> wire_con_box/lc_1/in_0 +(26 2) routing lc_trk_g1_4 <X> wire_con_box/lc_1/in_0 +(26 2) routing lc_trk_g1_6 <X> wire_con_box/lc_1/in_0 +(26 2) routing lc_trk_g2_5 <X> wire_con_box/lc_1/in_0 +(26 2) routing lc_trk_g2_7 <X> wire_con_box/lc_1/in_0 +(26 2) routing lc_trk_g3_4 <X> wire_con_box/lc_1/in_0 +(26 2) routing lc_trk_g3_6 <X> wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g0_3 <X> wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g0_7 <X> wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g1_2 <X> wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g1_6 <X> wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g2_3 <X> wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g2_7 <X> wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g3_2 <X> wire_con_box/lc_1/in_0 +(26 3) routing lc_trk_g3_6 <X> wire_con_box/lc_1/in_0 +(26 4) routing lc_trk_g0_4 <X> wire_con_box/lc_2/in_0 +(26 4) routing lc_trk_g0_6 <X> wire_con_box/lc_2/in_0 +(26 4) routing lc_trk_g1_5 <X> wire_con_box/lc_2/in_0 +(26 4) routing lc_trk_g1_7 <X> wire_con_box/lc_2/in_0 +(26 4) routing lc_trk_g2_4 <X> wire_con_box/lc_2/in_0 +(26 4) routing lc_trk_g2_6 <X> wire_con_box/lc_2/in_0 +(26 4) routing lc_trk_g3_5 <X> wire_con_box/lc_2/in_0 +(26 4) routing lc_trk_g3_7 <X> wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g0_2 <X> wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g0_6 <X> wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g1_3 <X> wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g1_7 <X> wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g2_2 <X> wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g2_6 <X> wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g3_3 <X> wire_con_box/lc_2/in_0 +(26 5) routing lc_trk_g3_7 <X> wire_con_box/lc_2/in_0 +(26 6) routing lc_trk_g0_5 <X> wire_con_box/lc_3/in_0 +(26 6) routing lc_trk_g0_7 <X> wire_con_box/lc_3/in_0 +(26 6) routing lc_trk_g1_4 <X> wire_con_box/lc_3/in_0 +(26 6) routing lc_trk_g1_6 <X> wire_con_box/lc_3/in_0 +(26 6) routing lc_trk_g2_5 <X> wire_con_box/lc_3/in_0 +(26 6) routing lc_trk_g2_7 <X> wire_con_box/lc_3/in_0 +(26 6) routing lc_trk_g3_4 <X> wire_con_box/lc_3/in_0 +(26 6) routing lc_trk_g3_6 <X> wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g0_3 <X> wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g0_7 <X> wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g1_2 <X> wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g1_6 <X> wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g2_3 <X> wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g2_7 <X> wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g3_2 <X> wire_con_box/lc_3/in_0 +(26 7) routing lc_trk_g3_6 <X> wire_con_box/lc_3/in_0 +(26 8) routing lc_trk_g0_4 <X> wire_con_box/lc_4/in_0 +(26 8) routing lc_trk_g0_6 <X> wire_con_box/lc_4/in_0 +(26 8) routing lc_trk_g1_5 <X> wire_con_box/lc_4/in_0 +(26 8) routing lc_trk_g1_7 <X> wire_con_box/lc_4/in_0 +(26 8) routing lc_trk_g2_4 <X> wire_con_box/lc_4/in_0 +(26 8) routing lc_trk_g2_6 <X> wire_con_box/lc_4/in_0 +(26 8) routing lc_trk_g3_5 <X> wire_con_box/lc_4/in_0 +(26 8) routing lc_trk_g3_7 <X> wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g0_2 <X> wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g0_6 <X> wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g1_3 <X> wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g1_7 <X> wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g2_2 <X> wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g2_6 <X> wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g3_3 <X> wire_con_box/lc_4/in_0 +(26 9) routing lc_trk_g3_7 <X> wire_con_box/lc_4/in_0 +(27 0) routing lc_trk_g1_0 <X> wire_con_box/lc_0/in_1 +(27 0) routing lc_trk_g1_2 <X> wire_con_box/lc_0/in_1 +(27 0) routing lc_trk_g1_4 <X> wire_con_box/lc_0/in_1 +(27 0) routing lc_trk_g1_6 <X> wire_con_box/lc_0/in_1 +(27 0) routing lc_trk_g3_0 <X> wire_con_box/lc_0/in_1 +(27 0) routing lc_trk_g3_2 <X> wire_con_box/lc_0/in_1 +(27 0) routing lc_trk_g3_4 <X> wire_con_box/lc_0/in_1 +(27 0) routing lc_trk_g3_6 <X> wire_con_box/lc_0/in_1 +(27 1) routing lc_trk_g1_1 <X> wire_con_box/lc_0/in_0 +(27 1) routing lc_trk_g1_3 <X> wire_con_box/lc_0/in_0 +(27 1) routing lc_trk_g1_5 <X> wire_con_box/lc_0/in_0 +(27 1) routing lc_trk_g1_7 <X> wire_con_box/lc_0/in_0 +(27 1) routing lc_trk_g3_1 <X> wire_con_box/lc_0/in_0 +(27 1) routing lc_trk_g3_3 <X> wire_con_box/lc_0/in_0 +(27 1) routing lc_trk_g3_5 <X> wire_con_box/lc_0/in_0 +(27 1) routing lc_trk_g3_7 <X> wire_con_box/lc_0/in_0 +(27 10) routing lc_trk_g1_1 <X> wire_con_box/lc_5/in_1 +(27 10) routing lc_trk_g1_3 <X> wire_con_box/lc_5/in_1 +(27 10) routing lc_trk_g1_5 <X> wire_con_box/lc_5/in_1 +(27 10) routing lc_trk_g1_7 <X> wire_con_box/lc_5/in_1 +(27 10) routing lc_trk_g3_1 <X> wire_con_box/lc_5/in_1 +(27 10) routing lc_trk_g3_3 <X> wire_con_box/lc_5/in_1 +(27 10) routing lc_trk_g3_5 <X> wire_con_box/lc_5/in_1 +(27 10) routing lc_trk_g3_7 <X> wire_con_box/lc_5/in_1 +(27 11) routing lc_trk_g1_0 <X> wire_con_box/lc_5/in_0 +(27 11) routing lc_trk_g1_2 <X> wire_con_box/lc_5/in_0 +(27 11) routing lc_trk_g1_4 <X> wire_con_box/lc_5/in_0 +(27 11) routing lc_trk_g1_6 <X> wire_con_box/lc_5/in_0 +(27 11) routing lc_trk_g3_0 <X> wire_con_box/lc_5/in_0 +(27 11) routing lc_trk_g3_2 <X> wire_con_box/lc_5/in_0 +(27 11) routing lc_trk_g3_4 <X> wire_con_box/lc_5/in_0 +(27 11) routing lc_trk_g3_6 <X> wire_con_box/lc_5/in_0 +(27 12) routing lc_trk_g1_0 <X> wire_con_box/lc_6/in_1 +(27 12) routing lc_trk_g1_2 <X> wire_con_box/lc_6/in_1 +(27 12) routing lc_trk_g1_4 <X> wire_con_box/lc_6/in_1 +(27 12) routing lc_trk_g1_6 <X> wire_con_box/lc_6/in_1 +(27 12) routing lc_trk_g3_0 <X> wire_con_box/lc_6/in_1 +(27 12) routing lc_trk_g3_2 <X> wire_con_box/lc_6/in_1 +(27 12) routing lc_trk_g3_4 <X> wire_con_box/lc_6/in_1 +(27 12) routing lc_trk_g3_6 <X> wire_con_box/lc_6/in_1 +(27 13) routing lc_trk_g1_1 <X> wire_con_box/lc_6/in_0 +(27 13) routing lc_trk_g1_3 <X> wire_con_box/lc_6/in_0 +(27 13) routing lc_trk_g1_5 <X> wire_con_box/lc_6/in_0 +(27 13) routing lc_trk_g1_7 <X> wire_con_box/lc_6/in_0 +(27 13) routing lc_trk_g3_1 <X> wire_con_box/lc_6/in_0 +(27 13) routing lc_trk_g3_3 <X> wire_con_box/lc_6/in_0 +(27 13) routing lc_trk_g3_5 <X> wire_con_box/lc_6/in_0 +(27 13) routing lc_trk_g3_7 <X> wire_con_box/lc_6/in_0 +(27 14) routing lc_trk_g1_1 <X> wire_con_box/lc_7/in_1 +(27 14) routing lc_trk_g1_3 <X> wire_con_box/lc_7/in_1 +(27 14) routing lc_trk_g1_5 <X> wire_con_box/lc_7/in_1 +(27 14) routing lc_trk_g1_7 <X> wire_con_box/lc_7/in_1 +(27 14) routing lc_trk_g3_1 <X> wire_con_box/lc_7/in_1 +(27 14) routing lc_trk_g3_3 <X> wire_con_box/lc_7/in_1 +(27 14) routing lc_trk_g3_5 <X> wire_con_box/lc_7/in_1 +(27 14) routing lc_trk_g3_7 <X> wire_con_box/lc_7/in_1 +(27 15) routing lc_trk_g1_0 <X> wire_con_box/lc_7/in_0 +(27 15) routing lc_trk_g1_2 <X> wire_con_box/lc_7/in_0 +(27 15) routing lc_trk_g1_4 <X> wire_con_box/lc_7/in_0 +(27 15) routing lc_trk_g1_6 <X> wire_con_box/lc_7/in_0 +(27 15) routing lc_trk_g3_0 <X> wire_con_box/lc_7/in_0 +(27 15) routing lc_trk_g3_2 <X> wire_con_box/lc_7/in_0 +(27 15) routing lc_trk_g3_4 <X> wire_con_box/lc_7/in_0 +(27 15) routing lc_trk_g3_6 <X> wire_con_box/lc_7/in_0 +(27 2) routing lc_trk_g1_1 <X> wire_con_box/lc_1/in_1 +(27 2) routing lc_trk_g1_3 <X> wire_con_box/lc_1/in_1 +(27 2) routing lc_trk_g1_5 <X> wire_con_box/lc_1/in_1 +(27 2) routing lc_trk_g1_7 <X> wire_con_box/lc_1/in_1 +(27 2) routing lc_trk_g3_1 <X> wire_con_box/lc_1/in_1 +(27 2) routing lc_trk_g3_3 <X> wire_con_box/lc_1/in_1 +(27 2) routing lc_trk_g3_5 <X> wire_con_box/lc_1/in_1 +(27 2) routing lc_trk_g3_7 <X> wire_con_box/lc_1/in_1 +(27 3) routing lc_trk_g1_0 <X> wire_con_box/lc_1/in_0 +(27 3) routing lc_trk_g1_2 <X> wire_con_box/lc_1/in_0 +(27 3) routing lc_trk_g1_4 <X> wire_con_box/lc_1/in_0 +(27 3) routing lc_trk_g1_6 <X> wire_con_box/lc_1/in_0 +(27 3) routing lc_trk_g3_0 <X> wire_con_box/lc_1/in_0 +(27 3) routing lc_trk_g3_2 <X> wire_con_box/lc_1/in_0 +(27 3) routing lc_trk_g3_4 <X> wire_con_box/lc_1/in_0 +(27 3) routing lc_trk_g3_6 <X> wire_con_box/lc_1/in_0 +(27 4) routing lc_trk_g1_0 <X> wire_con_box/lc_2/in_1 +(27 4) routing lc_trk_g1_2 <X> wire_con_box/lc_2/in_1 +(27 4) routing lc_trk_g1_4 <X> wire_con_box/lc_2/in_1 +(27 4) routing lc_trk_g1_6 <X> wire_con_box/lc_2/in_1 +(27 4) routing lc_trk_g3_0 <X> wire_con_box/lc_2/in_1 +(27 4) routing lc_trk_g3_2 <X> wire_con_box/lc_2/in_1 +(27 4) routing lc_trk_g3_4 <X> wire_con_box/lc_2/in_1 +(27 4) routing lc_trk_g3_6 <X> wire_con_box/lc_2/in_1 +(27 5) routing lc_trk_g1_1 <X> wire_con_box/lc_2/in_0 +(27 5) routing lc_trk_g1_3 <X> wire_con_box/lc_2/in_0 +(27 5) routing lc_trk_g1_5 <X> wire_con_box/lc_2/in_0 +(27 5) routing lc_trk_g1_7 <X> wire_con_box/lc_2/in_0 +(27 5) routing lc_trk_g3_1 <X> wire_con_box/lc_2/in_0 +(27 5) routing lc_trk_g3_3 <X> wire_con_box/lc_2/in_0 +(27 5) routing lc_trk_g3_5 <X> wire_con_box/lc_2/in_0 +(27 5) routing lc_trk_g3_7 <X> wire_con_box/lc_2/in_0 +(27 6) routing lc_trk_g1_1 <X> wire_con_box/lc_3/in_1 +(27 6) routing lc_trk_g1_3 <X> wire_con_box/lc_3/in_1 +(27 6) routing lc_trk_g1_5 <X> wire_con_box/lc_3/in_1 +(27 6) routing lc_trk_g1_7 <X> wire_con_box/lc_3/in_1 +(27 6) routing lc_trk_g3_1 <X> wire_con_box/lc_3/in_1 +(27 6) routing lc_trk_g3_3 <X> wire_con_box/lc_3/in_1 +(27 6) routing lc_trk_g3_5 <X> wire_con_box/lc_3/in_1 +(27 6) routing lc_trk_g3_7 <X> wire_con_box/lc_3/in_1 +(27 7) routing lc_trk_g1_0 <X> wire_con_box/lc_3/in_0 +(27 7) routing lc_trk_g1_2 <X> wire_con_box/lc_3/in_0 +(27 7) routing lc_trk_g1_4 <X> wire_con_box/lc_3/in_0 +(27 7) routing lc_trk_g1_6 <X> wire_con_box/lc_3/in_0 +(27 7) routing lc_trk_g3_0 <X> wire_con_box/lc_3/in_0 +(27 7) routing lc_trk_g3_2 <X> wire_con_box/lc_3/in_0 +(27 7) routing lc_trk_g3_4 <X> wire_con_box/lc_3/in_0 +(27 7) routing lc_trk_g3_6 <X> wire_con_box/lc_3/in_0 +(27 8) routing lc_trk_g1_0 <X> wire_con_box/lc_4/in_1 +(27 8) routing lc_trk_g1_2 <X> wire_con_box/lc_4/in_1 +(27 8) routing lc_trk_g1_4 <X> wire_con_box/lc_4/in_1 +(27 8) routing lc_trk_g1_6 <X> wire_con_box/lc_4/in_1 +(27 8) routing lc_trk_g3_0 <X> wire_con_box/lc_4/in_1 +(27 8) routing lc_trk_g3_2 <X> wire_con_box/lc_4/in_1 +(27 8) routing lc_trk_g3_4 <X> wire_con_box/lc_4/in_1 +(27 8) routing lc_trk_g3_6 <X> wire_con_box/lc_4/in_1 +(27 9) routing lc_trk_g1_1 <X> wire_con_box/lc_4/in_0 +(27 9) routing lc_trk_g1_3 <X> wire_con_box/lc_4/in_0 +(27 9) routing lc_trk_g1_5 <X> wire_con_box/lc_4/in_0 +(27 9) routing lc_trk_g1_7 <X> wire_con_box/lc_4/in_0 +(27 9) routing lc_trk_g3_1 <X> wire_con_box/lc_4/in_0 +(27 9) routing lc_trk_g3_3 <X> wire_con_box/lc_4/in_0 +(27 9) routing lc_trk_g3_5 <X> wire_con_box/lc_4/in_0 +(27 9) routing lc_trk_g3_7 <X> wire_con_box/lc_4/in_0 +(28 0) routing lc_trk_g2_1 <X> wire_con_box/lc_0/in_1 +(28 0) routing lc_trk_g2_3 <X> wire_con_box/lc_0/in_1 +(28 0) routing lc_trk_g2_5 <X> wire_con_box/lc_0/in_1 +(28 0) routing lc_trk_g2_7 <X> wire_con_box/lc_0/in_1 +(28 0) routing lc_trk_g3_0 <X> wire_con_box/lc_0/in_1 +(28 0) routing lc_trk_g3_2 <X> wire_con_box/lc_0/in_1 +(28 0) routing lc_trk_g3_4 <X> wire_con_box/lc_0/in_1 +(28 0) routing lc_trk_g3_6 <X> wire_con_box/lc_0/in_1 +(28 1) routing lc_trk_g2_0 <X> wire_con_box/lc_0/in_0 +(28 1) routing lc_trk_g2_2 <X> wire_con_box/lc_0/in_0 +(28 1) routing lc_trk_g2_4 <X> wire_con_box/lc_0/in_0 +(28 1) routing lc_trk_g2_6 <X> wire_con_box/lc_0/in_0 +(28 1) routing lc_trk_g3_1 <X> wire_con_box/lc_0/in_0 +(28 1) routing lc_trk_g3_3 <X> wire_con_box/lc_0/in_0 +(28 1) routing lc_trk_g3_5 <X> wire_con_box/lc_0/in_0 +(28 1) routing lc_trk_g3_7 <X> wire_con_box/lc_0/in_0 +(28 10) routing lc_trk_g2_0 <X> wire_con_box/lc_5/in_1 +(28 10) routing lc_trk_g2_2 <X> wire_con_box/lc_5/in_1 +(28 10) routing lc_trk_g2_4 <X> wire_con_box/lc_5/in_1 +(28 10) routing lc_trk_g2_6 <X> wire_con_box/lc_5/in_1 +(28 10) routing lc_trk_g3_1 <X> wire_con_box/lc_5/in_1 +(28 10) routing lc_trk_g3_3 <X> wire_con_box/lc_5/in_1 +(28 10) routing lc_trk_g3_5 <X> wire_con_box/lc_5/in_1 +(28 10) routing lc_trk_g3_7 <X> wire_con_box/lc_5/in_1 +(28 11) routing lc_trk_g2_1 <X> wire_con_box/lc_5/in_0 +(28 11) routing lc_trk_g2_3 <X> wire_con_box/lc_5/in_0 +(28 11) routing lc_trk_g2_5 <X> wire_con_box/lc_5/in_0 +(28 11) routing lc_trk_g2_7 <X> wire_con_box/lc_5/in_0 +(28 11) routing lc_trk_g3_0 <X> wire_con_box/lc_5/in_0 +(28 11) routing lc_trk_g3_2 <X> wire_con_box/lc_5/in_0 +(28 11) routing lc_trk_g3_4 <X> wire_con_box/lc_5/in_0 +(28 11) routing lc_trk_g3_6 <X> wire_con_box/lc_5/in_0 +(28 12) routing lc_trk_g2_1 <X> wire_con_box/lc_6/in_1 +(28 12) routing lc_trk_g2_3 <X> wire_con_box/lc_6/in_1 +(28 12) routing lc_trk_g2_5 <X> wire_con_box/lc_6/in_1 +(28 12) routing lc_trk_g2_7 <X> wire_con_box/lc_6/in_1 +(28 12) routing lc_trk_g3_0 <X> wire_con_box/lc_6/in_1 +(28 12) routing lc_trk_g3_2 <X> wire_con_box/lc_6/in_1 +(28 12) routing lc_trk_g3_4 <X> wire_con_box/lc_6/in_1 +(28 12) routing lc_trk_g3_6 <X> wire_con_box/lc_6/in_1 +(28 13) routing lc_trk_g2_0 <X> wire_con_box/lc_6/in_0 +(28 13) routing lc_trk_g2_2 <X> wire_con_box/lc_6/in_0 +(28 13) routing lc_trk_g2_4 <X> wire_con_box/lc_6/in_0 +(28 13) routing lc_trk_g2_6 <X> wire_con_box/lc_6/in_0 +(28 13) routing lc_trk_g3_1 <X> wire_con_box/lc_6/in_0 +(28 13) routing lc_trk_g3_3 <X> wire_con_box/lc_6/in_0 +(28 13) routing lc_trk_g3_5 <X> wire_con_box/lc_6/in_0 +(28 13) routing lc_trk_g3_7 <X> wire_con_box/lc_6/in_0 +(28 14) routing lc_trk_g2_0 <X> wire_con_box/lc_7/in_1 +(28 14) routing lc_trk_g2_2 <X> wire_con_box/lc_7/in_1 +(28 14) routing lc_trk_g2_4 <X> wire_con_box/lc_7/in_1 +(28 14) routing lc_trk_g2_6 <X> wire_con_box/lc_7/in_1 +(28 14) routing lc_trk_g3_1 <X> wire_con_box/lc_7/in_1 +(28 14) routing lc_trk_g3_3 <X> wire_con_box/lc_7/in_1 +(28 14) routing lc_trk_g3_5 <X> wire_con_box/lc_7/in_1 +(28 14) routing lc_trk_g3_7 <X> wire_con_box/lc_7/in_1 +(28 15) routing lc_trk_g2_1 <X> wire_con_box/lc_7/in_0 +(28 15) routing lc_trk_g2_3 <X> wire_con_box/lc_7/in_0 +(28 15) routing lc_trk_g2_5 <X> wire_con_box/lc_7/in_0 +(28 15) routing lc_trk_g2_7 <X> wire_con_box/lc_7/in_0 +(28 15) routing lc_trk_g3_0 <X> wire_con_box/lc_7/in_0 +(28 15) routing lc_trk_g3_2 <X> wire_con_box/lc_7/in_0 +(28 15) routing lc_trk_g3_4 <X> wire_con_box/lc_7/in_0 +(28 15) routing lc_trk_g3_6 <X> wire_con_box/lc_7/in_0 +(28 2) routing lc_trk_g2_0 <X> wire_con_box/lc_1/in_1 +(28 2) routing lc_trk_g2_2 <X> wire_con_box/lc_1/in_1 +(28 2) routing lc_trk_g2_4 <X> wire_con_box/lc_1/in_1 +(28 2) routing lc_trk_g2_6 <X> wire_con_box/lc_1/in_1 +(28 2) routing lc_trk_g3_1 <X> wire_con_box/lc_1/in_1 +(28 2) routing lc_trk_g3_3 <X> wire_con_box/lc_1/in_1 +(28 2) routing lc_trk_g3_5 <X> wire_con_box/lc_1/in_1 +(28 2) routing lc_trk_g3_7 <X> wire_con_box/lc_1/in_1 +(28 3) routing lc_trk_g2_1 <X> wire_con_box/lc_1/in_0 +(28 3) routing lc_trk_g2_3 <X> wire_con_box/lc_1/in_0 +(28 3) routing lc_trk_g2_5 <X> wire_con_box/lc_1/in_0 +(28 3) routing lc_trk_g2_7 <X> wire_con_box/lc_1/in_0 +(28 3) routing lc_trk_g3_0 <X> wire_con_box/lc_1/in_0 +(28 3) routing lc_trk_g3_2 <X> wire_con_box/lc_1/in_0 +(28 3) routing lc_trk_g3_4 <X> wire_con_box/lc_1/in_0 +(28 3) routing lc_trk_g3_6 <X> wire_con_box/lc_1/in_0 +(28 4) routing lc_trk_g2_1 <X> wire_con_box/lc_2/in_1 +(28 4) routing lc_trk_g2_3 <X> wire_con_box/lc_2/in_1 +(28 4) routing lc_trk_g2_5 <X> wire_con_box/lc_2/in_1 +(28 4) routing lc_trk_g2_7 <X> wire_con_box/lc_2/in_1 +(28 4) routing lc_trk_g3_0 <X> wire_con_box/lc_2/in_1 +(28 4) routing lc_trk_g3_2 <X> wire_con_box/lc_2/in_1 +(28 4) routing lc_trk_g3_4 <X> wire_con_box/lc_2/in_1 +(28 4) routing lc_trk_g3_6 <X> wire_con_box/lc_2/in_1 +(28 5) routing lc_trk_g2_0 <X> wire_con_box/lc_2/in_0 +(28 5) routing lc_trk_g2_2 <X> wire_con_box/lc_2/in_0 +(28 5) routing lc_trk_g2_4 <X> wire_con_box/lc_2/in_0 +(28 5) routing lc_trk_g2_6 <X> wire_con_box/lc_2/in_0 +(28 5) routing lc_trk_g3_1 <X> wire_con_box/lc_2/in_0 +(28 5) routing lc_trk_g3_3 <X> wire_con_box/lc_2/in_0 +(28 5) routing lc_trk_g3_5 <X> wire_con_box/lc_2/in_0 +(28 5) routing lc_trk_g3_7 <X> wire_con_box/lc_2/in_0 +(28 6) routing lc_trk_g2_0 <X> wire_con_box/lc_3/in_1 +(28 6) routing lc_trk_g2_2 <X> wire_con_box/lc_3/in_1 +(28 6) routing lc_trk_g2_4 <X> wire_con_box/lc_3/in_1 +(28 6) routing lc_trk_g2_6 <X> wire_con_box/lc_3/in_1 +(28 6) routing lc_trk_g3_1 <X> wire_con_box/lc_3/in_1 +(28 6) routing lc_trk_g3_3 <X> wire_con_box/lc_3/in_1 +(28 6) routing lc_trk_g3_5 <X> wire_con_box/lc_3/in_1 +(28 6) routing lc_trk_g3_7 <X> wire_con_box/lc_3/in_1 +(28 7) routing lc_trk_g2_1 <X> wire_con_box/lc_3/in_0 +(28 7) routing lc_trk_g2_3 <X> wire_con_box/lc_3/in_0 +(28 7) routing lc_trk_g2_5 <X> wire_con_box/lc_3/in_0 +(28 7) routing lc_trk_g2_7 <X> wire_con_box/lc_3/in_0 +(28 7) routing lc_trk_g3_0 <X> wire_con_box/lc_3/in_0 +(28 7) routing lc_trk_g3_2 <X> wire_con_box/lc_3/in_0 +(28 7) routing lc_trk_g3_4 <X> wire_con_box/lc_3/in_0 +(28 7) routing lc_trk_g3_6 <X> wire_con_box/lc_3/in_0 +(28 8) routing lc_trk_g2_1 <X> wire_con_box/lc_4/in_1 +(28 8) routing lc_trk_g2_3 <X> wire_con_box/lc_4/in_1 +(28 8) routing lc_trk_g2_5 <X> wire_con_box/lc_4/in_1 +(28 8) routing lc_trk_g2_7 <X> wire_con_box/lc_4/in_1 +(28 8) routing lc_trk_g3_0 <X> wire_con_box/lc_4/in_1 +(28 8) routing lc_trk_g3_2 <X> wire_con_box/lc_4/in_1 +(28 8) routing lc_trk_g3_4 <X> wire_con_box/lc_4/in_1 +(28 8) routing lc_trk_g3_6 <X> wire_con_box/lc_4/in_1 +(28 9) routing lc_trk_g2_0 <X> wire_con_box/lc_4/in_0 +(28 9) routing lc_trk_g2_2 <X> wire_con_box/lc_4/in_0 +(28 9) routing lc_trk_g2_4 <X> wire_con_box/lc_4/in_0 +(28 9) routing lc_trk_g2_6 <X> wire_con_box/lc_4/in_0 +(28 9) routing lc_trk_g3_1 <X> wire_con_box/lc_4/in_0 +(28 9) routing lc_trk_g3_3 <X> wire_con_box/lc_4/in_0 +(28 9) routing lc_trk_g3_5 <X> wire_con_box/lc_4/in_0 +(28 9) routing lc_trk_g3_7 <X> wire_con_box/lc_4/in_0 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g0_1 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g0_3 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g0_5 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g0_7 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g1_0 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g1_2 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g1_4 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g1_6 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g2_1 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g2_3 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g2_5 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g2_7 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g3_0 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g3_2 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g3_4 wire_con_box/lc_0/in_1 +(29 0) Enable bit of Mux _con_box/lcb1_0 => lc_trk_g3_6 wire_con_box/lc_0/in_1 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g0_0 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g0_2 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g0_4 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g0_6 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g1_1 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g1_3 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g1_5 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g1_7 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g2_0 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g2_2 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g2_4 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g2_6 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g3_1 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g3_3 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g3_5 wire_con_box/lc_0/in_0 +(29 1) Enable bit of Mux _con_box/lcb0_0 => lc_trk_g3_7 wire_con_box/lc_0/in_0 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g0_0 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g0_2 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g0_4 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g0_6 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g1_1 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g1_3 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g1_5 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g1_7 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g2_0 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g2_2 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g2_4 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g2_6 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g3_1 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g3_3 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g3_5 wire_con_box/lc_5/in_1 +(29 10) Enable bit of Mux _con_box/lcb1_5 => lc_trk_g3_7 wire_con_box/lc_5/in_1 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g0_1 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g0_3 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g0_5 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g0_7 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g1_0 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g1_2 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g1_4 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g1_6 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g2_1 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g2_3 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g2_5 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g2_7 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g3_0 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g3_2 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g3_4 wire_con_box/lc_5/in_0 +(29 11) Enable bit of Mux _con_box/lcb0_5 => lc_trk_g3_6 wire_con_box/lc_5/in_0 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g0_1 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g0_3 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g0_5 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g0_7 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g1_0 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g1_2 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g1_4 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g1_6 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g2_1 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g2_3 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g2_5 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g2_7 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g3_0 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g3_2 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g3_4 wire_con_box/lc_6/in_1 +(29 12) Enable bit of Mux _con_box/lcb1_6 => lc_trk_g3_6 wire_con_box/lc_6/in_1 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g0_0 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g0_2 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g0_4 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g0_6 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g1_1 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g1_3 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g1_5 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g1_7 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g2_0 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g2_2 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g2_4 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g2_6 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g3_1 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g3_3 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g3_5 wire_con_box/lc_6/in_0 +(29 13) Enable bit of Mux _con_box/lcb0_6 => lc_trk_g3_7 wire_con_box/lc_6/in_0 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g0_0 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g0_2 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g0_4 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g0_6 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g1_1 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g1_3 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g1_5 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g1_7 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g2_0 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g2_2 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g2_4 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g2_6 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g3_1 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g3_3 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g3_5 wire_con_box/lc_7/in_1 +(29 14) Enable bit of Mux _con_box/lcb1_7 => lc_trk_g3_7 wire_con_box/lc_7/in_1 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g0_1 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g0_3 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g0_5 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g0_7 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g1_0 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g1_2 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g1_4 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g1_6 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g2_1 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g2_3 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g2_5 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g2_7 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g3_0 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g3_2 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g3_4 wire_con_box/lc_7/in_0 +(29 15) Enable bit of Mux _con_box/lcb0_7 => lc_trk_g3_6 wire_con_box/lc_7/in_0 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g0_0 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g0_2 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g0_4 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g0_6 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g1_1 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g1_3 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g1_5 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g1_7 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g2_0 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g2_2 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g2_4 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g2_6 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g3_1 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g3_3 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g3_5 wire_con_box/lc_1/in_1 +(29 2) Enable bit of Mux _con_box/lcb1_1 => lc_trk_g3_7 wire_con_box/lc_1/in_1 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g0_1 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g0_3 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g0_5 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g0_7 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g1_0 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g1_2 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g1_4 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g1_6 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g2_1 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g2_3 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g2_5 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g2_7 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g3_0 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g3_2 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g3_4 wire_con_box/lc_1/in_0 +(29 3) Enable bit of Mux _con_box/lcb0_1 => lc_trk_g3_6 wire_con_box/lc_1/in_0 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g0_1 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g0_3 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g0_5 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g0_7 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g1_0 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g1_2 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g1_4 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g1_6 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g2_1 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g2_3 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g2_5 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g2_7 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g3_0 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g3_2 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g3_4 wire_con_box/lc_2/in_1 +(29 4) Enable bit of Mux _con_box/lcb1_2 => lc_trk_g3_6 wire_con_box/lc_2/in_1 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g0_0 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g0_2 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g0_4 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g0_6 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g1_1 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g1_3 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g1_5 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g1_7 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g2_0 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g2_2 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g2_4 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g2_6 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g3_1 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g3_3 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g3_5 wire_con_box/lc_2/in_0 +(29 5) Enable bit of Mux _con_box/lcb0_2 => lc_trk_g3_7 wire_con_box/lc_2/in_0 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g0_0 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g0_2 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g0_4 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g0_6 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g1_1 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g1_3 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g1_5 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g1_7 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g2_0 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g2_2 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g2_4 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g2_6 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g3_1 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g3_3 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g3_5 wire_con_box/lc_3/in_1 +(29 6) Enable bit of Mux _con_box/lcb1_3 => lc_trk_g3_7 wire_con_box/lc_3/in_1 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g0_1 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g0_3 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g0_5 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g0_7 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g1_0 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g1_2 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g1_4 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g1_6 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g2_1 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g2_3 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g2_5 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g2_7 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g3_0 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g3_2 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g3_4 wire_con_box/lc_3/in_0 +(29 7) Enable bit of Mux _con_box/lcb0_3 => lc_trk_g3_6 wire_con_box/lc_3/in_0 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g0_1 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g0_3 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g0_5 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g0_7 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g1_0 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g1_2 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g1_4 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g1_6 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g2_1 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g2_3 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g2_5 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g2_7 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g3_0 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g3_2 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g3_4 wire_con_box/lc_4/in_1 +(29 8) Enable bit of Mux _con_box/lcb1_4 => lc_trk_g3_6 wire_con_box/lc_4/in_1 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g0_0 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g0_2 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g0_4 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g0_6 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g1_1 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g1_3 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g1_5 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g1_7 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g2_0 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g2_2 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g2_4 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g2_6 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g3_1 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g3_3 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g3_5 wire_con_box/lc_4/in_0 +(29 9) Enable bit of Mux _con_box/lcb0_4 => lc_trk_g3_7 wire_con_box/lc_4/in_0 +(3 0) routing sp12_h_r_0 <X> sp12_v_b_0 +(3 0) routing sp12_v_t_23 <X> sp12_v_b_0 +(3 1) routing sp12_h_l_23 <X> sp12_v_b_0 +(3 1) routing sp12_h_r_0 <X> sp12_v_b_0 +(3 10) routing sp12_v_t_22 <X> sp12_h_l_22 +(3 11) routing sp12_v_b_1 <X> sp12_h_l_22 +(3 12) routing sp12_v_b_1 <X> sp12_h_r_1 +(3 12) routing sp12_v_t_22 <X> sp12_h_r_1 +(3 13) routing sp12_h_l_22 <X> sp12_h_r_1 +(3 13) routing sp12_v_b_1 <X> sp12_h_r_1 +(3 14) routing sp12_h_r_1 <X> sp12_v_t_22 +(3 14) routing sp12_v_b_1 <X> sp12_v_t_22 +(3 15) routing sp12_h_l_22 <X> sp12_v_t_22 +(3 15) routing sp12_h_r_1 <X> sp12_v_t_22 +(3 2) routing sp12_h_r_0 <X> sp12_h_l_23 +(3 2) routing sp12_v_t_23 <X> sp12_h_l_23 +(3 3) routing sp12_h_r_0 <X> sp12_h_l_23 +(3 3) routing sp12_v_b_0 <X> sp12_h_l_23 +(3 4) routing sp12_v_b_0 <X> sp12_h_r_0 +(3 4) routing sp12_v_t_23 <X> sp12_h_r_0 +(3 5) routing sp12_h_l_23 <X> sp12_h_r_0 +(3 5) routing sp12_v_b_0 <X> sp12_h_r_0 +(3 6) routing sp12_h_r_0 <X> sp12_v_t_23 +(3 6) routing sp12_v_b_0 <X> sp12_v_t_23 +(3 7) routing sp12_h_l_23 <X> sp12_v_t_23 +(3 7) routing sp12_h_r_0 <X> sp12_v_t_23 +(3 8) routing sp12_h_r_1 <X> sp12_v_b_1 +(3 8) routing sp12_v_t_22 <X> sp12_v_b_1 +(3 9) routing sp12_h_l_22 <X> sp12_v_b_1 +(3 9) routing sp12_h_r_1 <X> sp12_v_b_1 +(30 0) routing lc_trk_g0_5 <X> wire_con_box/lc_0/in_1 +(30 0) routing lc_trk_g0_7 <X> wire_con_box/lc_0/in_1 +(30 0) routing lc_trk_g1_4 <X> wire_con_box/lc_0/in_1 +(30 0) routing lc_trk_g1_6 <X> wire_con_box/lc_0/in_1 +(30 0) routing lc_trk_g2_5 <X> wire_con_box/lc_0/in_1 +(30 0) routing lc_trk_g2_7 <X> wire_con_box/lc_0/in_1 +(30 0) routing lc_trk_g3_4 <X> wire_con_box/lc_0/in_1 +(30 0) routing lc_trk_g3_6 <X> wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g0_3 <X> wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g0_7 <X> wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g1_2 <X> wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g1_6 <X> wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g2_3 <X> wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g2_7 <X> wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g3_2 <X> wire_con_box/lc_0/in_1 +(30 1) routing lc_trk_g3_6 <X> wire_con_box/lc_0/in_1 +(30 10) routing lc_trk_g0_4 <X> wire_con_box/lc_5/in_1 +(30 10) routing lc_trk_g0_6 <X> wire_con_box/lc_5/in_1 +(30 10) routing lc_trk_g1_5 <X> wire_con_box/lc_5/in_1 +(30 10) routing lc_trk_g1_7 <X> wire_con_box/lc_5/in_1 +(30 10) routing lc_trk_g2_4 <X> wire_con_box/lc_5/in_1 +(30 10) routing lc_trk_g2_6 <X> wire_con_box/lc_5/in_1 +(30 10) routing lc_trk_g3_5 <X> wire_con_box/lc_5/in_1 +(30 10) routing lc_trk_g3_7 <X> wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g0_2 <X> wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g0_6 <X> wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g1_3 <X> wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g1_7 <X> wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g2_2 <X> wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g2_6 <X> wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g3_3 <X> wire_con_box/lc_5/in_1 +(30 11) routing lc_trk_g3_7 <X> wire_con_box/lc_5/in_1 +(30 12) routing lc_trk_g0_5 <X> wire_con_box/lc_6/in_1 +(30 12) routing lc_trk_g0_7 <X> wire_con_box/lc_6/in_1 +(30 12) routing lc_trk_g1_4 <X> wire_con_box/lc_6/in_1 +(30 12) routing lc_trk_g1_6 <X> wire_con_box/lc_6/in_1 +(30 12) routing lc_trk_g2_5 <X> wire_con_box/lc_6/in_1 +(30 12) routing lc_trk_g2_7 <X> wire_con_box/lc_6/in_1 +(30 12) routing lc_trk_g3_4 <X> wire_con_box/lc_6/in_1 +(30 12) routing lc_trk_g3_6 <X> wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g0_3 <X> wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g0_7 <X> wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g1_2 <X> wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g1_6 <X> wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g2_3 <X> wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g2_7 <X> wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g3_2 <X> wire_con_box/lc_6/in_1 +(30 13) routing lc_trk_g3_6 <X> wire_con_box/lc_6/in_1 +(30 14) routing lc_trk_g0_4 <X> wire_con_box/lc_7/in_1 +(30 14) routing lc_trk_g0_6 <X> wire_con_box/lc_7/in_1 +(30 14) routing lc_trk_g1_5 <X> wire_con_box/lc_7/in_1 +(30 14) routing lc_trk_g1_7 <X> wire_con_box/lc_7/in_1 +(30 14) routing lc_trk_g2_4 <X> wire_con_box/lc_7/in_1 +(30 14) routing lc_trk_g2_6 <X> wire_con_box/lc_7/in_1 +(30 14) routing lc_trk_g3_5 <X> wire_con_box/lc_7/in_1 +(30 14) routing lc_trk_g3_7 <X> wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g0_2 <X> wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g0_6 <X> wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g1_3 <X> wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g1_7 <X> wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g2_2 <X> wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g2_6 <X> wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g3_3 <X> wire_con_box/lc_7/in_1 +(30 15) routing lc_trk_g3_7 <X> wire_con_box/lc_7/in_1 +(30 2) routing lc_trk_g0_4 <X> wire_con_box/lc_1/in_1 +(30 2) routing lc_trk_g0_6 <X> wire_con_box/lc_1/in_1 +(30 2) routing lc_trk_g1_5 <X> wire_con_box/lc_1/in_1 +(30 2) routing lc_trk_g1_7 <X> wire_con_box/lc_1/in_1 +(30 2) routing lc_trk_g2_4 <X> wire_con_box/lc_1/in_1 +(30 2) routing lc_trk_g2_6 <X> wire_con_box/lc_1/in_1 +(30 2) routing lc_trk_g3_5 <X> wire_con_box/lc_1/in_1 +(30 2) routing lc_trk_g3_7 <X> wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g0_2 <X> wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g0_6 <X> wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g1_3 <X> wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g1_7 <X> wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g2_2 <X> wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g2_6 <X> wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g3_3 <X> wire_con_box/lc_1/in_1 +(30 3) routing lc_trk_g3_7 <X> wire_con_box/lc_1/in_1 +(30 4) routing lc_trk_g0_5 <X> wire_con_box/lc_2/in_1 +(30 4) routing lc_trk_g0_7 <X> wire_con_box/lc_2/in_1 +(30 4) routing lc_trk_g1_4 <X> wire_con_box/lc_2/in_1 +(30 4) routing lc_trk_g1_6 <X> wire_con_box/lc_2/in_1 +(30 4) routing lc_trk_g2_5 <X> wire_con_box/lc_2/in_1 +(30 4) routing lc_trk_g2_7 <X> wire_con_box/lc_2/in_1 +(30 4) routing lc_trk_g3_4 <X> wire_con_box/lc_2/in_1 +(30 4) routing lc_trk_g3_6 <X> wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g0_3 <X> wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g0_7 <X> wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g1_2 <X> wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g1_6 <X> wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g2_3 <X> wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g2_7 <X> wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g3_2 <X> wire_con_box/lc_2/in_1 +(30 5) routing lc_trk_g3_6 <X> wire_con_box/lc_2/in_1 +(30 6) routing lc_trk_g0_4 <X> wire_con_box/lc_3/in_1 +(30 6) routing lc_trk_g0_6 <X> wire_con_box/lc_3/in_1 +(30 6) routing lc_trk_g1_5 <X> wire_con_box/lc_3/in_1 +(30 6) routing lc_trk_g1_7 <X> wire_con_box/lc_3/in_1 +(30 6) routing lc_trk_g2_4 <X> wire_con_box/lc_3/in_1 +(30 6) routing lc_trk_g2_6 <X> wire_con_box/lc_3/in_1 +(30 6) routing lc_trk_g3_5 <X> wire_con_box/lc_3/in_1 +(30 6) routing lc_trk_g3_7 <X> wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g0_2 <X> wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g0_6 <X> wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g1_3 <X> wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g1_7 <X> wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g2_2 <X> wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g2_6 <X> wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g3_3 <X> wire_con_box/lc_3/in_1 +(30 7) routing lc_trk_g3_7 <X> wire_con_box/lc_3/in_1 +(30 8) routing lc_trk_g0_5 <X> wire_con_box/lc_4/in_1 +(30 8) routing lc_trk_g0_7 <X> wire_con_box/lc_4/in_1 +(30 8) routing lc_trk_g1_4 <X> wire_con_box/lc_4/in_1 +(30 8) routing lc_trk_g1_6 <X> wire_con_box/lc_4/in_1 +(30 8) routing lc_trk_g2_5 <X> wire_con_box/lc_4/in_1 +(30 8) routing lc_trk_g2_7 <X> wire_con_box/lc_4/in_1 +(30 8) routing lc_trk_g3_4 <X> wire_con_box/lc_4/in_1 +(30 8) routing lc_trk_g3_6 <X> wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g0_3 <X> wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g0_7 <X> wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g1_2 <X> wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g1_6 <X> wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g2_3 <X> wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g2_7 <X> wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g3_2 <X> wire_con_box/lc_4/in_1 +(30 9) routing lc_trk_g3_6 <X> wire_con_box/lc_4/in_1 +(31 0) routing lc_trk_g0_5 <X> wire_con_box/lc_0/in_3 +(31 0) routing lc_trk_g0_7 <X> wire_con_box/lc_0/in_3 +(31 0) routing lc_trk_g1_4 <X> wire_con_box/lc_0/in_3 +(31 0) routing lc_trk_g1_6 <X> wire_con_box/lc_0/in_3 +(31 0) routing lc_trk_g2_5 <X> wire_con_box/lc_0/in_3 +(31 0) routing lc_trk_g2_7 <X> wire_con_box/lc_0/in_3 +(31 0) routing lc_trk_g3_4 <X> wire_con_box/lc_0/in_3 +(31 0) routing lc_trk_g3_6 <X> wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g0_3 <X> wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g0_7 <X> wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g1_2 <X> wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g1_6 <X> wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g2_3 <X> wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g2_7 <X> wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g3_2 <X> wire_con_box/lc_0/in_3 +(31 1) routing lc_trk_g3_6 <X> wire_con_box/lc_0/in_3 +(31 10) routing lc_trk_g0_4 <X> wire_con_box/lc_5/in_3 +(31 10) routing lc_trk_g0_6 <X> wire_con_box/lc_5/in_3 +(31 10) routing lc_trk_g1_5 <X> wire_con_box/lc_5/in_3 +(31 10) routing lc_trk_g1_7 <X> wire_con_box/lc_5/in_3 +(31 10) routing lc_trk_g2_4 <X> wire_con_box/lc_5/in_3 +(31 10) routing lc_trk_g2_6 <X> wire_con_box/lc_5/in_3 +(31 10) routing lc_trk_g3_5 <X> wire_con_box/lc_5/in_3 +(31 10) routing lc_trk_g3_7 <X> wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g0_2 <X> wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g0_6 <X> wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g1_3 <X> wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g1_7 <X> wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g2_2 <X> wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g2_6 <X> wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g3_3 <X> wire_con_box/lc_5/in_3 +(31 11) routing lc_trk_g3_7 <X> wire_con_box/lc_5/in_3 +(31 12) routing lc_trk_g0_5 <X> wire_con_box/lc_6/in_3 +(31 12) routing lc_trk_g0_7 <X> wire_con_box/lc_6/in_3 +(31 12) routing lc_trk_g1_4 <X> wire_con_box/lc_6/in_3 +(31 12) routing lc_trk_g1_6 <X> wire_con_box/lc_6/in_3 +(31 12) routing lc_trk_g2_5 <X> wire_con_box/lc_6/in_3 +(31 12) routing lc_trk_g2_7 <X> wire_con_box/lc_6/in_3 +(31 12) routing lc_trk_g3_4 <X> wire_con_box/lc_6/in_3 +(31 12) routing lc_trk_g3_6 <X> wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g0_3 <X> wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g0_7 <X> wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g1_2 <X> wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g1_6 <X> wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g2_3 <X> wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g2_7 <X> wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g3_2 <X> wire_con_box/lc_6/in_3 +(31 13) routing lc_trk_g3_6 <X> wire_con_box/lc_6/in_3 +(31 14) routing lc_trk_g0_4 <X> wire_con_box/lc_7/in_3 +(31 14) routing lc_trk_g0_6 <X> wire_con_box/lc_7/in_3 +(31 14) routing lc_trk_g1_5 <X> wire_con_box/lc_7/in_3 +(31 14) routing lc_trk_g1_7 <X> wire_con_box/lc_7/in_3 +(31 14) routing lc_trk_g2_4 <X> wire_con_box/lc_7/in_3 +(31 14) routing lc_trk_g2_6 <X> wire_con_box/lc_7/in_3 +(31 14) routing lc_trk_g3_5 <X> wire_con_box/lc_7/in_3 +(31 14) routing lc_trk_g3_7 <X> wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g0_2 <X> wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g0_6 <X> wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g1_3 <X> wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g1_7 <X> wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g2_2 <X> wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g2_6 <X> wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g3_3 <X> wire_con_box/lc_7/in_3 +(31 15) routing lc_trk_g3_7 <X> wire_con_box/lc_7/in_3 +(31 2) routing lc_trk_g0_4 <X> wire_con_box/lc_1/in_3 +(31 2) routing lc_trk_g0_6 <X> wire_con_box/lc_1/in_3 +(31 2) routing lc_trk_g1_5 <X> wire_con_box/lc_1/in_3 +(31 2) routing lc_trk_g1_7 <X> wire_con_box/lc_1/in_3 +(31 2) routing lc_trk_g2_4 <X> wire_con_box/lc_1/in_3 +(31 2) routing lc_trk_g2_6 <X> wire_con_box/lc_1/in_3 +(31 2) routing lc_trk_g3_5 <X> wire_con_box/lc_1/in_3 +(31 2) routing lc_trk_g3_7 <X> wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g0_2 <X> wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g0_6 <X> wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g1_3 <X> wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g1_7 <X> wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g2_2 <X> wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g2_6 <X> wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g3_3 <X> wire_con_box/lc_1/in_3 +(31 3) routing lc_trk_g3_7 <X> wire_con_box/lc_1/in_3 +(31 4) routing lc_trk_g0_5 <X> wire_con_box/lc_2/in_3 +(31 4) routing lc_trk_g0_7 <X> wire_con_box/lc_2/in_3 +(31 4) routing lc_trk_g1_4 <X> wire_con_box/lc_2/in_3 +(31 4) routing lc_trk_g1_6 <X> wire_con_box/lc_2/in_3 +(31 4) routing lc_trk_g2_5 <X> wire_con_box/lc_2/in_3 +(31 4) routing lc_trk_g2_7 <X> wire_con_box/lc_2/in_3 +(31 4) routing lc_trk_g3_4 <X> wire_con_box/lc_2/in_3 +(31 4) routing lc_trk_g3_6 <X> wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g0_3 <X> wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g0_7 <X> wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g1_2 <X> wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g1_6 <X> wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g2_3 <X> wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g2_7 <X> wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g3_2 <X> wire_con_box/lc_2/in_3 +(31 5) routing lc_trk_g3_6 <X> wire_con_box/lc_2/in_3 +(31 6) routing lc_trk_g0_4 <X> wire_con_box/lc_3/in_3 +(31 6) routing lc_trk_g0_6 <X> wire_con_box/lc_3/in_3 +(31 6) routing lc_trk_g1_5 <X> wire_con_box/lc_3/in_3 +(31 6) routing lc_trk_g1_7 <X> wire_con_box/lc_3/in_3 +(31 6) routing lc_trk_g2_4 <X> wire_con_box/lc_3/in_3 +(31 6) routing lc_trk_g2_6 <X> wire_con_box/lc_3/in_3 +(31 6) routing lc_trk_g3_5 <X> wire_con_box/lc_3/in_3 +(31 6) routing lc_trk_g3_7 <X> wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g0_2 <X> wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g0_6 <X> wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g1_3 <X> wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g1_7 <X> wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g2_2 <X> wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g2_6 <X> wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g3_3 <X> wire_con_box/lc_3/in_3 +(31 7) routing lc_trk_g3_7 <X> wire_con_box/lc_3/in_3 +(31 8) routing lc_trk_g0_5 <X> wire_con_box/lc_4/in_3 +(31 8) routing lc_trk_g0_7 <X> wire_con_box/lc_4/in_3 +(31 8) routing lc_trk_g1_4 <X> wire_con_box/lc_4/in_3 +(31 8) routing lc_trk_g1_6 <X> wire_con_box/lc_4/in_3 +(31 8) routing lc_trk_g2_5 <X> wire_con_box/lc_4/in_3 +(31 8) routing lc_trk_g2_7 <X> wire_con_box/lc_4/in_3 +(31 8) routing lc_trk_g3_4 <X> wire_con_box/lc_4/in_3 +(31 8) routing lc_trk_g3_6 <X> wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g0_3 <X> wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g0_7 <X> wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g1_2 <X> wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g1_6 <X> wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g2_3 <X> wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g2_7 <X> wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g3_2 <X> wire_con_box/lc_4/in_3 +(31 9) routing lc_trk_g3_6 <X> wire_con_box/lc_4/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g0_3 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g0_5 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g0_7 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g1_0 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g1_2 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g1_4 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g1_6 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g2_1 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g2_3 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g2_5 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g2_7 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g3_0 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g3_2 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g3_4 wire_con_box/lc_0/in_3 +(32 0) Enable bit of Mux _con_box/lcb3_0 => lc_trk_g3_6 wire_con_box/lc_0/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g0_2 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g0_4 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g0_6 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g1_1 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g1_3 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g1_5 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g1_7 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g2_0 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g2_2 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g2_4 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g2_6 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g3_1 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g3_3 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g3_5 wire_con_box/lc_5/in_3 +(32 10) Enable bit of Mux _con_box/lcb3_5 => lc_trk_g3_7 wire_con_box/lc_5/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g0_3 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g0_5 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g0_7 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g1_0 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g1_2 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g1_4 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g1_6 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g2_1 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g2_3 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g2_5 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g2_7 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g3_0 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g3_2 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g3_4 wire_con_box/lc_6/in_3 +(32 12) Enable bit of Mux _con_box/lcb3_6 => lc_trk_g3_6 wire_con_box/lc_6/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g0_2 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g0_4 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g0_6 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g1_1 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g1_3 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g1_5 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g1_7 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g2_0 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g2_2 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g2_4 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g2_6 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g3_1 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g3_3 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g3_5 wire_con_box/lc_7/in_3 +(32 14) Enable bit of Mux _con_box/lcb3_7 => lc_trk_g3_7 wire_con_box/lc_7/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g0_2 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g0_4 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g0_6 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g1_1 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g1_3 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g1_5 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g1_7 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g2_0 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g2_2 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g2_4 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g2_6 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g3_1 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g3_3 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g3_5 wire_con_box/lc_1/in_3 +(32 2) Enable bit of Mux _con_box/lcb3_1 => lc_trk_g3_7 wire_con_box/lc_1/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g0_3 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g0_5 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g0_7 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g1_0 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g1_2 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g1_4 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g1_6 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g2_1 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g2_3 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g2_5 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g2_7 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g3_0 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g3_2 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g3_4 wire_con_box/lc_2/in_3 +(32 4) Enable bit of Mux _con_box/lcb3_2 => lc_trk_g3_6 wire_con_box/lc_2/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g0_2 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g0_4 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g0_6 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g1_1 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g1_3 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g1_5 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g1_7 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g2_0 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g2_2 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g2_4 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g2_6 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g3_1 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g3_3 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g3_5 wire_con_box/lc_3/in_3 +(32 6) Enable bit of Mux _con_box/lcb3_3 => lc_trk_g3_7 wire_con_box/lc_3/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g0_3 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g0_5 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g0_7 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g1_0 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g1_2 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g1_4 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g1_6 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g2_1 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g2_3 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g2_5 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g2_7 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g3_0 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g3_2 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g3_4 wire_con_box/lc_4/in_3 +(32 8) Enable bit of Mux _con_box/lcb3_4 => lc_trk_g3_6 wire_con_box/lc_4/in_3 +(33 0) routing lc_trk_g2_1 <X> wire_con_box/lc_0/in_3 +(33 0) routing lc_trk_g2_3 <X> wire_con_box/lc_0/in_3 +(33 0) routing lc_trk_g2_5 <X> wire_con_box/lc_0/in_3 +(33 0) routing lc_trk_g2_7 <X> wire_con_box/lc_0/in_3 +(33 0) routing lc_trk_g3_0 <X> wire_con_box/lc_0/in_3 +(33 0) routing lc_trk_g3_2 <X> wire_con_box/lc_0/in_3 +(33 0) routing lc_trk_g3_4 <X> wire_con_box/lc_0/in_3 +(33 0) routing lc_trk_g3_6 <X> wire_con_box/lc_0/in_3 +(33 10) routing lc_trk_g2_0 <X> wire_con_box/lc_5/in_3 +(33 10) routing lc_trk_g2_2 <X> wire_con_box/lc_5/in_3 +(33 10) routing lc_trk_g2_4 <X> wire_con_box/lc_5/in_3 +(33 10) routing lc_trk_g2_6 <X> wire_con_box/lc_5/in_3 +(33 10) routing lc_trk_g3_1 <X> wire_con_box/lc_5/in_3 +(33 10) routing lc_trk_g3_3 <X> wire_con_box/lc_5/in_3 +(33 10) routing lc_trk_g3_5 <X> wire_con_box/lc_5/in_3 +(33 10) routing lc_trk_g3_7 <X> wire_con_box/lc_5/in_3 +(33 12) routing lc_trk_g2_1 <X> wire_con_box/lc_6/in_3 +(33 12) routing lc_trk_g2_3 <X> wire_con_box/lc_6/in_3 +(33 12) routing lc_trk_g2_5 <X> wire_con_box/lc_6/in_3 +(33 12) routing lc_trk_g2_7 <X> wire_con_box/lc_6/in_3 +(33 12) routing lc_trk_g3_0 <X> wire_con_box/lc_6/in_3 +(33 12) routing lc_trk_g3_2 <X> wire_con_box/lc_6/in_3 +(33 12) routing lc_trk_g3_4 <X> wire_con_box/lc_6/in_3 +(33 12) routing lc_trk_g3_6 <X> wire_con_box/lc_6/in_3 +(33 14) routing lc_trk_g2_0 <X> wire_con_box/lc_7/in_3 +(33 14) routing lc_trk_g2_2 <X> wire_con_box/lc_7/in_3 +(33 14) routing lc_trk_g2_4 <X> wire_con_box/lc_7/in_3 +(33 14) routing lc_trk_g2_6 <X> wire_con_box/lc_7/in_3 +(33 14) routing lc_trk_g3_1 <X> wire_con_box/lc_7/in_3 +(33 14) routing lc_trk_g3_3 <X> wire_con_box/lc_7/in_3 +(33 14) routing lc_trk_g3_5 <X> wire_con_box/lc_7/in_3 +(33 14) routing lc_trk_g3_7 <X> wire_con_box/lc_7/in_3 +(33 2) routing lc_trk_g2_0 <X> wire_con_box/lc_1/in_3 +(33 2) routing lc_trk_g2_2 <X> wire_con_box/lc_1/in_3 +(33 2) routing lc_trk_g2_4 <X> wire_con_box/lc_1/in_3 +(33 2) routing lc_trk_g2_6 <X> wire_con_box/lc_1/in_3 +(33 2) routing lc_trk_g3_1 <X> wire_con_box/lc_1/in_3 +(33 2) routing lc_trk_g3_3 <X> wire_con_box/lc_1/in_3 +(33 2) routing lc_trk_g3_5 <X> wire_con_box/lc_1/in_3 +(33 2) routing lc_trk_g3_7 <X> wire_con_box/lc_1/in_3 +(33 4) routing lc_trk_g2_1 <X> wire_con_box/lc_2/in_3 +(33 4) routing lc_trk_g2_3 <X> wire_con_box/lc_2/in_3 +(33 4) routing lc_trk_g2_5 <X> wire_con_box/lc_2/in_3 +(33 4) routing lc_trk_g2_7 <X> wire_con_box/lc_2/in_3 +(33 4) routing lc_trk_g3_0 <X> wire_con_box/lc_2/in_3 +(33 4) routing lc_trk_g3_2 <X> wire_con_box/lc_2/in_3 +(33 4) routing lc_trk_g3_4 <X> wire_con_box/lc_2/in_3 +(33 4) routing lc_trk_g3_6 <X> wire_con_box/lc_2/in_3 +(33 6) routing lc_trk_g2_0 <X> wire_con_box/lc_3/in_3 +(33 6) routing lc_trk_g2_2 <X> wire_con_box/lc_3/in_3 +(33 6) routing lc_trk_g2_4 <X> wire_con_box/lc_3/in_3 +(33 6) routing lc_trk_g2_6 <X> wire_con_box/lc_3/in_3 +(33 6) routing lc_trk_g3_1 <X> wire_con_box/lc_3/in_3 +(33 6) routing lc_trk_g3_3 <X> wire_con_box/lc_3/in_3 +(33 6) routing lc_trk_g3_5 <X> wire_con_box/lc_3/in_3 +(33 6) routing lc_trk_g3_7 <X> wire_con_box/lc_3/in_3 +(33 8) routing lc_trk_g2_1 <X> wire_con_box/lc_4/in_3 +(33 8) routing lc_trk_g2_3 <X> wire_con_box/lc_4/in_3 +(33 8) routing lc_trk_g2_5 <X> wire_con_box/lc_4/in_3 +(33 8) routing lc_trk_g2_7 <X> wire_con_box/lc_4/in_3 +(33 8) routing lc_trk_g3_0 <X> wire_con_box/lc_4/in_3 +(33 8) routing lc_trk_g3_2 <X> wire_con_box/lc_4/in_3 +(33 8) routing lc_trk_g3_4 <X> wire_con_box/lc_4/in_3 +(33 8) routing lc_trk_g3_6 <X> wire_con_box/lc_4/in_3 +(34 0) routing lc_trk_g1_0 <X> wire_con_box/lc_0/in_3 +(34 0) routing lc_trk_g1_2 <X> wire_con_box/lc_0/in_3 +(34 0) routing lc_trk_g1_4 <X> wire_con_box/lc_0/in_3 +(34 0) routing lc_trk_g1_6 <X> wire_con_box/lc_0/in_3 +(34 0) routing lc_trk_g3_0 <X> wire_con_box/lc_0/in_3 +(34 0) routing lc_trk_g3_2 <X> wire_con_box/lc_0/in_3 +(34 0) routing lc_trk_g3_4 <X> wire_con_box/lc_0/in_3 +(34 0) routing lc_trk_g3_6 <X> wire_con_box/lc_0/in_3 +(34 10) routing lc_trk_g1_1 <X> wire_con_box/lc_5/in_3 +(34 10) routing lc_trk_g1_3 <X> wire_con_box/lc_5/in_3 +(34 10) routing lc_trk_g1_5 <X> wire_con_box/lc_5/in_3 +(34 10) routing lc_trk_g1_7 <X> wire_con_box/lc_5/in_3 +(34 10) routing lc_trk_g3_1 <X> wire_con_box/lc_5/in_3 +(34 10) routing lc_trk_g3_3 <X> wire_con_box/lc_5/in_3 +(34 10) routing lc_trk_g3_5 <X> wire_con_box/lc_5/in_3 +(34 10) routing lc_trk_g3_7 <X> wire_con_box/lc_5/in_3 +(34 12) routing lc_trk_g1_0 <X> wire_con_box/lc_6/in_3 +(34 12) routing lc_trk_g1_2 <X> wire_con_box/lc_6/in_3 +(34 12) routing lc_trk_g1_4 <X> wire_con_box/lc_6/in_3 +(34 12) routing lc_trk_g1_6 <X> wire_con_box/lc_6/in_3 +(34 12) routing lc_trk_g3_0 <X> wire_con_box/lc_6/in_3 +(34 12) routing lc_trk_g3_2 <X> wire_con_box/lc_6/in_3 +(34 12) routing lc_trk_g3_4 <X> wire_con_box/lc_6/in_3 +(34 12) routing lc_trk_g3_6 <X> wire_con_box/lc_6/in_3 +(34 14) routing lc_trk_g1_1 <X> wire_con_box/lc_7/in_3 +(34 14) routing lc_trk_g1_3 <X> wire_con_box/lc_7/in_3 +(34 14) routing lc_trk_g1_5 <X> wire_con_box/lc_7/in_3 +(34 14) routing lc_trk_g1_7 <X> wire_con_box/lc_7/in_3 +(34 14) routing lc_trk_g3_1 <X> wire_con_box/lc_7/in_3 +(34 14) routing lc_trk_g3_3 <X> wire_con_box/lc_7/in_3 +(34 14) routing lc_trk_g3_5 <X> wire_con_box/lc_7/in_3 +(34 14) routing lc_trk_g3_7 <X> wire_con_box/lc_7/in_3 +(34 2) routing lc_trk_g1_1 <X> wire_con_box/lc_1/in_3 +(34 2) routing lc_trk_g1_3 <X> wire_con_box/lc_1/in_3 +(34 2) routing lc_trk_g1_5 <X> wire_con_box/lc_1/in_3 +(34 2) routing lc_trk_g1_7 <X> wire_con_box/lc_1/in_3 +(34 2) routing lc_trk_g3_1 <X> wire_con_box/lc_1/in_3 +(34 2) routing lc_trk_g3_3 <X> wire_con_box/lc_1/in_3 +(34 2) routing lc_trk_g3_5 <X> wire_con_box/lc_1/in_3 +(34 2) routing lc_trk_g3_7 <X> wire_con_box/lc_1/in_3 +(34 4) routing lc_trk_g1_0 <X> wire_con_box/lc_2/in_3 +(34 4) routing lc_trk_g1_2 <X> wire_con_box/lc_2/in_3 +(34 4) routing lc_trk_g1_4 <X> wire_con_box/lc_2/in_3 +(34 4) routing lc_trk_g1_6 <X> wire_con_box/lc_2/in_3 +(34 4) routing lc_trk_g3_0 <X> wire_con_box/lc_2/in_3 +(34 4) routing lc_trk_g3_2 <X> wire_con_box/lc_2/in_3 +(34 4) routing lc_trk_g3_4 <X> wire_con_box/lc_2/in_3 +(34 4) routing lc_trk_g3_6 <X> wire_con_box/lc_2/in_3 +(34 6) routing lc_trk_g1_1 <X> wire_con_box/lc_3/in_3 +(34 6) routing lc_trk_g1_3 <X> wire_con_box/lc_3/in_3 +(34 6) routing lc_trk_g1_5 <X> wire_con_box/lc_3/in_3 +(34 6) routing lc_trk_g1_7 <X> wire_con_box/lc_3/in_3 +(34 6) routing lc_trk_g3_1 <X> wire_con_box/lc_3/in_3 +(34 6) routing lc_trk_g3_3 <X> wire_con_box/lc_3/in_3 +(34 6) routing lc_trk_g3_5 <X> wire_con_box/lc_3/in_3 +(34 6) routing lc_trk_g3_7 <X> wire_con_box/lc_3/in_3 +(34 8) routing lc_trk_g1_0 <X> wire_con_box/lc_4/in_3 +(34 8) routing lc_trk_g1_2 <X> wire_con_box/lc_4/in_3 +(34 8) routing lc_trk_g1_4 <X> wire_con_box/lc_4/in_3 +(34 8) routing lc_trk_g1_6 <X> wire_con_box/lc_4/in_3 +(34 8) routing lc_trk_g3_0 <X> wire_con_box/lc_4/in_3 +(34 8) routing lc_trk_g3_2 <X> wire_con_box/lc_4/in_3 +(34 8) routing lc_trk_g3_4 <X> wire_con_box/lc_4/in_3 +(34 8) routing lc_trk_g3_6 <X> wire_con_box/lc_4/in_3 +(36 0) LC_0 Logic Functioning bit +(36 1) LC_0 Logic Functioning bit +(36 10) LC_5 Logic Functioning bit +(36 11) LC_5 Logic Functioning bit +(36 12) LC_6 Logic Functioning bit +(36 13) LC_6 Logic Functioning bit +(36 14) LC_7 Logic Functioning bit +(36 15) LC_7 Logic Functioning bit +(36 2) LC_1 Logic Functioning bit +(36 3) LC_1 Logic Functioning bit +(36 4) LC_2 Logic Functioning bit +(36 5) LC_2 Logic Functioning bit +(36 6) LC_3 Logic Functioning bit +(36 7) LC_3 Logic Functioning bit +(36 8) LC_4 Logic Functioning bit +(36 9) LC_4 Logic Functioning bit +(37 0) LC_0 Logic Functioning bit +(37 1) LC_0 Logic Functioning bit +(37 10) LC_5 Logic Functioning bit +(37 11) LC_5 Logic Functioning bit +(37 12) LC_6 Logic Functioning bit +(37 13) LC_6 Logic Functioning bit +(37 14) LC_7 Logic Functioning bit +(37 15) LC_7 Logic Functioning bit +(37 2) LC_1 Logic Functioning bit +(37 3) LC_1 Logic Functioning bit +(37 4) LC_2 Logic Functioning bit +(37 5) LC_2 Logic Functioning bit +(37 6) LC_3 Logic Functioning bit +(37 7) LC_3 Logic Functioning bit +(37 8) LC_4 Logic Functioning bit +(37 9) LC_4 Logic Functioning bit +(4 0) routing sp4_h_l_37 <X> sp4_v_b_0 +(4 0) routing sp4_h_l_43 <X> sp4_v_b_0 +(4 0) routing sp4_v_t_37 <X> sp4_v_b_0 +(4 0) routing sp4_v_t_41 <X> sp4_v_b_0 +(4 1) routing sp4_h_l_41 <X> sp4_h_r_0 +(4 1) routing sp4_h_l_44 <X> sp4_h_r_0 +(4 1) routing sp4_v_b_6 <X> sp4_h_r_0 +(4 1) routing sp4_v_t_42 <X> sp4_h_r_0 +(4 10) routing sp4_h_r_0 <X> sp4_v_t_43 +(4 10) routing sp4_h_r_6 <X> sp4_v_t_43 +(4 10) routing sp4_v_b_10 <X> sp4_v_t_43 +(4 10) routing sp4_v_b_6 <X> sp4_v_t_43 +(4 11) routing sp4_h_r_10 <X> sp4_h_l_43 +(4 11) routing sp4_v_b_1 <X> sp4_h_l_43 +(4 11) routing sp4_v_t_37 <X> sp4_h_l_43 +(4 12) routing sp4_h_l_38 <X> sp4_v_b_9 +(4 12) routing sp4_h_l_44 <X> sp4_v_b_9 +(4 12) routing sp4_v_t_36 <X> sp4_v_b_9 +(4 12) routing sp4_v_t_44 <X> sp4_v_b_9 +(4 13) routing sp4_h_l_36 <X> sp4_h_r_9 +(4 13) routing sp4_h_l_43 <X> sp4_h_r_9 +(4 13) routing sp4_v_b_3 <X> sp4_h_r_9 +(4 13) routing sp4_v_t_41 <X> sp4_h_r_9 +(4 14) routing sp4_h_r_3 <X> sp4_v_t_44 +(4 14) routing sp4_h_r_9 <X> sp4_v_t_44 +(4 14) routing sp4_v_b_1 <X> sp4_v_t_44 +(4 14) routing sp4_v_b_9 <X> sp4_v_t_44 +(4 15) routing sp4_h_r_1 <X> sp4_h_l_44 +(4 15) routing sp4_v_b_4 <X> sp4_h_l_44 +(4 15) routing sp4_v_t_38 <X> sp4_h_l_44 +(4 2) routing sp4_h_r_0 <X> sp4_v_t_37 +(4 2) routing sp4_h_r_6 <X> sp4_v_t_37 +(4 2) routing sp4_v_b_0 <X> sp4_v_t_37 +(4 2) routing sp4_v_b_4 <X> sp4_v_t_37 +(4 3) routing sp4_h_r_4 <X> sp4_h_l_37 +(4 3) routing sp4_h_r_9 <X> sp4_h_l_37 +(4 3) routing sp4_v_b_7 <X> sp4_h_l_37 +(4 3) routing sp4_v_t_43 <X> sp4_h_l_37 +(4 4) routing sp4_h_l_38 <X> sp4_v_b_3 +(4 4) routing sp4_h_l_44 <X> sp4_v_b_3 +(4 4) routing sp4_v_t_38 <X> sp4_v_b_3 +(4 4) routing sp4_v_t_42 <X> sp4_v_b_3 +(4 5) routing sp4_h_l_37 <X> sp4_h_r_3 +(4 5) routing sp4_h_l_42 <X> sp4_h_r_3 +(4 5) routing sp4_v_b_9 <X> sp4_h_r_3 +(4 5) routing sp4_v_t_47 <X> sp4_h_r_3 +(4 6) routing sp4_h_r_3 <X> sp4_v_t_38 +(4 6) routing sp4_h_r_9 <X> sp4_v_t_38 +(4 6) routing sp4_v_b_3 <X> sp4_v_t_38 +(4 6) routing sp4_v_b_7 <X> sp4_v_t_38 +(4 7) routing sp4_h_r_0 <X> sp4_h_l_38 +(4 7) routing sp4_v_b_10 <X> sp4_h_l_38 +(4 7) routing sp4_v_t_44 <X> sp4_h_l_38 +(4 8) routing sp4_h_l_37 <X> sp4_v_b_6 +(4 8) routing sp4_h_l_43 <X> sp4_v_b_6 +(4 8) routing sp4_v_t_43 <X> sp4_v_b_6 +(4 8) routing sp4_v_t_47 <X> sp4_v_b_6 +(4 9) routing sp4_h_l_38 <X> sp4_h_r_6 +(4 9) routing sp4_h_l_47 <X> sp4_h_r_6 +(4 9) routing sp4_v_b_0 <X> sp4_h_r_6 +(4 9) routing sp4_v_t_36 <X> sp4_h_r_6 +(42 0) LC_0 Logic Functioning bit +(42 1) LC_0 Logic Functioning bit +(42 10) LC_5 Logic Functioning bit +(42 11) LC_5 Logic Functioning bit +(42 12) LC_6 Logic Functioning bit +(42 13) LC_6 Logic Functioning bit +(42 14) LC_7 Logic Functioning bit +(42 15) LC_7 Logic Functioning bit +(42 2) LC_1 Logic Functioning bit +(42 3) LC_1 Logic Functioning bit +(42 4) LC_2 Logic Functioning bit +(42 5) LC_2 Logic Functioning bit +(42 6) LC_3 Logic Functioning bit +(42 7) LC_3 Logic Functioning bit +(42 8) LC_4 Logic Functioning bit +(42 9) LC_4 Logic Functioning bit +(43 0) LC_0 Logic Functioning bit +(43 1) LC_0 Logic Functioning bit +(43 10) LC_5 Logic Functioning bit +(43 11) LC_5 Logic Functioning bit +(43 12) LC_6 Logic Functioning bit +(43 13) LC_6 Logic Functioning bit +(43 14) LC_7 Logic Functioning bit +(43 15) LC_7 Logic Functioning bit +(43 2) LC_1 Logic Functioning bit +(43 3) LC_1 Logic Functioning bit +(43 4) LC_2 Logic Functioning bit +(43 5) LC_2 Logic Functioning bit +(43 6) LC_3 Logic Functioning bit +(43 7) LC_3 Logic Functioning bit +(43 8) LC_4 Logic Functioning bit +(43 9) LC_4 Logic Functioning bit +(46 0) Enable bit of Mux _out_links/OutMux7_0 => slf_op_0 sp4_h_r_16 +(46 1) Enable bit of Mux _out_links/OutMux6_0 => slf_op_0 sp4_h_r_0 +(46 10) Enable bit of Mux _out_links/OutMux7_5 => slf_op_5 sp4_h_r_26 +(46 11) Enable bit of Mux _out_links/OutMux6_5 => slf_op_5 sp4_h_r_10 +(46 12) Enable bit of Mux _out_links/OutMux7_6 => slf_op_6 sp4_h_r_28 +(46 13) Enable bit of Mux _out_links/OutMux6_6 => slf_op_6 sp4_h_l_1 +(46 14) Enable bit of Mux _out_links/OutMux7_7 => slf_op_7 sp4_h_l_19 +(46 15) Enable bit of Mux _out_links/OutMux6_7 => slf_op_7 sp4_h_l_3 +(46 2) Enable bit of Mux _out_links/OutMux7_1 => slf_op_1 sp4_h_l_7 +(46 3) Enable bit of Mux _out_links/OutMux6_1 => slf_op_1 sp4_h_r_2 +(46 4) Enable bit of Mux _out_links/OutMux7_2 => slf_op_2 sp4_h_r_20 +(46 5) Enable bit of Mux _out_links/OutMux6_2 => slf_op_2 sp4_h_r_4 +(46 6) Enable bit of Mux _out_links/OutMux7_3 => slf_op_3 sp4_h_l_11 +(46 7) Enable bit of Mux _out_links/OutMux6_3 => slf_op_3 sp4_h_r_6 +(46 8) Enable bit of Mux _out_links/OutMux7_4 => slf_op_4 sp4_h_r_24 +(46 9) Enable bit of Mux _out_links/OutMux6_4 => slf_op_4 sp4_h_r_8 +(47 0) Enable bit of Mux _out_links/OutMux5_0 => slf_op_0 sp12_h_l_7 +(47 1) Enable bit of Mux _out_links/OutMux8_0 => slf_op_0 sp4_h_l_21 +(47 10) Enable bit of Mux _out_links/OutMux4_5 => slf_op_5 sp12_h_l_1 +(47 11) Enable bit of Mux _out_links/OutMux8_5 => slf_op_5 sp4_h_r_42 +(47 12) Enable bit of Mux _out_links/OutMux4_6 => slf_op_6 sp12_h_r_4 +(47 13) Enable bit of Mux _out_links/OutMux8_6 => slf_op_6 sp4_h_l_33 +(47 14) Enable bit of Mux _out_links/OutMux4_7 => slf_op_7 sp12_h_l_5 +(47 15) Enable bit of Mux _out_links/OutMux8_7 => slf_op_7 sp4_h_l_35 +(47 2) Enable bit of Mux _out_links/OutMux5_1 => slf_op_1 sp12_h_l_9 +(47 3) Enable bit of Mux _out_links/OutMux8_1 => slf_op_1 sp4_h_r_34 +(47 4) Enable bit of Mux _out_links/OutMux5_2 => slf_op_2 sp12_h_l_11 +(47 5) Enable bit of Mux _out_links/OutMux8_2 => slf_op_2 sp4_h_r_36 +(47 6) Enable bit of Mux _out_links/OutMux5_3 => slf_op_3 sp12_h_r_14 +(47 7) Enable bit of Mux _out_links/OutMux8_3 => slf_op_3 sp4_h_r_38 +(47 8) Enable bit of Mux _out_links/OutMux4_4 => slf_op_4 sp12_h_r_0 +(47 9) Enable bit of Mux _out_links/OutMux8_4 => slf_op_4 sp4_h_l_29 +(48 0) Enable bit of Mux _out_links/OutMux0_0 => slf_op_0 sp4_v_b_0 +(48 1) Enable bit of Mux _out_links/OutMux1_0 => slf_op_0 sp4_v_t_5 +(48 10) Enable bit of Mux _out_links/OutMux5_5 => slf_op_5 sp12_h_l_17 +(48 11) Enable bit of Mux _out_links/OutMux0_5 => slf_op_5 sp4_v_b_10 +(48 12) Enable bit of Mux _out_links/OutMux5_6 => slf_op_6 sp12_h_r_20 +(48 13) Enable bit of Mux _out_links/OutMux0_6 => slf_op_6 sp4_v_b_12 +(48 14) Enable bit of Mux _out_links/OutMux5_7 => slf_op_7 sp12_h_r_22 +(48 15) Enable bit of Mux _out_links/OutMux0_7 => slf_op_7 sp4_v_t_3 +(48 2) Enable bit of Mux _out_links/OutMux0_1 => slf_op_1 sp4_v_b_2 +(48 3) Enable bit of Mux _out_links/OutMux1_1 => slf_op_1 sp4_v_b_18 +(48 4) Enable bit of Mux _out_links/OutMux0_2 => slf_op_2 sp4_v_b_4 +(48 5) Enable bit of Mux _out_links/OutMux1_2 => slf_op_2 sp4_v_t_9 +(48 6) Enable bit of Mux _out_links/OutMux0_3 => slf_op_3 sp4_v_b_6 +(48 7) Enable bit of Mux _out_links/OutMux1_3 => slf_op_3 sp4_v_b_22 +(48 8) Enable bit of Mux _out_links/OutMux5_4 => slf_op_4 sp12_h_l_15 +(48 9) Enable bit of Mux _out_links/OutMux0_4 => slf_op_4 sp4_v_b_8 +(5 0) routing sp4_h_l_44 <X> sp4_h_r_0 +(5 0) routing sp4_v_b_0 <X> sp4_h_r_0 +(5 0) routing sp4_v_b_6 <X> sp4_h_r_0 +(5 0) routing sp4_v_t_37 <X> sp4_h_r_0 +(5 1) routing sp4_h_l_37 <X> sp4_v_b_0 +(5 1) routing sp4_h_l_43 <X> sp4_v_b_0 +(5 1) routing sp4_h_r_0 <X> sp4_v_b_0 +(5 1) routing sp4_v_t_44 <X> sp4_v_b_0 +(5 10) routing sp4_v_b_6 <X> sp4_h_l_43 +(5 10) routing sp4_v_t_37 <X> sp4_h_l_43 +(5 10) routing sp4_v_t_43 <X> sp4_h_l_43 +(5 11) routing sp4_h_l_43 <X> sp4_v_t_43 +(5 11) routing sp4_h_r_0 <X> sp4_v_t_43 +(5 11) routing sp4_h_r_6 <X> sp4_v_t_43 +(5 11) routing sp4_v_b_3 <X> sp4_v_t_43 +(5 12) routing sp4_h_l_43 <X> sp4_h_r_9 +(5 12) routing sp4_v_b_3 <X> sp4_h_r_9 +(5 12) routing sp4_v_b_9 <X> sp4_h_r_9 +(5 12) routing sp4_v_t_44 <X> sp4_h_r_9 +(5 13) routing sp4_h_l_38 <X> sp4_v_b_9 +(5 13) routing sp4_h_l_44 <X> sp4_v_b_9 +(5 13) routing sp4_h_r_9 <X> sp4_v_b_9 +(5 13) routing sp4_v_t_43 <X> sp4_v_b_9 +(5 14) routing sp4_v_b_9 <X> sp4_h_l_44 +(5 14) routing sp4_v_t_38 <X> sp4_h_l_44 +(5 14) routing sp4_v_t_44 <X> sp4_h_l_44 +(5 15) routing sp4_h_l_44 <X> sp4_v_t_44 +(5 15) routing sp4_h_r_3 <X> sp4_v_t_44 +(5 15) routing sp4_h_r_9 <X> sp4_v_t_44 +(5 15) routing sp4_v_b_6 <X> sp4_v_t_44 +(5 2) routing sp4_h_r_9 <X> sp4_h_l_37 +(5 2) routing sp4_v_b_0 <X> sp4_h_l_37 +(5 2) routing sp4_v_t_37 <X> sp4_h_l_37 +(5 2) routing sp4_v_t_43 <X> sp4_h_l_37 +(5 3) routing sp4_h_l_37 <X> sp4_v_t_37 +(5 3) routing sp4_h_r_0 <X> sp4_v_t_37 +(5 3) routing sp4_h_r_6 <X> sp4_v_t_37 +(5 3) routing sp4_v_b_9 <X> sp4_v_t_37 +(5 4) routing sp4_h_l_37 <X> sp4_h_r_3 +(5 4) routing sp4_v_b_3 <X> sp4_h_r_3 +(5 4) routing sp4_v_b_9 <X> sp4_h_r_3 +(5 4) routing sp4_v_t_38 <X> sp4_h_r_3 +(5 5) routing sp4_h_l_38 <X> sp4_v_b_3 +(5 5) routing sp4_h_l_44 <X> sp4_v_b_3 +(5 5) routing sp4_h_r_3 <X> sp4_v_b_3 +(5 5) routing sp4_v_t_37 <X> sp4_v_b_3 +(5 6) routing sp4_h_r_0 <X> sp4_h_l_38 +(5 6) routing sp4_v_b_3 <X> sp4_h_l_38 +(5 6) routing sp4_v_t_38 <X> sp4_h_l_38 +(5 6) routing sp4_v_t_44 <X> sp4_h_l_38 +(5 7) routing sp4_h_l_38 <X> sp4_v_t_38 +(5 7) routing sp4_h_r_3 <X> sp4_v_t_38 +(5 7) routing sp4_h_r_9 <X> sp4_v_t_38 +(5 7) routing sp4_v_b_0 <X> sp4_v_t_38 +(5 8) routing sp4_h_l_38 <X> sp4_h_r_6 +(5 8) routing sp4_v_b_0 <X> sp4_h_r_6 +(5 8) routing sp4_v_b_6 <X> sp4_h_r_6 +(5 8) routing sp4_v_t_43 <X> sp4_h_r_6 +(5 9) routing sp4_h_l_37 <X> sp4_v_b_6 +(5 9) routing sp4_h_l_43 <X> sp4_v_b_6 +(5 9) routing sp4_h_r_6 <X> sp4_v_b_6 +(5 9) routing sp4_v_t_38 <X> sp4_v_b_6 +(50 0) Cascade buffer Enable bit: IPCON_LC00_inmux02_5 +(50 10) Cascade buffer Enable bit: IPCON_LC05_inmux02_5 +(50 12) Cascade buffer Enable bit: IPCON_LC06_inmux02_5 +(50 14) Cascade buffer Enable bit: IPCON_LC07_inmux02_5 +(50 2) Cascade buffer Enable bit: IPCON_LC01_inmux02_5 +(50 4) Cascade buffer Enable bit: IPCON_LC02_inmux02_5 +(50 6) Cascade buffer Enable bit: IPCON_LC03_inmux02_5 +(50 8) Cascade buffer Enable bit: IPCON_LC04_inmux02_5 +(51 0) Enable bit of Mux _out_links/OutMux3_0 => slf_op_0 sp12_v_b_0 +(51 1) Enable bit of Mux _out_links/OutMux2_0 => slf_op_0 sp4_v_t_21 +(51 10) Enable bit of Mux _out_links/OutMux2_5 => slf_op_5 sp4_v_t_31 +(51 11) Enable bit of Mux _out_links/OutMux1_5 => slf_op_5 sp4_v_t_15 +(51 12) Enable bit of Mux _out_links/OutMux2_6 => slf_op_6 sp4_v_t_33 +(51 13) Enable bit of Mux _out_links/OutMux1_6 => slf_op_6 sp4_v_t_17 +(51 14) Enable bit of Mux _out_links/OutMux2_7 => slf_op_7 sp4_v_b_46 +(51 15) Enable bit of Mux _out_links/OutMux1_7 => slf_op_7 sp4_v_t_19 +(51 2) Enable bit of Mux _out_links/OutMux3_1 => slf_op_1 sp12_v_t_1 +(51 3) Enable bit of Mux _out_links/OutMux2_1 => slf_op_1 sp4_v_t_23 +(51 4) Enable bit of Mux _out_links/OutMux3_2 => slf_op_2 sp12_v_b_4 +(51 5) Enable bit of Mux _out_links/OutMux2_2 => slf_op_2 sp4_v_b_36 +(51 6) Enable bit of Mux _out_links/OutMux3_3 => slf_op_3 sp12_v_b_6 +(51 7) Enable bit of Mux _out_links/OutMux2_3 => slf_op_3 sp4_v_t_27 +(51 8) Enable bit of Mux _out_links/OutMux2_4 => slf_op_4 sp4_v_b_40 +(51 9) Enable bit of Mux _out_links/OutMux1_4 => slf_op_4 sp4_v_t_13 +(52 0) Enable bit of Mux _out_links/OutMux4_0 => slf_op_0 sp12_v_b_16 +(52 1) Enable bit of Mux _out_links/OutMux9_0 => slf_op_0 sp4_r_v_b_1 +(52 10) Enable bit of Mux _out_links/OutMux3_5 => slf_op_5 sp12_v_b_10 +(52 11) Enable bit of Mux _out_links/OutMux9_5 => slf_op_5 sp4_r_v_b_11 +(52 12) Enable bit of Mux _out_links/OutMux3_6 => slf_op_6 sp12_v_b_12 +(52 13) Enable bit of Mux _out_links/OutMux9_6 => slf_op_6 sp4_r_v_b_13 +(52 14) Enable bit of Mux _out_links/OutMux3_7 => slf_op_7 sp12_v_b_14 +(52 15) Enable bit of Mux _out_links/OutMux9_7 => slf_op_7 sp4_r_v_b_15 +(52 2) Enable bit of Mux _out_links/OutMux4_1 => slf_op_1 sp12_v_t_17 +(52 3) Enable bit of Mux _out_links/OutMux9_1 => slf_op_1 sp4_r_v_b_3 +(52 4) Enable bit of Mux _out_links/OutMux4_2 => slf_op_2 sp12_v_b_20 +(52 5) Enable bit of Mux _out_links/OutMux9_2 => slf_op_2 sp4_r_v_b_5 +(52 6) Enable bit of Mux _out_links/OutMux4_3 => slf_op_3 sp12_v_t_21 +(52 7) Enable bit of Mux _out_links/OutMux9_3 => slf_op_3 sp4_r_v_b_7 +(52 8) Enable bit of Mux _out_links/OutMux3_4 => slf_op_4 sp12_v_t_7 +(52 9) Enable bit of Mux _out_links/OutMux9_4 => slf_op_4 sp4_r_v_b_9 +(53 0) Enable bit of Mux _out_links/OutMuxa_0 => slf_op_0 sp4_r_v_b_17 +(53 1) Enable bit of Mux _out_links/OutMuxb_0 => slf_op_0 sp4_r_v_b_33 +(53 10) Enable bit of Mux _out_links/OutMuxa_5 => slf_op_5 sp4_r_v_b_27 +(53 11) Enable bit of Mux _out_links/OutMuxb_5 => slf_op_5 sp4_r_v_b_43 +(53 12) Enable bit of Mux _out_links/OutMuxa_6 => slf_op_6 sp4_r_v_b_29 +(53 13) Enable bit of Mux _out_links/OutMuxb_6 => slf_op_6 sp4_r_v_b_45 +(53 14) Enable bit of Mux _out_links/OutMuxa_7 => slf_op_7 sp4_r_v_b_31 +(53 15) Enable bit of Mux _out_links/OutMuxb_7 => slf_op_7 sp4_r_v_b_47 +(53 2) Enable bit of Mux _out_links/OutMuxa_1 => slf_op_1 sp4_r_v_b_19 +(53 3) Enable bit of Mux _out_links/OutMuxb_1 => slf_op_1 sp4_r_v_b_35 +(53 4) Enable bit of Mux _out_links/OutMuxa_2 => slf_op_2 sp4_r_v_b_21 +(53 5) Enable bit of Mux _out_links/OutMuxb_2 => slf_op_2 sp4_r_v_b_37 +(53 6) Enable bit of Mux _out_links/OutMuxa_3 => slf_op_3 sp4_r_v_b_23 +(53 7) Enable bit of Mux _out_links/OutMuxb_3 => slf_op_3 sp4_r_v_b_39 +(53 8) Enable bit of Mux _out_links/OutMuxa_4 => slf_op_4 sp4_r_v_b_25 +(53 9) Enable bit of Mux _out_links/OutMuxb_4 => slf_op_4 sp4_r_v_b_41 +(6 0) routing sp4_h_l_43 <X> sp4_v_b_0 +(6 0) routing sp4_h_r_7 <X> sp4_v_b_0 +(6 0) routing sp4_v_t_41 <X> sp4_v_b_0 +(6 0) routing sp4_v_t_44 <X> sp4_v_b_0 +(6 1) routing sp4_h_l_37 <X> sp4_h_r_0 +(6 1) routing sp4_h_l_41 <X> sp4_h_r_0 +(6 1) routing sp4_v_b_0 <X> sp4_h_r_0 +(6 1) routing sp4_v_b_6 <X> sp4_h_r_0 +(6 10) routing sp4_h_l_36 <X> sp4_v_t_43 +(6 10) routing sp4_h_r_0 <X> sp4_v_t_43 +(6 10) routing sp4_v_b_10 <X> sp4_v_t_43 +(6 10) routing sp4_v_b_3 <X> sp4_v_t_43 +(6 11) routing sp4_h_r_10 <X> sp4_h_l_43 +(6 11) routing sp4_v_t_37 <X> sp4_h_l_43 +(6 11) routing sp4_v_t_43 <X> sp4_h_l_43 +(6 12) routing sp4_h_l_38 <X> sp4_v_b_9 +(6 12) routing sp4_h_r_4 <X> sp4_v_b_9 +(6 12) routing sp4_v_t_36 <X> sp4_v_b_9 +(6 12) routing sp4_v_t_43 <X> sp4_v_b_9 +(6 13) routing sp4_h_l_36 <X> sp4_h_r_9 +(6 13) routing sp4_h_l_44 <X> sp4_h_r_9 +(6 13) routing sp4_v_b_3 <X> sp4_h_r_9 +(6 13) routing sp4_v_b_9 <X> sp4_h_r_9 +(6 14) routing sp4_h_l_41 <X> sp4_v_t_44 +(6 14) routing sp4_h_r_3 <X> sp4_v_t_44 +(6 14) routing sp4_v_b_1 <X> sp4_v_t_44 +(6 14) routing sp4_v_b_6 <X> sp4_v_t_44 +(6 15) routing sp4_h_r_1 <X> sp4_h_l_44 +(6 15) routing sp4_v_t_38 <X> sp4_h_l_44 +(6 15) routing sp4_v_t_44 <X> sp4_h_l_44 +(6 2) routing sp4_h_l_42 <X> sp4_v_t_37 +(6 2) routing sp4_h_r_6 <X> sp4_v_t_37 +(6 2) routing sp4_v_b_4 <X> sp4_v_t_37 +(6 2) routing sp4_v_b_9 <X> sp4_v_t_37 +(6 3) routing sp4_h_r_0 <X> sp4_h_l_37 +(6 3) routing sp4_h_r_4 <X> sp4_h_l_37 +(6 3) routing sp4_v_t_37 <X> sp4_h_l_37 +(6 3) routing sp4_v_t_43 <X> sp4_h_l_37 +(6 4) routing sp4_h_l_44 <X> sp4_v_b_3 +(6 4) routing sp4_h_r_10 <X> sp4_v_b_3 +(6 4) routing sp4_v_t_37 <X> sp4_v_b_3 +(6 4) routing sp4_v_t_42 <X> sp4_v_b_3 +(6 5) routing sp4_h_l_38 <X> sp4_h_r_3 +(6 5) routing sp4_h_l_42 <X> sp4_h_r_3 +(6 5) routing sp4_v_b_3 <X> sp4_h_r_3 +(6 5) routing sp4_v_b_9 <X> sp4_h_r_3 +(6 6) routing sp4_h_l_47 <X> sp4_v_t_38 +(6 6) routing sp4_h_r_9 <X> sp4_v_t_38 +(6 6) routing sp4_v_b_0 <X> sp4_v_t_38 +(6 6) routing sp4_v_b_7 <X> sp4_v_t_38 +(6 7) routing sp4_v_t_38 <X> sp4_h_l_38 +(6 7) routing sp4_v_t_44 <X> sp4_h_l_38 +(6 8) routing sp4_h_l_37 <X> sp4_v_b_6 +(6 8) routing sp4_h_r_1 <X> sp4_v_b_6 +(6 8) routing sp4_v_t_38 <X> sp4_v_b_6 +(6 8) routing sp4_v_t_47 <X> sp4_v_b_6 +(6 9) routing sp4_h_l_43 <X> sp4_h_r_6 +(6 9) routing sp4_h_l_47 <X> sp4_h_r_6 +(6 9) routing sp4_v_b_0 <X> sp4_h_r_6 +(6 9) routing sp4_v_b_6 <X> sp4_h_r_6 +(7 0) Hard IP config bit: IPCON_bram_cbit_1 +(7 1) Hard IP config bit: IPCON_bram_cbit_0 +(7 10) Column buffer control bit: IPCON_colbuf_cntl_3 +(7 11) Column buffer control bit: IPCON_colbuf_cntl_2 +(7 12) Column buffer control bit: IPCON_colbuf_cntl_5 +(7 13) Column buffer control bit: IPCON_colbuf_cntl_4 +(7 14) Column buffer control bit: IPCON_colbuf_cntl_7 +(7 15) Column buffer control bit: IPCON_colbuf_cntl_6 +(7 2) Hard IP config bit: IPCON_bram_cbit_3 +(7 2) MAC16 functional bit: IPCON_bram_cbit_3 +(7 3) Hard IP config bit: IPCON_bram_cbit_2 +(7 4) Hard IP config bit: IPCON_bram_cbit_5 +(7 4) MAC16 functional bit: IPCON_bram_cbit_5 +(7 5) Hard IP config bit: IPCON_bram_cbit_4 +(7 5) MAC16 functional bit: IPCON_bram_cbit_4 +(7 6) Hard IP config bit: IPCON_bram_cbit_7 +(7 7) Hard IP config bit: IPCON_bram_cbit_6 +(7 7) MAC16 functional bit: IPCON_bram_cbit_6 +(7 8) Column buffer control bit: IPCON_colbuf_cntl_1 +(7 9) Column buffer control bit: IPCON_colbuf_cntl_0 +(8 0) routing sp4_h_l_36 <X> sp4_h_r_1 +(8 0) routing sp4_h_l_40 <X> sp4_h_r_1 +(8 0) routing sp4_v_b_1 <X> sp4_h_r_1 +(8 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(8 1) routing sp4_h_l_36 <X> sp4_v_b_1 +(8 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(8 1) routing sp4_h_r_1 <X> sp4_v_b_1 +(8 1) routing sp4_v_t_47 <X> sp4_v_b_1 +(8 10) routing sp4_h_r_11 <X> sp4_h_l_42 +(8 10) routing sp4_h_r_7 <X> sp4_h_l_42 +(8 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(8 10) routing sp4_v_t_42 <X> sp4_h_l_42 +(8 11) routing sp4_h_l_42 <X> sp4_v_t_42 +(8 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(8 11) routing sp4_h_r_7 <X> sp4_v_t_42 +(8 11) routing sp4_v_b_4 <X> sp4_v_t_42 +(8 12) routing sp4_h_l_47 <X> sp4_h_r_10 +(8 12) routing sp4_v_b_10 <X> sp4_h_r_10 +(8 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(8 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(8 13) routing sp4_h_l_47 <X> sp4_v_b_10 +(8 13) routing sp4_h_r_10 <X> sp4_v_b_10 +(8 13) routing sp4_v_t_42 <X> sp4_v_b_10 +(8 14) routing sp4_h_r_10 <X> sp4_h_l_47 +(8 14) routing sp4_h_r_2 <X> sp4_h_l_47 +(8 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(8 14) routing sp4_v_t_47 <X> sp4_h_l_47 +(8 15) routing sp4_h_l_47 <X> sp4_v_t_47 +(8 15) routing sp4_h_r_10 <X> sp4_v_t_47 +(8 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(8 15) routing sp4_v_b_7 <X> sp4_v_t_47 +(8 2) routing sp4_h_r_5 <X> sp4_h_l_36 +(8 2) routing sp4_v_t_36 <X> sp4_h_l_36 +(8 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(8 3) routing sp4_h_l_36 <X> sp4_v_t_36 +(8 3) routing sp4_h_r_1 <X> sp4_v_t_36 +(8 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(8 3) routing sp4_v_b_10 <X> sp4_v_t_36 +(8 4) routing sp4_h_l_41 <X> sp4_h_r_4 +(8 4) routing sp4_h_l_45 <X> sp4_h_r_4 +(8 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(8 4) routing sp4_v_b_4 <X> sp4_h_r_4 +(8 5) routing sp4_h_l_41 <X> sp4_v_b_4 +(8 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(8 5) routing sp4_h_r_4 <X> sp4_v_b_4 +(8 5) routing sp4_v_t_36 <X> sp4_v_b_4 +(8 6) routing sp4_h_r_4 <X> sp4_h_l_41 +(8 6) routing sp4_h_r_8 <X> sp4_h_l_41 +(8 6) routing sp4_v_t_41 <X> sp4_h_l_41 +(8 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(8 7) routing sp4_h_l_41 <X> sp4_v_t_41 +(8 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(8 7) routing sp4_h_r_4 <X> sp4_v_t_41 +(8 7) routing sp4_v_b_1 <X> sp4_v_t_41 +(8 8) routing sp4_h_l_42 <X> sp4_h_r_7 +(8 8) routing sp4_h_l_46 <X> sp4_h_r_7 +(8 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(8 8) routing sp4_v_b_7 <X> sp4_h_r_7 +(8 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(8 9) routing sp4_h_l_42 <X> sp4_v_b_7 +(8 9) routing sp4_h_r_7 <X> sp4_v_b_7 +(8 9) routing sp4_v_t_41 <X> sp4_v_b_7 +(9 0) routing sp4_h_l_47 <X> sp4_h_r_1 +(9 0) routing sp4_v_b_1 <X> sp4_h_r_1 +(9 0) routing sp4_v_b_7 <X> sp4_h_r_1 +(9 0) routing sp4_v_t_36 <X> sp4_h_r_1 +(9 1) routing sp4_h_l_36 <X> sp4_v_b_1 +(9 1) routing sp4_h_l_42 <X> sp4_v_b_1 +(9 1) routing sp4_v_t_36 <X> sp4_v_b_1 +(9 1) routing sp4_v_t_40 <X> sp4_v_b_1 +(9 10) routing sp4_h_r_4 <X> sp4_h_l_42 +(9 10) routing sp4_v_b_7 <X> sp4_h_l_42 +(9 10) routing sp4_v_t_36 <X> sp4_h_l_42 +(9 10) routing sp4_v_t_42 <X> sp4_h_l_42 +(9 11) routing sp4_h_r_1 <X> sp4_v_t_42 +(9 11) routing sp4_h_r_7 <X> sp4_v_t_42 +(9 11) routing sp4_v_b_11 <X> sp4_v_t_42 +(9 11) routing sp4_v_b_7 <X> sp4_v_t_42 +(9 12) routing sp4_h_l_42 <X> sp4_h_r_10 +(9 12) routing sp4_v_b_10 <X> sp4_h_r_10 +(9 12) routing sp4_v_b_4 <X> sp4_h_r_10 +(9 12) routing sp4_v_t_47 <X> sp4_h_r_10 +(9 13) routing sp4_h_l_41 <X> sp4_v_b_10 +(9 13) routing sp4_h_l_47 <X> sp4_v_b_10 +(9 13) routing sp4_v_t_39 <X> sp4_v_b_10 +(9 13) routing sp4_v_t_47 <X> sp4_v_b_10 +(9 14) routing sp4_v_b_10 <X> sp4_h_l_47 +(9 14) routing sp4_v_t_41 <X> sp4_h_l_47 +(9 14) routing sp4_v_t_47 <X> sp4_h_l_47 +(9 15) routing sp4_h_r_10 <X> sp4_v_t_47 +(9 15) routing sp4_h_r_4 <X> sp4_v_t_47 +(9 15) routing sp4_v_b_10 <X> sp4_v_t_47 +(9 15) routing sp4_v_b_2 <X> sp4_v_t_47 +(9 2) routing sp4_h_r_10 <X> sp4_h_l_36 +(9 2) routing sp4_v_b_1 <X> sp4_h_l_36 +(9 2) routing sp4_v_t_36 <X> sp4_h_l_36 +(9 2) routing sp4_v_t_42 <X> sp4_h_l_36 +(9 3) routing sp4_h_r_1 <X> sp4_v_t_36 +(9 3) routing sp4_h_r_7 <X> sp4_v_t_36 +(9 3) routing sp4_v_b_1 <X> sp4_v_t_36 +(9 3) routing sp4_v_b_5 <X> sp4_v_t_36 +(9 4) routing sp4_h_l_36 <X> sp4_h_r_4 +(9 4) routing sp4_v_b_10 <X> sp4_h_r_4 +(9 4) routing sp4_v_b_4 <X> sp4_h_r_4 +(9 4) routing sp4_v_t_41 <X> sp4_h_r_4 +(9 5) routing sp4_h_l_41 <X> sp4_v_b_4 +(9 5) routing sp4_h_l_47 <X> sp4_v_b_4 +(9 5) routing sp4_v_t_41 <X> sp4_v_b_4 +(9 5) routing sp4_v_t_45 <X> sp4_v_b_4 +(9 6) routing sp4_h_r_1 <X> sp4_h_l_41 +(9 6) routing sp4_v_b_4 <X> sp4_h_l_41 +(9 6) routing sp4_v_t_41 <X> sp4_h_l_41 +(9 6) routing sp4_v_t_47 <X> sp4_h_l_41 +(9 7) routing sp4_h_r_10 <X> sp4_v_t_41 +(9 7) routing sp4_h_r_4 <X> sp4_v_t_41 +(9 7) routing sp4_v_b_4 <X> sp4_v_t_41 +(9 7) routing sp4_v_b_8 <X> sp4_v_t_41 +(9 8) routing sp4_h_l_41 <X> sp4_h_r_7 +(9 8) routing sp4_v_b_1 <X> sp4_h_r_7 +(9 8) routing sp4_v_b_7 <X> sp4_h_r_7 +(9 8) routing sp4_v_t_42 <X> sp4_h_r_7 +(9 9) routing sp4_h_l_36 <X> sp4_v_b_7 +(9 9) routing sp4_h_l_42 <X> sp4_v_b_7 +(9 9) routing sp4_v_t_42 <X> sp4_v_b_7 +(9 9) routing sp4_v_t_46 <X> sp4_v_b_7 diff --git a/icefuzz/cached_ramb_5k.txt b/icefuzz/cached_ramb_5k.txt index d553dbf..65c15e3 100644 --- a/icefuzz/cached_ramb_5k.txt +++ b/icefuzz/cached_ramb_5k.txt @@ -1,27 +1,18 @@ (0 0) Negative Clock bit +(0 10) routing glb_netwk_2 <X> glb2local_2 (0 10) routing glb_netwk_3 <X> glb2local_2 (0 10) routing glb_netwk_6 <X> glb2local_2 -(0 10) routing glb_netwk_7 <X> glb2local_2 -(0 11) routing glb_netwk_1 <X> glb2local_2 (0 11) routing glb_netwk_3 <X> glb2local_2 -(0 11) routing glb_netwk_5 <X> glb2local_2 -(0 11) routing glb_netwk_7 <X> glb2local_2 (0 12) routing glb_netwk_3 <X> glb2local_3 -(0 12) routing glb_netwk_6 <X> glb2local_3 (0 13) routing glb_netwk_1 <X> glb2local_3 (0 13) routing glb_netwk_3 <X> glb2local_3 -(0 13) routing glb_netwk_5 <X> glb2local_3 (0 14) routing glb_netwk_4 <X> wire_bram/ram/RE -(0 14) routing glb_netwk_6 <X> wire_bram/ram/RE (0 14) routing lc_trk_g2_4 <X> wire_bram/ram/RE (0 14) routing lc_trk_g3_5 <X> wire_bram/ram/RE -(0 15) routing glb_netwk_2 <X> wire_bram/ram/RE -(0 15) routing glb_netwk_6 <X> wire_bram/ram/RE (0 15) routing lc_trk_g1_5 <X> wire_bram/ram/RE (0 15) routing lc_trk_g3_5 <X> wire_bram/ram/RE (0 2) routing glb_netwk_2 <X> wire_bram/ram/RCLK (0 2) routing glb_netwk_3 <X> wire_bram/ram/RCLK -(0 2) routing glb_netwk_6 <X> wire_bram/ram/RCLK (0 2) routing glb_netwk_7 <X> wire_bram/ram/RCLK (0 2) routing lc_trk_g2_0 <X> wire_bram/ram/RCLK (0 2) routing lc_trk_g3_1 <X> wire_bram/ram/RCLK @@ -31,46 +22,22 @@ (0 3) routing glb_netwk_7 <X> wire_bram/ram/RCLK (0 3) routing lc_trk_g1_1 <X> wire_bram/ram/RCLK (0 3) routing lc_trk_g3_1 <X> wire_bram/ram/RCLK -(0 4) routing glb_netwk_5 <X> wire_bram/ram/RCLKE (0 4) routing lc_trk_g2_2 <X> wire_bram/ram/RCLKE (0 4) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE (0 5) routing lc_trk_g1_3 <X> wire_bram/ram/RCLKE (0 5) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE -(0 6) routing glb_netwk_3 <X> glb2local_0 -(0 6) routing glb_netwk_6 <X> glb2local_0 -(0 6) routing glb_netwk_7 <X> glb2local_0 (0 7) routing glb_netwk_1 <X> glb2local_0 -(0 7) routing glb_netwk_3 <X> glb2local_0 (0 7) routing glb_netwk_5 <X> glb2local_0 -(0 7) routing glb_netwk_7 <X> glb2local_0 -(0 8) routing glb_netwk_3 <X> glb2local_1 -(0 8) routing glb_netwk_6 <X> glb2local_1 -(0 8) routing glb_netwk_7 <X> glb2local_1 -(0 9) routing glb_netwk_1 <X> glb2local_1 -(0 9) routing glb_netwk_3 <X> glb2local_1 (0 9) routing glb_netwk_5 <X> glb2local_1 -(0 9) routing glb_netwk_7 <X> glb2local_1 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 +(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 (1 11) routing glb_netwk_4 <X> glb2local_2 -(1 11) routing glb_netwk_5 <X> glb2local_2 (1 11) routing glb_netwk_6 <X> glb2local_2 -(1 11) routing glb_netwk_7 <X> glb2local_2 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 -(1 13) routing glb_netwk_4 <X> glb2local_3 -(1 13) routing glb_netwk_5 <X> glb2local_3 -(1 13) routing glb_netwk_6 <X> glb2local_3 -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/RE -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/RE @@ -81,10 +48,8 @@ (1 15) routing lc_trk_g3_5 <X> wire_bram/ram/RE (1 2) routing glb_netwk_4 <X> wire_bram/ram/RCLK (1 2) routing glb_netwk_5 <X> wire_bram/ram/RCLK -(1 2) routing glb_netwk_6 <X> wire_bram/ram/RCLK (1 2) routing glb_netwk_7 <X> wire_bram/ram/RCLK (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 -(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/RCLKE @@ -94,25 +59,10 @@ (1 5) routing lc_trk_g2_2 <X> wire_bram/ram/RCLKE (1 5) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 -(1 7) routing glb_netwk_4 <X> glb2local_0 (1 7) routing glb_netwk_5 <X> glb2local_0 -(1 7) routing glb_netwk_6 <X> glb2local_0 -(1 7) routing glb_netwk_7 <X> glb2local_0 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 -(1 9) routing glb_netwk_4 <X> glb2local_1 (1 9) routing glb_netwk_5 <X> glb2local_1 -(1 9) routing glb_netwk_6 <X> glb2local_1 -(1 9) routing glb_netwk_7 <X> glb2local_1 (10 0) routing sp4_h_l_40 <X> sp4_h_r_1 (10 0) routing sp4_h_l_47 <X> sp4_h_r_1 (10 0) routing sp4_v_b_7 <X> sp4_h_r_1 @@ -214,6 +164,7 @@ (11 2) routing sp4_v_b_11 <X> sp4_v_t_39 (11 2) routing sp4_v_b_6 <X> sp4_v_t_39 (11 3) routing sp4_h_r_2 <X> sp4_h_l_39 +(11 3) routing sp4_h_r_6 <X> sp4_h_l_39 (11 3) routing sp4_v_t_39 <X> sp4_h_l_39 (11 3) routing sp4_v_t_45 <X> sp4_h_l_39 (11 4) routing sp4_h_l_46 <X> sp4_v_b_5 @@ -264,6 +215,7 @@ (12 13) routing sp4_h_l_46 <X> sp4_v_b_11 (12 13) routing sp4_h_r_11 <X> sp4_v_b_11 (12 13) routing sp4_v_t_45 <X> sp4_v_b_11 +(12 14) routing sp4_h_r_8 <X> sp4_h_l_46 (12 14) routing sp4_v_b_11 <X> sp4_h_l_46 (12 14) routing sp4_v_t_40 <X> sp4_h_l_46 (12 14) routing sp4_v_t_46 <X> sp4_h_l_46 @@ -332,6 +284,7 @@ (13 14) routing sp4_v_b_11 <X> sp4_v_t_46 (13 14) routing sp4_v_b_3 <X> sp4_v_t_46 (13 15) routing sp4_h_r_3 <X> sp4_h_l_46 +(13 15) routing sp4_h_r_8 <X> sp4_h_l_46 (13 15) routing sp4_v_b_6 <X> sp4_h_l_46 (13 15) routing sp4_v_t_40 <X> sp4_h_l_46 (13 2) routing sp4_h_r_2 <X> sp4_v_t_39 @@ -339,6 +292,7 @@ (13 2) routing sp4_v_b_2 <X> sp4_v_t_39 (13 2) routing sp4_v_b_6 <X> sp4_v_t_39 (13 3) routing sp4_h_r_11 <X> sp4_h_l_39 +(13 3) routing sp4_h_r_6 <X> sp4_h_l_39 (13 3) routing sp4_v_b_9 <X> sp4_h_l_39 (13 3) routing sp4_v_t_45 <X> sp4_h_l_39 (13 4) routing sp4_h_l_40 <X> sp4_v_b_5 @@ -442,13 +396,10 @@ (14 4) routing lft_op_0 <X> lc_trk_g1_0 (14 4) routing sp12_h_r_0 <X> lc_trk_g1_0 (14 4) routing sp4_h_r_16 <X> lc_trk_g1_0 -(14 4) routing sp4_h_r_8 <X> lc_trk_g1_0 (14 4) routing sp4_v_b_0 <X> lc_trk_g1_0 (14 4) routing sp4_v_b_8 <X> lc_trk_g1_0 (14 5) routing bnr_op_0 <X> lc_trk_g1_0 -(14 5) routing sp12_h_l_15 <X> lc_trk_g1_0 (14 5) routing sp12_h_r_0 <X> lc_trk_g1_0 -(14 5) routing sp4_h_r_0 <X> lc_trk_g1_0 (14 5) routing sp4_h_r_16 <X> lc_trk_g1_0 (14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0 (14 5) routing sp4_v_b_8 <X> lc_trk_g1_0 @@ -463,7 +414,6 @@ (14 7) routing sp12_h_l_3 <X> lc_trk_g1_4 (14 7) routing sp12_h_r_20 <X> lc_trk_g1_4 (14 7) routing sp4_h_l_9 <X> lc_trk_g1_4 -(14 7) routing sp4_h_r_4 <X> lc_trk_g1_4 (14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4 (14 7) routing sp4_v_b_12 <X> lc_trk_g1_4 (14 8) routing bnl_op_0 <X> lc_trk_g2_0 @@ -476,7 +426,6 @@ (14 9) routing bnl_op_0 <X> lc_trk_g2_0 (14 9) routing sp12_v_b_0 <X> lc_trk_g2_0 (14 9) routing sp12_v_b_16 <X> lc_trk_g2_0 -(14 9) routing sp4_h_r_24 <X> lc_trk_g2_0 (14 9) routing sp4_h_r_40 <X> lc_trk_g2_0 (14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0 (14 9) routing sp4_v_b_32 <X> lc_trk_g2_0 @@ -485,9 +434,7 @@ (15 0) routing sp12_h_r_1 <X> lc_trk_g0_1 (15 0) routing sp4_h_r_1 <X> lc_trk_g0_1 (15 0) routing sp4_h_r_17 <X> lc_trk_g0_1 -(15 0) routing sp4_h_r_9 <X> lc_trk_g0_1 (15 0) routing sp4_v_t_4 <X> lc_trk_g0_1 -(15 1) routing bot_op_0 <X> lc_trk_g0_0 (15 1) routing lft_op_0 <X> lc_trk_g0_0 (15 1) routing sp12_h_r_0 <X> lc_trk_g0_0 (15 1) routing sp4_h_r_0 <X> lc_trk_g0_0 @@ -499,9 +446,7 @@ (15 10) routing sp4_h_r_29 <X> lc_trk_g2_5 (15 10) routing sp4_h_r_37 <X> lc_trk_g2_5 (15 10) routing sp4_h_r_45 <X> lc_trk_g2_5 -(15 10) routing sp4_v_b_45 <X> lc_trk_g2_5 (15 10) routing tnl_op_5 <X> lc_trk_g2_5 -(15 10) routing tnr_op_5 <X> lc_trk_g2_5 (15 11) routing rgt_op_4 <X> lc_trk_g2_4 (15 11) routing sp12_v_b_4 <X> lc_trk_g2_4 (15 11) routing sp4_h_r_28 <X> lc_trk_g2_4 @@ -516,8 +461,6 @@ (15 12) routing sp4_h_r_25 <X> lc_trk_g3_1 (15 12) routing sp4_h_r_33 <X> lc_trk_g3_1 (15 12) routing sp4_v_b_41 <X> lc_trk_g3_1 -(15 12) routing tnl_op_1 <X> lc_trk_g3_1 -(15 12) routing tnr_op_1 <X> lc_trk_g3_1 (15 13) routing rgt_op_0 <X> lc_trk_g3_0 (15 13) routing sp12_v_b_0 <X> lc_trk_g3_0 (15 13) routing sp4_h_r_24 <X> lc_trk_g3_0 @@ -525,7 +468,6 @@ (15 13) routing sp4_h_r_40 <X> lc_trk_g3_0 (15 13) routing sp4_v_b_40 <X> lc_trk_g3_0 (15 13) routing tnl_op_0 <X> lc_trk_g3_0 -(15 13) routing tnr_op_0 <X> lc_trk_g3_0 (15 14) routing rgt_op_5 <X> lc_trk_g3_5 (15 14) routing sp12_v_b_5 <X> lc_trk_g3_5 (15 14) routing sp4_h_r_29 <X> lc_trk_g3_5 @@ -541,14 +483,11 @@ (15 15) routing sp4_h_r_44 <X> lc_trk_g3_4 (15 15) routing sp4_v_b_44 <X> lc_trk_g3_4 (15 15) routing tnl_op_4 <X> lc_trk_g3_4 -(15 15) routing tnr_op_4 <X> lc_trk_g3_4 (15 2) routing lft_op_5 <X> lc_trk_g0_5 -(15 2) routing sp12_h_l_2 <X> lc_trk_g0_5 (15 2) routing sp4_h_r_13 <X> lc_trk_g0_5 (15 2) routing sp4_h_r_21 <X> lc_trk_g0_5 (15 2) routing sp4_h_r_5 <X> lc_trk_g0_5 (15 2) routing sp4_v_t_8 <X> lc_trk_g0_5 -(15 3) routing bot_op_4 <X> lc_trk_g0_4 (15 3) routing lft_op_4 <X> lc_trk_g0_4 (15 3) routing sp12_h_l_3 <X> lc_trk_g0_4 (15 3) routing sp4_h_l_1 <X> lc_trk_g0_4 @@ -564,44 +503,32 @@ (15 5) routing bot_op_0 <X> lc_trk_g1_0 (15 5) routing lft_op_0 <X> lc_trk_g1_0 (15 5) routing sp12_h_r_0 <X> lc_trk_g1_0 -(15 5) routing sp4_h_r_0 <X> lc_trk_g1_0 (15 5) routing sp4_h_r_16 <X> lc_trk_g1_0 -(15 5) routing sp4_h_r_8 <X> lc_trk_g1_0 (15 5) routing sp4_v_b_16 <X> lc_trk_g1_0 (15 6) routing lft_op_5 <X> lc_trk_g1_5 -(15 6) routing sp12_h_l_2 <X> lc_trk_g1_5 (15 6) routing sp4_h_r_13 <X> lc_trk_g1_5 (15 6) routing sp4_h_r_21 <X> lc_trk_g1_5 (15 6) routing sp4_h_r_5 <X> lc_trk_g1_5 (15 6) routing sp4_v_t_8 <X> lc_trk_g1_5 -(15 7) routing bot_op_4 <X> lc_trk_g1_4 (15 7) routing lft_op_4 <X> lc_trk_g1_4 (15 7) routing sp12_h_l_3 <X> lc_trk_g1_4 (15 7) routing sp4_h_l_1 <X> lc_trk_g1_4 (15 7) routing sp4_h_l_9 <X> lc_trk_g1_4 -(15 7) routing sp4_h_r_4 <X> lc_trk_g1_4 (15 7) routing sp4_v_b_20 <X> lc_trk_g1_4 (15 8) routing rgt_op_1 <X> lc_trk_g2_1 -(15 8) routing sp12_v_b_1 <X> lc_trk_g2_1 (15 8) routing sp4_h_l_28 <X> lc_trk_g2_1 (15 8) routing sp4_h_r_25 <X> lc_trk_g2_1 (15 8) routing sp4_h_r_33 <X> lc_trk_g2_1 (15 8) routing sp4_v_b_41 <X> lc_trk_g2_1 (15 8) routing tnl_op_1 <X> lc_trk_g2_1 -(15 8) routing tnr_op_1 <X> lc_trk_g2_1 (15 9) routing rgt_op_0 <X> lc_trk_g2_0 (15 9) routing sp12_v_b_0 <X> lc_trk_g2_0 -(15 9) routing sp4_h_r_24 <X> lc_trk_g2_0 (15 9) routing sp4_h_r_32 <X> lc_trk_g2_0 (15 9) routing sp4_h_r_40 <X> lc_trk_g2_0 (15 9) routing sp4_v_b_40 <X> lc_trk_g2_0 (15 9) routing tnl_op_0 <X> lc_trk_g2_0 -(15 9) routing tnr_op_0 <X> lc_trk_g2_0 -(16 0) routing sp12_h_l_14 <X> lc_trk_g0_1 -(16 0) routing sp12_h_r_9 <X> lc_trk_g0_1 (16 0) routing sp4_h_r_1 <X> lc_trk_g0_1 (16 0) routing sp4_h_r_17 <X> lc_trk_g0_1 -(16 0) routing sp4_h_r_9 <X> lc_trk_g0_1 (16 0) routing sp4_v_b_1 <X> lc_trk_g0_1 (16 0) routing sp4_v_b_9 <X> lc_trk_g0_1 (16 0) routing sp4_v_t_4 <X> lc_trk_g0_1 @@ -619,7 +546,6 @@ (16 10) routing sp4_h_r_37 <X> lc_trk_g2_5 (16 10) routing sp4_h_r_45 <X> lc_trk_g2_5 (16 10) routing sp4_v_b_29 <X> lc_trk_g2_5 -(16 10) routing sp4_v_b_45 <X> lc_trk_g2_5 (16 10) routing sp4_v_t_24 <X> lc_trk_g2_5 (16 11) routing sp12_v_b_20 <X> lc_trk_g2_4 (16 11) routing sp12_v_t_11 <X> lc_trk_g2_4 @@ -661,8 +587,6 @@ (16 15) routing sp4_v_b_28 <X> lc_trk_g3_4 (16 15) routing sp4_v_b_44 <X> lc_trk_g3_4 (16 15) routing sp4_v_t_25 <X> lc_trk_g3_4 -(16 2) routing sp12_h_l_10 <X> lc_trk_g0_5 -(16 2) routing sp12_h_r_21 <X> lc_trk_g0_5 (16 2) routing sp4_h_r_13 <X> lc_trk_g0_5 (16 2) routing sp4_h_r_21 <X> lc_trk_g0_5 (16 2) routing sp4_h_r_5 <X> lc_trk_g0_5 @@ -678,23 +602,17 @@ (16 3) routing sp4_v_b_20 <X> lc_trk_g0_4 (16 3) routing sp4_v_b_4 <X> lc_trk_g0_4 (16 4) routing sp12_h_l_14 <X> lc_trk_g1_1 -(16 4) routing sp12_h_r_9 <X> lc_trk_g1_1 (16 4) routing sp4_h_r_1 <X> lc_trk_g1_1 (16 4) routing sp4_h_r_17 <X> lc_trk_g1_1 (16 4) routing sp4_h_r_9 <X> lc_trk_g1_1 (16 4) routing sp4_v_b_1 <X> lc_trk_g1_1 (16 4) routing sp4_v_b_9 <X> lc_trk_g1_1 (16 4) routing sp4_v_t_4 <X> lc_trk_g1_1 -(16 5) routing sp12_h_l_15 <X> lc_trk_g1_0 (16 5) routing sp12_h_r_8 <X> lc_trk_g1_0 -(16 5) routing sp4_h_r_0 <X> lc_trk_g1_0 (16 5) routing sp4_h_r_16 <X> lc_trk_g1_0 -(16 5) routing sp4_h_r_8 <X> lc_trk_g1_0 (16 5) routing sp4_v_b_0 <X> lc_trk_g1_0 (16 5) routing sp4_v_b_16 <X> lc_trk_g1_0 (16 5) routing sp4_v_b_8 <X> lc_trk_g1_0 -(16 6) routing sp12_h_l_10 <X> lc_trk_g1_5 -(16 6) routing sp12_h_r_21 <X> lc_trk_g1_5 (16 6) routing sp4_h_r_13 <X> lc_trk_g1_5 (16 6) routing sp4_h_r_21 <X> lc_trk_g1_5 (16 6) routing sp4_h_r_5 <X> lc_trk_g1_5 @@ -705,7 +623,6 @@ (16 7) routing sp12_h_r_20 <X> lc_trk_g1_4 (16 7) routing sp4_h_l_1 <X> lc_trk_g1_4 (16 7) routing sp4_h_l_9 <X> lc_trk_g1_4 -(16 7) routing sp4_h_r_4 <X> lc_trk_g1_4 (16 7) routing sp4_v_b_12 <X> lc_trk_g1_4 (16 7) routing sp4_v_b_20 <X> lc_trk_g1_4 (16 7) routing sp4_v_b_4 <X> lc_trk_g1_4 @@ -719,7 +636,6 @@ (16 8) routing sp4_v_t_20 <X> lc_trk_g2_1 (16 9) routing sp12_v_b_16 <X> lc_trk_g2_0 (16 9) routing sp12_v_t_7 <X> lc_trk_g2_0 -(16 9) routing sp4_h_r_24 <X> lc_trk_g2_0 (16 9) routing sp4_h_r_32 <X> lc_trk_g2_0 (16 9) routing sp4_h_r_40 <X> lc_trk_g2_0 (16 9) routing sp4_v_b_32 <X> lc_trk_g2_0 @@ -727,19 +643,15 @@ (16 9) routing sp4_v_t_13 <X> lc_trk_g2_0 (17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_t_4 lc_trk_g0_1 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => bot_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 @@ -763,10 +675,8 @@ (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_24 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 (17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4 @@ -795,8 +705,6 @@ (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 (17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 @@ -811,7 +719,6 @@ (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 (17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_13 lc_trk_g3_5 @@ -841,13 +748,9 @@ (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 (17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_2 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 @@ -856,7 +759,6 @@ (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 (17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => bot_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 @@ -873,7 +775,6 @@ (17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 @@ -885,12 +786,9 @@ (17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bot_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 @@ -898,9 +796,6 @@ (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 (17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_2 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 @@ -910,14 +805,12 @@ (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 (17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => bot_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_1 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_12 lc_trk_g1_4 @@ -925,7 +818,6 @@ (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 (17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 @@ -937,13 +829,11 @@ (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 (17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 @@ -952,16 +842,13 @@ (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 (18 0) routing bnr_op_1 <X> lc_trk_g0_1 (18 0) routing lft_op_1 <X> lc_trk_g0_1 (18 0) routing sp12_h_r_1 <X> lc_trk_g0_1 (18 0) routing sp4_h_r_17 <X> lc_trk_g0_1 -(18 0) routing sp4_h_r_9 <X> lc_trk_g0_1 (18 0) routing sp4_v_b_1 <X> lc_trk_g0_1 (18 0) routing sp4_v_b_9 <X> lc_trk_g0_1 (18 1) routing bnr_op_1 <X> lc_trk_g0_1 -(18 1) routing sp12_h_l_14 <X> lc_trk_g0_1 (18 1) routing sp12_h_r_1 <X> lc_trk_g0_1 (18 1) routing sp4_h_r_1 <X> lc_trk_g0_1 (18 1) routing sp4_h_r_17 <X> lc_trk_g0_1 @@ -996,7 +883,6 @@ (18 13) routing sp4_h_r_25 <X> lc_trk_g3_1 (18 13) routing sp4_r_v_b_41 <X> lc_trk_g3_1 (18 13) routing sp4_v_t_20 <X> lc_trk_g3_1 -(18 13) routing tnl_op_1 <X> lc_trk_g3_1 (18 14) routing bnl_op_5 <X> lc_trk_g3_5 (18 14) routing rgt_op_5 <X> lc_trk_g3_5 (18 14) routing sp12_v_b_5 <X> lc_trk_g3_5 @@ -1014,14 +900,11 @@ (18 15) routing tnl_op_5 <X> lc_trk_g3_5 (18 2) routing bnr_op_5 <X> lc_trk_g0_5 (18 2) routing lft_op_5 <X> lc_trk_g0_5 -(18 2) routing sp12_h_l_2 <X> lc_trk_g0_5 (18 2) routing sp4_h_r_13 <X> lc_trk_g0_5 (18 2) routing sp4_h_r_21 <X> lc_trk_g0_5 (18 2) routing sp4_v_b_13 <X> lc_trk_g0_5 (18 2) routing sp4_v_b_5 <X> lc_trk_g0_5 (18 3) routing bnr_op_5 <X> lc_trk_g0_5 -(18 3) routing sp12_h_l_2 <X> lc_trk_g0_5 -(18 3) routing sp12_h_r_21 <X> lc_trk_g0_5 (18 3) routing sp4_h_r_21 <X> lc_trk_g0_5 (18 3) routing sp4_h_r_5 <X> lc_trk_g0_5 (18 3) routing sp4_r_v_b_29 <X> lc_trk_g0_5 @@ -1042,27 +925,22 @@ (18 5) routing sp4_v_b_9 <X> lc_trk_g1_1 (18 6) routing bnr_op_5 <X> lc_trk_g1_5 (18 6) routing lft_op_5 <X> lc_trk_g1_5 -(18 6) routing sp12_h_l_2 <X> lc_trk_g1_5 (18 6) routing sp4_h_r_13 <X> lc_trk_g1_5 (18 6) routing sp4_h_r_21 <X> lc_trk_g1_5 (18 6) routing sp4_v_b_13 <X> lc_trk_g1_5 (18 6) routing sp4_v_b_5 <X> lc_trk_g1_5 (18 7) routing bnr_op_5 <X> lc_trk_g1_5 -(18 7) routing sp12_h_l_2 <X> lc_trk_g1_5 -(18 7) routing sp12_h_r_21 <X> lc_trk_g1_5 (18 7) routing sp4_h_r_21 <X> lc_trk_g1_5 (18 7) routing sp4_h_r_5 <X> lc_trk_g1_5 (18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5 (18 7) routing sp4_v_b_13 <X> lc_trk_g1_5 (18 8) routing bnl_op_1 <X> lc_trk_g2_1 (18 8) routing rgt_op_1 <X> lc_trk_g2_1 -(18 8) routing sp12_v_b_1 <X> lc_trk_g2_1 (18 8) routing sp4_h_l_28 <X> lc_trk_g2_1 (18 8) routing sp4_h_r_33 <X> lc_trk_g2_1 (18 8) routing sp4_v_b_25 <X> lc_trk_g2_1 (18 8) routing sp4_v_t_20 <X> lc_trk_g2_1 (18 9) routing bnl_op_1 <X> lc_trk_g2_1 -(18 9) routing sp12_v_b_1 <X> lc_trk_g2_1 (18 9) routing sp12_v_t_14 <X> lc_trk_g2_1 (18 9) routing sp4_h_l_28 <X> lc_trk_g2_1 (18 9) routing sp4_h_r_25 <X> lc_trk_g2_1 @@ -1089,13 +967,11 @@ (2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_r_21 (2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_l_11 (2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_r_23 -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/RCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/RCLK @@ -1112,7 +988,6 @@ (21 0) routing lft_op_3 <X> lc_trk_g0_3 (21 0) routing sp12_h_r_3 <X> lc_trk_g0_3 (21 0) routing sp4_h_l_6 <X> lc_trk_g0_3 -(21 0) routing sp4_h_r_11 <X> lc_trk_g0_3 (21 0) routing sp4_v_b_11 <X> lc_trk_g0_3 (21 0) routing sp4_v_b_3 <X> lc_trk_g0_3 (21 1) routing bnr_op_3 <X> lc_trk_g0_3 @@ -1125,18 +1000,15 @@ (21 10) routing bnl_op_7 <X> lc_trk_g2_7 (21 10) routing rgt_op_7 <X> lc_trk_g2_7 (21 10) routing sp12_v_t_4 <X> lc_trk_g2_7 -(21 10) routing sp4_h_l_26 <X> lc_trk_g2_7 (21 10) routing sp4_h_r_47 <X> lc_trk_g2_7 (21 10) routing sp4_v_b_31 <X> lc_trk_g2_7 (21 10) routing sp4_v_t_26 <X> lc_trk_g2_7 (21 11) routing bnl_op_7 <X> lc_trk_g2_7 -(21 11) routing sp12_v_t_20 <X> lc_trk_g2_7 (21 11) routing sp12_v_t_4 <X> lc_trk_g2_7 (21 11) routing sp4_h_r_31 <X> lc_trk_g2_7 (21 11) routing sp4_h_r_47 <X> lc_trk_g2_7 (21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7 (21 11) routing sp4_v_t_26 <X> lc_trk_g2_7 -(21 11) routing tnl_op_7 <X> lc_trk_g2_7 (21 12) routing bnl_op_3 <X> lc_trk_g3_3 (21 12) routing rgt_op_3 <X> lc_trk_g3_3 (21 12) routing sp12_v_b_3 <X> lc_trk_g3_3 @@ -1151,58 +1023,49 @@ (21 13) routing sp4_h_r_43 <X> lc_trk_g3_3 (21 13) routing sp4_r_v_b_43 <X> lc_trk_g3_3 (21 13) routing sp4_v_b_35 <X> lc_trk_g3_3 -(21 13) routing tnl_op_3 <X> lc_trk_g3_3 (21 14) routing bnl_op_7 <X> lc_trk_g3_7 (21 14) routing rgt_op_7 <X> lc_trk_g3_7 (21 14) routing sp12_v_t_4 <X> lc_trk_g3_7 (21 14) routing sp4_h_l_26 <X> lc_trk_g3_7 -(21 14) routing sp4_h_r_47 <X> lc_trk_g3_7 (21 14) routing sp4_v_b_31 <X> lc_trk_g3_7 (21 14) routing sp4_v_t_26 <X> lc_trk_g3_7 (21 15) routing bnl_op_7 <X> lc_trk_g3_7 (21 15) routing sp12_v_t_20 <X> lc_trk_g3_7 (21 15) routing sp12_v_t_4 <X> lc_trk_g3_7 (21 15) routing sp4_h_r_31 <X> lc_trk_g3_7 -(21 15) routing sp4_h_r_47 <X> lc_trk_g3_7 (21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7 (21 15) routing sp4_v_t_26 <X> lc_trk_g3_7 (21 15) routing tnl_op_7 <X> lc_trk_g3_7 (21 2) routing bnr_op_7 <X> lc_trk_g0_7 (21 2) routing lft_op_7 <X> lc_trk_g0_7 -(21 2) routing sp12_h_r_7 <X> lc_trk_g0_7 (21 2) routing sp4_h_r_15 <X> lc_trk_g0_7 (21 2) routing sp4_h_r_23 <X> lc_trk_g0_7 (21 2) routing sp4_v_b_7 <X> lc_trk_g0_7 (21 2) routing sp4_v_t_2 <X> lc_trk_g0_7 (21 3) routing bnr_op_7 <X> lc_trk_g0_7 (21 3) routing sp12_h_l_20 <X> lc_trk_g0_7 -(21 3) routing sp12_h_r_7 <X> lc_trk_g0_7 (21 3) routing sp4_h_r_23 <X> lc_trk_g0_7 (21 3) routing sp4_h_r_7 <X> lc_trk_g0_7 (21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7 (21 3) routing sp4_v_t_2 <X> lc_trk_g0_7 -(21 4) routing bnr_op_3 <X> lc_trk_g1_3 (21 4) routing lft_op_3 <X> lc_trk_g1_3 (21 4) routing sp12_h_r_3 <X> lc_trk_g1_3 (21 4) routing sp4_h_l_6 <X> lc_trk_g1_3 (21 4) routing sp4_h_r_11 <X> lc_trk_g1_3 (21 4) routing sp4_v_b_11 <X> lc_trk_g1_3 (21 4) routing sp4_v_b_3 <X> lc_trk_g1_3 -(21 5) routing bnr_op_3 <X> lc_trk_g1_3 (21 5) routing sp12_h_l_16 <X> lc_trk_g1_3 (21 5) routing sp12_h_r_3 <X> lc_trk_g1_3 (21 5) routing sp4_h_l_6 <X> lc_trk_g1_3 (21 5) routing sp4_h_r_3 <X> lc_trk_g1_3 (21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3 (21 5) routing sp4_v_b_11 <X> lc_trk_g1_3 -(21 6) routing bnr_op_7 <X> lc_trk_g1_7 (21 6) routing lft_op_7 <X> lc_trk_g1_7 (21 6) routing sp12_h_r_7 <X> lc_trk_g1_7 (21 6) routing sp4_h_r_15 <X> lc_trk_g1_7 (21 6) routing sp4_h_r_23 <X> lc_trk_g1_7 (21 6) routing sp4_v_b_7 <X> lc_trk_g1_7 (21 6) routing sp4_v_t_2 <X> lc_trk_g1_7 -(21 7) routing bnr_op_7 <X> lc_trk_g1_7 (21 7) routing sp12_h_l_20 <X> lc_trk_g1_7 (21 7) routing sp12_h_r_7 <X> lc_trk_g1_7 (21 7) routing sp4_h_r_23 <X> lc_trk_g1_7 @@ -1211,14 +1074,11 @@ (21 7) routing sp4_v_t_2 <X> lc_trk_g1_7 (21 8) routing bnl_op_3 <X> lc_trk_g2_3 (21 8) routing rgt_op_3 <X> lc_trk_g2_3 -(21 8) routing sp12_v_b_3 <X> lc_trk_g2_3 -(21 8) routing sp4_h_l_22 <X> lc_trk_g2_3 (21 8) routing sp4_h_r_43 <X> lc_trk_g2_3 (21 8) routing sp4_v_b_27 <X> lc_trk_g2_3 (21 8) routing sp4_v_b_35 <X> lc_trk_g2_3 (21 9) routing bnl_op_3 <X> lc_trk_g2_3 (21 9) routing sp12_v_b_19 <X> lc_trk_g2_3 -(21 9) routing sp12_v_b_3 <X> lc_trk_g2_3 (21 9) routing sp4_h_l_14 <X> lc_trk_g2_3 (21 9) routing sp4_h_r_43 <X> lc_trk_g2_3 (21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3 @@ -1230,7 +1090,6 @@ (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_l_6 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 @@ -1238,11 +1097,9 @@ (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_t_6 lc_trk_g0_3 (22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => bot_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_1 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_18 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 @@ -1254,9 +1111,7 @@ (22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_20 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 @@ -1264,8 +1119,6 @@ (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_31 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 (22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 @@ -1294,8 +1147,6 @@ (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_43 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 (22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_10 lc_trk_g3_2 @@ -1310,7 +1161,6 @@ (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 (22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 @@ -1318,14 +1168,12 @@ (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_31 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 (22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 @@ -1336,7 +1184,6 @@ (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_27 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 @@ -1346,7 +1193,6 @@ (22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 @@ -1355,11 +1201,9 @@ (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 (22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => bot_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 @@ -1368,7 +1212,6 @@ (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 @@ -1395,7 +1238,6 @@ (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 @@ -1409,26 +1251,19 @@ (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 (22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => bot_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6 (22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_14 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 @@ -1451,17 +1286,14 @@ (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 (23 0) routing sp12_h_l_16 <X> lc_trk_g0_3 (23 0) routing sp12_h_r_11 <X> lc_trk_g0_3 (23 0) routing sp4_h_l_6 <X> lc_trk_g0_3 -(23 0) routing sp4_h_r_11 <X> lc_trk_g0_3 (23 0) routing sp4_h_r_3 <X> lc_trk_g0_3 (23 0) routing sp4_v_b_11 <X> lc_trk_g0_3 (23 0) routing sp4_v_b_3 <X> lc_trk_g0_3 (23 0) routing sp4_v_t_6 <X> lc_trk_g0_3 (23 1) routing sp12_h_l_17 <X> lc_trk_g0_2 -(23 1) routing sp12_h_l_9 <X> lc_trk_g0_2 (23 1) routing sp4_h_r_10 <X> lc_trk_g0_2 (23 1) routing sp4_h_r_18 <X> lc_trk_g0_2 (23 1) routing sp4_h_r_2 <X> lc_trk_g0_2 @@ -1469,8 +1301,6 @@ (23 1) routing sp4_v_b_2 <X> lc_trk_g0_2 (23 1) routing sp4_v_t_7 <X> lc_trk_g0_2 (23 10) routing sp12_v_t_12 <X> lc_trk_g2_7 -(23 10) routing sp12_v_t_20 <X> lc_trk_g2_7 -(23 10) routing sp4_h_l_26 <X> lc_trk_g2_7 (23 10) routing sp4_h_r_31 <X> lc_trk_g2_7 (23 10) routing sp4_h_r_47 <X> lc_trk_g2_7 (23 10) routing sp4_v_b_31 <X> lc_trk_g2_7 @@ -1504,7 +1334,6 @@ (23 14) routing sp12_v_t_20 <X> lc_trk_g3_7 (23 14) routing sp4_h_l_26 <X> lc_trk_g3_7 (23 14) routing sp4_h_r_31 <X> lc_trk_g3_7 -(23 14) routing sp4_h_r_47 <X> lc_trk_g3_7 (23 14) routing sp4_v_b_31 <X> lc_trk_g3_7 (23 14) routing sp4_v_t_26 <X> lc_trk_g3_7 (23 14) routing sp4_v_t_34 <X> lc_trk_g3_7 @@ -1513,7 +1342,6 @@ (23 15) routing sp4_h_l_19 <X> lc_trk_g3_6 (23 15) routing sp4_h_l_27 <X> lc_trk_g3_6 (23 15) routing sp4_h_r_46 <X> lc_trk_g3_6 -(23 15) routing sp4_v_b_46 <X> lc_trk_g3_6 (23 15) routing sp4_v_t_19 <X> lc_trk_g3_6 (23 15) routing sp4_v_t_27 <X> lc_trk_g3_6 (23 2) routing sp12_h_l_12 <X> lc_trk_g0_7 @@ -1524,7 +1352,6 @@ (23 2) routing sp4_v_b_23 <X> lc_trk_g0_7 (23 2) routing sp4_v_b_7 <X> lc_trk_g0_7 (23 2) routing sp4_v_t_2 <X> lc_trk_g0_7 -(23 3) routing sp12_h_r_14 <X> lc_trk_g0_6 (23 3) routing sp12_h_r_22 <X> lc_trk_g0_6 (23 3) routing sp4_h_l_11 <X> lc_trk_g0_6 (23 3) routing sp4_h_l_3 <X> lc_trk_g0_6 @@ -1557,17 +1384,12 @@ (23 6) routing sp4_v_b_7 <X> lc_trk_g1_7 (23 6) routing sp4_v_t_2 <X> lc_trk_g1_7 (23 7) routing sp12_h_r_14 <X> lc_trk_g1_6 -(23 7) routing sp12_h_r_22 <X> lc_trk_g1_6 (23 7) routing sp4_h_l_11 <X> lc_trk_g1_6 (23 7) routing sp4_h_l_3 <X> lc_trk_g1_6 (23 7) routing sp4_h_r_6 <X> lc_trk_g1_6 -(23 7) routing sp4_v_b_14 <X> lc_trk_g1_6 -(23 7) routing sp4_v_b_6 <X> lc_trk_g1_6 (23 7) routing sp4_v_t_11 <X> lc_trk_g1_6 (23 8) routing sp12_v_b_19 <X> lc_trk_g2_3 -(23 8) routing sp12_v_t_8 <X> lc_trk_g2_3 (23 8) routing sp4_h_l_14 <X> lc_trk_g2_3 -(23 8) routing sp4_h_l_22 <X> lc_trk_g2_3 (23 8) routing sp4_h_r_43 <X> lc_trk_g2_3 (23 8) routing sp4_v_b_27 <X> lc_trk_g2_3 (23 8) routing sp4_v_b_35 <X> lc_trk_g2_3 @@ -1583,10 +1405,8 @@ (24 0) routing lft_op_3 <X> lc_trk_g0_3 (24 0) routing sp12_h_r_3 <X> lc_trk_g0_3 (24 0) routing sp4_h_l_6 <X> lc_trk_g0_3 -(24 0) routing sp4_h_r_11 <X> lc_trk_g0_3 (24 0) routing sp4_h_r_3 <X> lc_trk_g0_3 (24 0) routing sp4_v_t_6 <X> lc_trk_g0_3 -(24 1) routing bot_op_2 <X> lc_trk_g0_2 (24 1) routing lft_op_2 <X> lc_trk_g0_2 (24 1) routing sp12_h_l_1 <X> lc_trk_g0_2 (24 1) routing sp4_h_r_10 <X> lc_trk_g0_2 @@ -1595,12 +1415,9 @@ (24 1) routing sp4_v_t_7 <X> lc_trk_g0_2 (24 10) routing rgt_op_7 <X> lc_trk_g2_7 (24 10) routing sp12_v_t_4 <X> lc_trk_g2_7 -(24 10) routing sp4_h_l_26 <X> lc_trk_g2_7 (24 10) routing sp4_h_r_31 <X> lc_trk_g2_7 (24 10) routing sp4_h_r_47 <X> lc_trk_g2_7 (24 10) routing sp4_v_t_34 <X> lc_trk_g2_7 -(24 10) routing tnl_op_7 <X> lc_trk_g2_7 -(24 10) routing tnr_op_7 <X> lc_trk_g2_7 (24 11) routing rgt_op_6 <X> lc_trk_g2_6 (24 11) routing sp12_v_t_5 <X> lc_trk_g2_6 (24 11) routing sp4_h_l_19 <X> lc_trk_g2_6 @@ -1615,8 +1432,6 @@ (24 12) routing sp4_h_l_22 <X> lc_trk_g3_3 (24 12) routing sp4_h_r_43 <X> lc_trk_g3_3 (24 12) routing sp4_v_b_43 <X> lc_trk_g3_3 -(24 12) routing tnl_op_3 <X> lc_trk_g3_3 -(24 12) routing tnr_op_3 <X> lc_trk_g3_3 (24 13) routing rgt_op_2 <X> lc_trk_g3_2 (24 13) routing sp12_v_t_1 <X> lc_trk_g3_2 (24 13) routing sp4_h_l_15 <X> lc_trk_g3_2 @@ -1624,30 +1439,24 @@ (24 13) routing sp4_h_r_42 <X> lc_trk_g3_2 (24 13) routing sp4_v_t_31 <X> lc_trk_g3_2 (24 13) routing tnl_op_2 <X> lc_trk_g3_2 -(24 13) routing tnr_op_2 <X> lc_trk_g3_2 (24 14) routing rgt_op_7 <X> lc_trk_g3_7 (24 14) routing sp12_v_t_4 <X> lc_trk_g3_7 (24 14) routing sp4_h_l_26 <X> lc_trk_g3_7 (24 14) routing sp4_h_r_31 <X> lc_trk_g3_7 -(24 14) routing sp4_h_r_47 <X> lc_trk_g3_7 (24 14) routing sp4_v_t_34 <X> lc_trk_g3_7 (24 14) routing tnl_op_7 <X> lc_trk_g3_7 -(24 14) routing tnr_op_7 <X> lc_trk_g3_7 (24 15) routing rgt_op_6 <X> lc_trk_g3_6 (24 15) routing sp12_v_t_5 <X> lc_trk_g3_6 (24 15) routing sp4_h_l_19 <X> lc_trk_g3_6 (24 15) routing sp4_h_l_27 <X> lc_trk_g3_6 (24 15) routing sp4_h_r_46 <X> lc_trk_g3_6 -(24 15) routing sp4_v_b_46 <X> lc_trk_g3_6 (24 15) routing tnl_op_6 <X> lc_trk_g3_6 (24 15) routing tnr_op_6 <X> lc_trk_g3_6 (24 2) routing lft_op_7 <X> lc_trk_g0_7 -(24 2) routing sp12_h_r_7 <X> lc_trk_g0_7 (24 2) routing sp4_h_r_15 <X> lc_trk_g0_7 (24 2) routing sp4_h_r_23 <X> lc_trk_g0_7 (24 2) routing sp4_h_r_7 <X> lc_trk_g0_7 (24 2) routing sp4_v_b_23 <X> lc_trk_g0_7 -(24 3) routing bot_op_6 <X> lc_trk_g0_6 (24 3) routing lft_op_6 <X> lc_trk_g0_6 (24 3) routing sp12_h_l_5 <X> lc_trk_g0_6 (24 3) routing sp4_h_l_11 <X> lc_trk_g0_6 @@ -1673,7 +1482,6 @@ (24 6) routing sp4_h_r_23 <X> lc_trk_g1_7 (24 6) routing sp4_h_r_7 <X> lc_trk_g1_7 (24 6) routing sp4_v_b_23 <X> lc_trk_g1_7 -(24 7) routing bot_op_6 <X> lc_trk_g1_6 (24 7) routing lft_op_6 <X> lc_trk_g1_6 (24 7) routing sp12_h_l_5 <X> lc_trk_g1_6 (24 7) routing sp4_h_l_11 <X> lc_trk_g1_6 @@ -1681,9 +1489,7 @@ (24 7) routing sp4_h_r_6 <X> lc_trk_g1_6 (24 7) routing sp4_v_t_11 <X> lc_trk_g1_6 (24 8) routing rgt_op_3 <X> lc_trk_g2_3 -(24 8) routing sp12_v_b_3 <X> lc_trk_g2_3 (24 8) routing sp4_h_l_14 <X> lc_trk_g2_3 -(24 8) routing sp4_h_l_22 <X> lc_trk_g2_3 (24 8) routing sp4_h_r_43 <X> lc_trk_g2_3 (24 8) routing sp4_v_b_43 <X> lc_trk_g2_3 (24 8) routing tnl_op_3 <X> lc_trk_g2_3 @@ -1695,7 +1501,6 @@ (24 9) routing sp4_h_r_42 <X> lc_trk_g2_2 (24 9) routing sp4_v_t_31 <X> lc_trk_g2_2 (24 9) routing tnl_op_2 <X> lc_trk_g2_2 -(24 9) routing tnr_op_2 <X> lc_trk_g2_2 (25 0) routing bnr_op_2 <X> lc_trk_g0_2 (25 0) routing lft_op_2 <X> lc_trk_g0_2 (25 0) routing sp12_h_l_1 <X> lc_trk_g0_2 @@ -1788,15 +1593,11 @@ (25 6) routing sp12_h_l_5 <X> lc_trk_g1_6 (25 6) routing sp4_h_l_11 <X> lc_trk_g1_6 (25 6) routing sp4_h_l_3 <X> lc_trk_g1_6 -(25 6) routing sp4_v_b_14 <X> lc_trk_g1_6 -(25 6) routing sp4_v_b_6 <X> lc_trk_g1_6 (25 7) routing bnr_op_6 <X> lc_trk_g1_6 (25 7) routing sp12_h_l_5 <X> lc_trk_g1_6 -(25 7) routing sp12_h_r_22 <X> lc_trk_g1_6 (25 7) routing sp4_h_l_11 <X> lc_trk_g1_6 (25 7) routing sp4_h_r_6 <X> lc_trk_g1_6 (25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6 -(25 7) routing sp4_v_b_14 <X> lc_trk_g1_6 (25 8) routing bnl_op_2 <X> lc_trk_g2_2 (25 8) routing rgt_op_2 <X> lc_trk_g2_2 (25 8) routing sp12_v_t_1 <X> lc_trk_g2_2 @@ -1941,11 +1742,8 @@ (26 9) routing lc_trk_g3_3 <X> input0_4 (26 9) routing lc_trk_g3_7 <X> input0_4 (27 0) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15 (27 1) routing lc_trk_g1_1 <X> input0_0 @@ -1956,14 +1754,10 @@ (27 1) routing lc_trk_g3_3 <X> input0_0 (27 1) routing lc_trk_g3_5 <X> input0_0 (27 1) routing lc_trk_g3_7 <X> input0_0 -(27 10) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_10 (27 11) routing lc_trk_g1_0 <X> input0_5 (27 11) routing lc_trk_g1_2 <X> input0_5 (27 11) routing lc_trk_g1_4 <X> input0_5 @@ -1990,12 +1784,8 @@ (27 13) routing lc_trk_g3_7 <X> input0_6 (27 14) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_8 (27 15) routing lc_trk_g1_0 <X> input0_7 (27 15) routing lc_trk_g1_2 <X> input0_7 (27 15) routing lc_trk_g1_4 <X> input0_7 @@ -2006,12 +1796,9 @@ (27 15) routing lc_trk_g3_6 <X> input0_7 (27 2) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_14 (27 3) routing lc_trk_g1_0 <X> input0_1 (27 3) routing lc_trk_g1_2 <X> input0_1 (27 3) routing lc_trk_g1_4 <X> input0_1 @@ -2036,10 +1823,7 @@ (27 5) routing lc_trk_g3_3 <X> input0_2 (27 5) routing lc_trk_g3_5 <X> input0_2 (27 5) routing lc_trk_g3_7 <X> input0_2 -(27 6) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_12 @@ -2053,12 +1837,10 @@ (27 7) routing lc_trk_g3_4 <X> input0_3 (27 7) routing lc_trk_g3_6 <X> input0_3 (27 8) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_11 -(27 8) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_11 -(27 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_11 (27 9) routing lc_trk_g1_1 <X> input0_4 (27 9) routing lc_trk_g1_3 <X> input0_4 @@ -2070,10 +1852,8 @@ (27 9) routing lc_trk_g3_7 <X> input0_4 (28 0) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_15 -(28 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_15 -(28 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15 (28 1) routing lc_trk_g2_0 <X> input0_0 @@ -2084,14 +1864,10 @@ (28 1) routing lc_trk_g3_3 <X> input0_0 (28 1) routing lc_trk_g3_5 <X> input0_0 (28 1) routing lc_trk_g3_7 <X> input0_0 -(28 10) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_10 (28 11) routing lc_trk_g2_1 <X> input0_5 (28 11) routing lc_trk_g2_3 <X> input0_5 (28 11) routing lc_trk_g2_5 <X> input0_5 @@ -2119,11 +1895,8 @@ (28 14) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_8 (28 15) routing lc_trk_g2_1 <X> input0_7 (28 15) routing lc_trk_g2_3 <X> input0_7 (28 15) routing lc_trk_g2_5 <X> input0_7 @@ -2133,13 +1906,10 @@ (28 15) routing lc_trk_g3_4 <X> input0_7 (28 15) routing lc_trk_g3_6 <X> input0_7 (28 2) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_14 (28 3) routing lc_trk_g2_1 <X> input0_1 (28 3) routing lc_trk_g2_3 <X> input0_1 (28 3) routing lc_trk_g2_5 <X> input0_1 @@ -2166,7 +1936,6 @@ (28 5) routing lc_trk_g3_7 <X> input0_2 (28 6) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_12 -(28 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_12 @@ -2180,13 +1949,11 @@ (28 7) routing lc_trk_g3_2 <X> input0_3 (28 7) routing lc_trk_g3_4 <X> input0_3 (28 7) routing lc_trk_g3_6 <X> input0_3 -(28 8) routing lc_trk_g2_1 <X> wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_11 -(28 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_11 (28 9) routing lc_trk_g2_0 <X> input0_4 (28 9) routing lc_trk_g2_2 <X> input0_4 @@ -2198,18 +1965,12 @@ (28 9) routing lc_trk_g3_7 <X> input0_4 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_15 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 @@ -2232,18 +1993,11 @@ (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_10 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5 @@ -2293,21 +2047,15 @@ (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_8 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7 @@ -2325,21 +2073,16 @@ (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_14 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1 @@ -2390,15 +2133,9 @@ (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_12 @@ -2421,20 +2158,15 @@ (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_11 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4 @@ -2484,38 +2216,22 @@ (3 8) routing sp12_v_t_22 <X> sp12_v_b_1 (3 9) routing sp12_h_l_22 <X> sp12_v_b_1 (3 9) routing sp12_h_r_1 <X> sp12_v_b_1 -(30 0) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_15 (30 10) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_10 (30 12) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_9 @@ -2534,36 +2250,21 @@ (30 13) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_9 (30 14) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_8 (30 2) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_14 (30 4) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_13 @@ -2580,33 +2281,22 @@ (30 5) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_13 -(30 6) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_12 -(30 8) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_11 -(30 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_11 -(30 9) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_11 -(30 9) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_11 @@ -2615,89 +2305,58 @@ (31 0) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_15 (31 0) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_15 (31 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_15 (31 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_15 (31 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15 (31 1) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_15 (31 1) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_15 (31 1) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_15 (31 1) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_15 (31 1) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15 (31 10) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_10 (31 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_10 (31 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_10 (31 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_10 (31 11) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_10 -(31 11) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_10 (31 11) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_10 (31 11) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_10 (31 11) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_10 -(31 11) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_10 (31 11) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_10 (31 11) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_10 -(31 12) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_9 (31 12) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_9 (31 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_9 (31 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_9 (31 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_9 (31 13) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_9 (31 13) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_9 (31 13) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_9 (31 13) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_9 (31 13) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_9 (31 14) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_8 (31 14) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_8 (31 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_8 (31 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_8 (31 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_8 (31 15) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_8 (31 15) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_8 (31 15) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_8 (31 15) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_8 (31 15) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_8 (31 2) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_14 (31 2) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_14 -(31 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_14 (31 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_14 (31 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_14 (31 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_14 (31 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_14 (31 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_14 -(31 3) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_14 (31 3) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_14 (31 3) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_14 (31 3) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_14 (31 3) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_14 (31 3) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_14 -(31 3) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_14 (31 3) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_14 -(31 4) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_13 (31 4) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_13 (31 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_13 (31 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_13 -(31 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_13 -(31 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_13 (31 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_13 (31 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_13 (31 5) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_13 @@ -2705,40 +2364,25 @@ (31 5) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_13 (31 5) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_13 (31 5) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_13 -(31 5) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_13 (31 5) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_13 (31 5) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_13 (31 6) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_12 (31 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_12 (31 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_12 (31 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_12 (31 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12 (31 7) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_12 (31 7) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_12 (31 7) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_12 (31 7) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_12 (31 7) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12 (31 8) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_11 (31 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_11 (31 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_11 (31 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_11 (31 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_11 (31 9) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_11 (31 9) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_11 (31 9) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_11 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_15 @@ -2746,60 +2390,39 @@ (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_15 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_10 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_9 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6 @@ -2821,16 +2444,10 @@ (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_8 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_1 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_3 input2_7 @@ -2843,44 +2460,34 @@ (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_1 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_3 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_5 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_7 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_0 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_2 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_14 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_13 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_12 @@ -2888,57 +2495,37 @@ (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_11 (33 0) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_15 (33 0) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_15 (33 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_15 -(33 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_15 -(33 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15 (33 10) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_10 (33 10) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_10 (33 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_10 -(33 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_10 -(33 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_10 -(33 11) routing lc_trk_g2_1 <X> input2_5 (33 11) routing lc_trk_g2_3 <X> input2_5 -(33 11) routing lc_trk_g2_5 <X> input2_5 -(33 11) routing lc_trk_g2_7 <X> input2_5 (33 11) routing lc_trk_g3_0 <X> input2_5 -(33 11) routing lc_trk_g3_2 <X> input2_5 (33 11) routing lc_trk_g3_4 <X> input2_5 (33 11) routing lc_trk_g3_6 <X> input2_5 (33 12) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_9 -(33 12) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_9 (33 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_9 -(33 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_9 -(33 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_9 (33 13) routing lc_trk_g2_0 <X> input2_6 (33 13) routing lc_trk_g2_2 <X> input2_6 @@ -2952,14 +2539,10 @@ (33 14) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_8 (33 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_8 (33 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_8 -(33 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_8 -(33 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_8 -(33 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_8 (33 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_8 (33 15) routing lc_trk_g2_1 <X> input2_7 (33 15) routing lc_trk_g2_3 <X> input2_7 (33 15) routing lc_trk_g2_5 <X> input2_7 -(33 15) routing lc_trk_g2_7 <X> input2_7 (33 15) routing lc_trk_g3_0 <X> input2_7 (33 15) routing lc_trk_g3_2 <X> input2_7 (33 15) routing lc_trk_g3_4 <X> input2_7 @@ -2969,13 +2552,10 @@ (33 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_14 (33 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_14 -(33 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_14 (33 4) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_13 (33 4) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_13 -(33 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_13 -(33 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_13 @@ -2983,50 +2563,34 @@ (33 6) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_12 (33 6) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_12 (33 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_12 (33 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12 (33 8) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_11 (33 8) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_11 (33 8) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_11 -(33 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_11 -(33 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_11 (34 0) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_15 (34 0) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_15 (34 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_15 -(34 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_15 -(34 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_15 (34 10) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_10 (34 10) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_10 -(34 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_10 (34 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_10 -(34 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_10 (34 11) routing lc_trk_g1_0 <X> input2_5 -(34 11) routing lc_trk_g1_2 <X> input2_5 (34 11) routing lc_trk_g1_4 <X> input2_5 -(34 11) routing lc_trk_g1_6 <X> input2_5 (34 11) routing lc_trk_g3_0 <X> input2_5 -(34 11) routing lc_trk_g3_2 <X> input2_5 (34 11) routing lc_trk_g3_4 <X> input2_5 (34 11) routing lc_trk_g3_6 <X> input2_5 -(34 12) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_9 (34 12) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_9 (34 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_9 -(34 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_9 -(34 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_9 (34 13) routing lc_trk_g1_1 <X> input2_6 (34 13) routing lc_trk_g1_3 <X> input2_6 @@ -3037,12 +2601,6 @@ (34 13) routing lc_trk_g3_5 <X> input2_6 (34 13) routing lc_trk_g3_7 <X> input2_6 (34 14) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_8 (34 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_8 (34 15) routing lc_trk_g1_0 <X> input2_7 (34 15) routing lc_trk_g1_2 <X> input2_7 @@ -3052,15 +2610,11 @@ (34 15) routing lc_trk_g3_2 <X> input2_7 (34 15) routing lc_trk_g3_4 <X> input2_7 (34 15) routing lc_trk_g3_6 <X> input2_7 -(34 2) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_14 (34 2) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_14 -(34 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_14 (34 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_14 -(34 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_14 -(34 4) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_13 @@ -3072,33 +2626,19 @@ (34 6) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_12 (34 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_12 (34 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_12 (34 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_12 (34 8) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_11 (34 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_11 -(35 10) routing lc_trk_g0_5 <X> input2_5 (35 10) routing lc_trk_g0_7 <X> input2_5 (35 10) routing lc_trk_g1_4 <X> input2_5 -(35 10) routing lc_trk_g1_6 <X> input2_5 -(35 10) routing lc_trk_g2_5 <X> input2_5 -(35 10) routing lc_trk_g2_7 <X> input2_5 (35 10) routing lc_trk_g3_4 <X> input2_5 (35 10) routing lc_trk_g3_6 <X> input2_5 (35 11) routing lc_trk_g0_3 <X> input2_5 (35 11) routing lc_trk_g0_7 <X> input2_5 -(35 11) routing lc_trk_g1_2 <X> input2_5 -(35 11) routing lc_trk_g1_6 <X> input2_5 (35 11) routing lc_trk_g2_3 <X> input2_5 -(35 11) routing lc_trk_g2_7 <X> input2_5 -(35 11) routing lc_trk_g3_2 <X> input2_5 (35 11) routing lc_trk_g3_6 <X> input2_5 (35 12) routing lc_trk_g0_4 <X> input2_6 (35 12) routing lc_trk_g0_6 <X> input2_6 @@ -3121,7 +2661,6 @@ (35 14) routing lc_trk_g1_4 <X> input2_7 (35 14) routing lc_trk_g1_6 <X> input2_7 (35 14) routing lc_trk_g2_5 <X> input2_7 -(35 14) routing lc_trk_g2_7 <X> input2_7 (35 14) routing lc_trk_g3_4 <X> input2_7 (35 14) routing lc_trk_g3_6 <X> input2_7 (35 15) routing lc_trk_g0_3 <X> input2_7 @@ -3129,25 +2668,15 @@ (35 15) routing lc_trk_g1_2 <X> input2_7 (35 15) routing lc_trk_g1_6 <X> input2_7 (35 15) routing lc_trk_g2_3 <X> input2_7 -(35 15) routing lc_trk_g2_7 <X> input2_7 (35 15) routing lc_trk_g3_2 <X> input2_7 (35 15) routing lc_trk_g3_6 <X> input2_7 (36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_15 sp4_h_r_32 -(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_15 sp4_h_r_0 -(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_10 sp4_h_r_42 -(36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_10 sp4_h_r_10 (36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_9 sp4_h_r_44 (36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_9 sp4_h_l_1 (36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_8 sp4_h_r_46 -(36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_8 sp4_h_l_3 (36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_14 sp4_h_r_34 -(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_14 sp4_h_r_2 (36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_13 sp4_h_r_36 (36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_13 sp4_h_r_4 -(36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_12 sp4_h_l_27 -(36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_12 sp4_h_r_6 -(36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_11 sp4_h_r_40 -(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_11 sp4_h_r_8 (37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_15 sp12_h_r_8 (37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_15 sp4_h_r_16 (37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_10 sp12_h_l_1 @@ -3166,20 +2695,15 @@ (37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_11 sp4_h_r_24 (38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_15 sp4_v_b_32 (38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_15 sp4_v_b_0 -(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_10 sp4_v_t_15 (38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_10 sp12_h_l_17 (38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_9 sp4_v_b_28 (38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_9 sp12_h_r_20 -(38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_8 sp4_v_t_19 (38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_8 sp12_h_r_22 (38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_14 sp4_v_b_34 (38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_14 sp4_v_b_2 (38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_13 sp4_v_t_25 (38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_13 sp4_v_b_4 (38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_12 sp4_v_t_27 -(38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_12 sp4_v_b_6 -(38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_11 sp4_v_t_13 -(38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_11 sp12_h_l_15 (39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_15 sp12_v_b_0 (39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_15 sp4_v_b_16 (39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_10 sp4_v_t_31 @@ -3261,12 +2785,8 @@ (4 9) routing sp4_v_b_0 <X> sp4_h_r_6 (4 9) routing sp4_v_t_36 <X> sp4_h_r_6 (40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_17 -(40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_15 sp12_v_b_16 -(40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_27 (40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_10 sp12_v_b_10 -(40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_29 (40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_9 sp12_v_t_11 -(40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_31 (40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_8 sp12_v_b_14 (40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_19 (40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_14 sp12_v_b_18 @@ -3285,7 +2805,6 @@ (41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_47 (41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_15 (41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_35 -(41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_3 (41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_37 (41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_5 (41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_39 @@ -3428,7 +2947,6 @@ (7 14) Column buffer control bit: MEMB_colbuf_cntl_7 (7 15) Column buffer control bit: MEMB_colbuf_cntl_6 (7 8) Column buffer control bit: MEMB_colbuf_cntl_1 -(7 9) Column buffer control bit: MEMB_colbuf_cntl_0 (8 0) routing sp4_h_l_36 <X> sp4_h_r_1 (8 0) routing sp4_h_l_40 <X> sp4_h_r_1 (8 0) routing sp4_v_b_1 <X> sp4_h_r_1 diff --git a/icefuzz/cached_ramt_5k.txt b/icefuzz/cached_ramt_5k.txt index 48708fe..768ae76 100644 --- a/icefuzz/cached_ramt_5k.txt +++ b/icefuzz/cached_ramt_5k.txt @@ -1,18 +1,9 @@ (0 0) Negative Clock bit (0 10) routing glb_netwk_3 <X> glb2local_2 (0 10) routing glb_netwk_6 <X> glb2local_2 -(0 10) routing glb_netwk_7 <X> glb2local_2 -(0 11) routing glb_netwk_1 <X> glb2local_2 (0 11) routing glb_netwk_3 <X> glb2local_2 (0 11) routing glb_netwk_5 <X> glb2local_2 -(0 11) routing glb_netwk_7 <X> glb2local_2 -(0 12) routing glb_netwk_3 <X> glb2local_3 -(0 12) routing glb_netwk_6 <X> glb2local_3 -(0 12) routing glb_netwk_7 <X> glb2local_3 -(0 13) routing glb_netwk_1 <X> glb2local_3 -(0 13) routing glb_netwk_3 <X> glb2local_3 (0 13) routing glb_netwk_5 <X> glb2local_3 -(0 13) routing glb_netwk_7 <X> glb2local_3 (0 14) routing glb_netwk_4 <X> wire_bram/ram/WE (0 14) routing glb_netwk_6 <X> wire_bram/ram/WE (0 14) routing lc_trk_g2_4 <X> wire_bram/ram/WE @@ -21,55 +12,31 @@ (0 15) routing lc_trk_g1_5 <X> wire_bram/ram/WE (0 15) routing lc_trk_g3_5 <X> wire_bram/ram/WE (0 2) routing glb_netwk_2 <X> wire_bram/ram/WCLK -(0 2) routing glb_netwk_3 <X> wire_bram/ram/WCLK -(0 2) routing glb_netwk_6 <X> wire_bram/ram/WCLK (0 2) routing glb_netwk_7 <X> wire_bram/ram/WCLK (0 2) routing lc_trk_g2_0 <X> wire_bram/ram/WCLK (0 2) routing lc_trk_g3_1 <X> wire_bram/ram/WCLK (0 3) routing glb_netwk_1 <X> wire_bram/ram/WCLK -(0 3) routing glb_netwk_3 <X> wire_bram/ram/WCLK (0 3) routing glb_netwk_5 <X> wire_bram/ram/WCLK (0 3) routing glb_netwk_7 <X> wire_bram/ram/WCLK (0 3) routing lc_trk_g1_1 <X> wire_bram/ram/WCLK (0 3) routing lc_trk_g3_1 <X> wire_bram/ram/WCLK -(0 4) routing glb_netwk_5 <X> wire_bram/ram/WCLKE (0 4) routing lc_trk_g2_2 <X> wire_bram/ram/WCLKE (0 4) routing lc_trk_g3_3 <X> wire_bram/ram/WCLKE -(0 5) routing glb_netwk_3 <X> wire_bram/ram/WCLKE (0 5) routing lc_trk_g1_3 <X> wire_bram/ram/WCLKE (0 5) routing lc_trk_g3_3 <X> wire_bram/ram/WCLKE (0 6) routing glb_netwk_3 <X> glb2local_0 -(0 6) routing glb_netwk_6 <X> glb2local_0 -(0 6) routing glb_netwk_7 <X> glb2local_0 -(0 7) routing glb_netwk_1 <X> glb2local_0 (0 7) routing glb_netwk_3 <X> glb2local_0 (0 7) routing glb_netwk_5 <X> glb2local_0 -(0 7) routing glb_netwk_7 <X> glb2local_0 -(0 8) routing glb_netwk_3 <X> glb2local_1 (0 8) routing glb_netwk_6 <X> glb2local_1 -(0 9) routing glb_netwk_1 <X> glb2local_1 -(0 9) routing glb_netwk_3 <X> glb2local_1 -(0 9) routing glb_netwk_5 <X> glb2local_1 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 (1 11) routing glb_netwk_4 <X> glb2local_2 (1 11) routing glb_netwk_5 <X> glb2local_2 (1 11) routing glb_netwk_6 <X> glb2local_2 -(1 11) routing glb_netwk_7 <X> glb2local_2 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 -(1 13) routing glb_netwk_4 <X> glb2local_3 (1 13) routing glb_netwk_5 <X> glb2local_3 -(1 13) routing glb_netwk_6 <X> glb2local_3 -(1 13) routing glb_netwk_7 <X> glb2local_3 (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/WE @@ -82,11 +49,8 @@ (1 15) routing lc_trk_g3_5 <X> wire_bram/ram/WE (1 2) routing glb_netwk_4 <X> wire_bram/ram/WCLK (1 2) routing glb_netwk_5 <X> wire_bram/ram/WCLK -(1 2) routing glb_netwk_6 <X> wire_bram/ram/WCLK (1 2) routing glb_netwk_7 <X> wire_bram/ram/WCLK (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_r_10 sp4_h_r_17 -(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_bram/ram/WCLKE -(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/WCLKE @@ -95,23 +59,10 @@ (1 5) routing lc_trk_g1_3 <X> wire_bram/ram/WCLKE (1 5) routing lc_trk_g2_2 <X> wire_bram/ram/WCLKE (1 5) routing lc_trk_g3_3 <X> wire_bram/ram/WCLKE -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 -(1 7) routing glb_netwk_4 <X> glb2local_0 (1 7) routing glb_netwk_5 <X> glb2local_0 -(1 7) routing glb_netwk_6 <X> glb2local_0 -(1 7) routing glb_netwk_7 <X> glb2local_0 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 -(1 9) routing glb_netwk_4 <X> glb2local_1 -(1 9) routing glb_netwk_5 <X> glb2local_1 (1 9) routing glb_netwk_6 <X> glb2local_1 (10 0) routing sp4_h_l_40 <X> sp4_h_r_1 (10 0) routing sp4_h_l_47 <X> sp4_h_r_1 @@ -181,6 +132,7 @@ (11 0) routing sp4_h_r_9 <X> sp4_v_b_2 (11 0) routing sp4_v_t_43 <X> sp4_v_b_2 (11 0) routing sp4_v_t_46 <X> sp4_v_b_2 +(11 1) routing sp4_h_l_39 <X> sp4_h_r_2 (11 1) routing sp4_h_l_43 <X> sp4_h_r_2 (11 1) routing sp4_v_b_2 <X> sp4_h_r_2 (11 1) routing sp4_v_b_8 <X> sp4_h_r_2 @@ -221,6 +173,7 @@ (11 4) routing sp4_v_t_39 <X> sp4_v_b_5 (11 4) routing sp4_v_t_44 <X> sp4_v_b_5 (11 5) routing sp4_h_l_40 <X> sp4_h_r_5 +(11 5) routing sp4_h_l_44 <X> sp4_h_r_5 (11 5) routing sp4_v_b_11 <X> sp4_h_r_5 (11 5) routing sp4_v_b_5 <X> sp4_h_r_5 (11 6) routing sp4_h_l_37 <X> sp4_v_t_40 @@ -348,6 +301,7 @@ (13 4) routing sp4_v_t_40 <X> sp4_v_b_5 (13 4) routing sp4_v_t_44 <X> sp4_v_b_5 (13 5) routing sp4_h_l_39 <X> sp4_h_r_5 +(13 5) routing sp4_h_l_44 <X> sp4_h_r_5 (13 5) routing sp4_v_b_11 <X> sp4_h_r_5 (13 5) routing sp4_v_t_37 <X> sp4_h_r_5 (13 6) routing sp4_h_r_11 <X> sp4_v_t_40 @@ -368,20 +322,16 @@ (13 9) routing sp4_v_t_38 <X> sp4_h_r_8 (14 0) routing bnr_op_0 <X> lc_trk_g0_0 (14 0) routing lft_op_0 <X> lc_trk_g0_0 -(14 0) routing sp12_h_r_0 <X> lc_trk_g0_0 (14 0) routing sp4_h_l_5 <X> lc_trk_g0_0 (14 0) routing sp4_h_r_8 <X> lc_trk_g0_0 (14 0) routing sp4_v_b_0 <X> lc_trk_g0_0 (14 0) routing sp4_v_b_8 <X> lc_trk_g0_0 (14 1) routing bnr_op_0 <X> lc_trk_g0_0 -(14 1) routing sp12_h_r_0 <X> lc_trk_g0_0 -(14 1) routing sp12_h_r_16 <X> lc_trk_g0_0 (14 1) routing sp4_h_l_5 <X> lc_trk_g0_0 (14 1) routing sp4_h_r_0 <X> lc_trk_g0_0 (14 1) routing sp4_r_v_b_35 <X> lc_trk_g0_0 (14 1) routing sp4_v_b_8 <X> lc_trk_g0_0 (14 10) routing bnl_op_4 <X> lc_trk_g2_4 -(14 10) routing rgt_op_4 <X> lc_trk_g2_4 (14 10) routing sp12_v_t_3 <X> lc_trk_g2_4 (14 10) routing sp4_h_r_36 <X> lc_trk_g2_4 (14 10) routing sp4_h_r_44 <X> lc_trk_g2_4 @@ -397,31 +347,21 @@ (14 11) routing tnl_op_4 <X> lc_trk_g2_4 (14 12) routing bnl_op_0 <X> lc_trk_g3_0 (14 12) routing rgt_op_0 <X> lc_trk_g3_0 -(14 12) routing sp12_v_b_0 <X> lc_trk_g3_0 -(14 12) routing sp4_h_l_21 <X> lc_trk_g3_0 (14 12) routing sp4_h_l_29 <X> lc_trk_g3_0 (14 12) routing sp4_v_t_13 <X> lc_trk_g3_0 (14 12) routing sp4_v_t_21 <X> lc_trk_g3_0 (14 13) routing bnl_op_0 <X> lc_trk_g3_0 -(14 13) routing sp12_v_b_0 <X> lc_trk_g3_0 (14 13) routing sp12_v_b_16 <X> lc_trk_g3_0 -(14 13) routing sp4_h_l_13 <X> lc_trk_g3_0 (14 13) routing sp4_h_l_29 <X> lc_trk_g3_0 (14 13) routing sp4_r_v_b_40 <X> lc_trk_g3_0 (14 13) routing sp4_v_t_21 <X> lc_trk_g3_0 (14 13) routing tnl_op_0 <X> lc_trk_g3_0 (14 14) routing bnl_op_4 <X> lc_trk_g3_4 (14 14) routing rgt_op_4 <X> lc_trk_g3_4 -(14 14) routing sp12_v_t_3 <X> lc_trk_g3_4 -(14 14) routing sp4_h_r_36 <X> lc_trk_g3_4 -(14 14) routing sp4_h_r_44 <X> lc_trk_g3_4 (14 14) routing sp4_v_b_28 <X> lc_trk_g3_4 (14 14) routing sp4_v_t_25 <X> lc_trk_g3_4 (14 15) routing bnl_op_4 <X> lc_trk_g3_4 -(14 15) routing sp12_v_t_19 <X> lc_trk_g3_4 -(14 15) routing sp12_v_t_3 <X> lc_trk_g3_4 (14 15) routing sp4_h_l_17 <X> lc_trk_g3_4 -(14 15) routing sp4_h_r_44 <X> lc_trk_g3_4 (14 15) routing sp4_r_v_b_44 <X> lc_trk_g3_4 (14 15) routing sp4_v_t_25 <X> lc_trk_g3_4 (14 15) routing tnl_op_4 <X> lc_trk_g3_4 @@ -434,14 +374,11 @@ (14 2) routing sp4_v_t_1 <X> lc_trk_g0_4 (14 3) routing bnr_op_4 <X> lc_trk_g0_4 (14 3) routing sp12_h_l_3 <X> lc_trk_g0_4 -(14 3) routing sp12_h_r_20 <X> lc_trk_g0_4 (14 3) routing sp4_h_r_20 <X> lc_trk_g0_4 (14 3) routing sp4_h_r_4 <X> lc_trk_g0_4 (14 3) routing sp4_r_v_b_28 <X> lc_trk_g0_4 (14 3) routing sp4_v_t_1 <X> lc_trk_g0_4 -(14 3) routing top_op_4 <X> lc_trk_g0_4 (14 4) routing bnr_op_0 <X> lc_trk_g1_0 -(14 4) routing lft_op_0 <X> lc_trk_g1_0 (14 4) routing sp12_h_r_0 <X> lc_trk_g1_0 (14 4) routing sp4_h_l_5 <X> lc_trk_g1_0 (14 4) routing sp4_h_r_8 <X> lc_trk_g1_0 @@ -449,7 +386,6 @@ (14 4) routing sp4_v_b_8 <X> lc_trk_g1_0 (14 5) routing bnr_op_0 <X> lc_trk_g1_0 (14 5) routing sp12_h_r_0 <X> lc_trk_g1_0 -(14 5) routing sp12_h_r_16 <X> lc_trk_g1_0 (14 5) routing sp4_h_l_5 <X> lc_trk_g1_0 (14 5) routing sp4_h_r_0 <X> lc_trk_g1_0 (14 5) routing sp4_r_v_b_24 <X> lc_trk_g1_0 @@ -463,34 +399,28 @@ (14 6) routing sp4_v_t_1 <X> lc_trk_g1_4 (14 7) routing bnr_op_4 <X> lc_trk_g1_4 (14 7) routing sp12_h_l_3 <X> lc_trk_g1_4 -(14 7) routing sp12_h_r_20 <X> lc_trk_g1_4 (14 7) routing sp4_h_r_20 <X> lc_trk_g1_4 (14 7) routing sp4_h_r_4 <X> lc_trk_g1_4 (14 7) routing sp4_r_v_b_28 <X> lc_trk_g1_4 (14 7) routing sp4_v_t_1 <X> lc_trk_g1_4 (14 8) routing bnl_op_0 <X> lc_trk_g2_0 (14 8) routing rgt_op_0 <X> lc_trk_g2_0 -(14 8) routing sp12_v_b_0 <X> lc_trk_g2_0 (14 8) routing sp4_h_l_21 <X> lc_trk_g2_0 (14 8) routing sp4_h_l_29 <X> lc_trk_g2_0 (14 8) routing sp4_v_t_13 <X> lc_trk_g2_0 (14 8) routing sp4_v_t_21 <X> lc_trk_g2_0 (14 9) routing bnl_op_0 <X> lc_trk_g2_0 -(14 9) routing sp12_v_b_0 <X> lc_trk_g2_0 (14 9) routing sp12_v_b_16 <X> lc_trk_g2_0 (14 9) routing sp4_h_l_13 <X> lc_trk_g2_0 (14 9) routing sp4_h_l_29 <X> lc_trk_g2_0 (14 9) routing sp4_r_v_b_32 <X> lc_trk_g2_0 (14 9) routing sp4_v_t_21 <X> lc_trk_g2_0 -(14 9) routing tnl_op_0 <X> lc_trk_g2_0 (15 0) routing lft_op_1 <X> lc_trk_g0_1 (15 0) routing sp12_h_r_1 <X> lc_trk_g0_1 -(15 0) routing sp4_h_r_1 <X> lc_trk_g0_1 (15 0) routing sp4_h_r_17 <X> lc_trk_g0_1 (15 0) routing sp4_h_r_9 <X> lc_trk_g0_1 (15 0) routing sp4_v_b_17 <X> lc_trk_g0_1 (15 1) routing lft_op_0 <X> lc_trk_g0_0 -(15 1) routing sp12_h_r_0 <X> lc_trk_g0_0 (15 1) routing sp4_h_l_5 <X> lc_trk_g0_0 (15 1) routing sp4_h_r_0 <X> lc_trk_g0_0 (15 1) routing sp4_h_r_8 <X> lc_trk_g0_0 @@ -498,12 +428,10 @@ (15 10) routing rgt_op_5 <X> lc_trk_g2_5 (15 10) routing sp12_v_b_5 <X> lc_trk_g2_5 (15 10) routing sp4_h_l_16 <X> lc_trk_g2_5 -(15 10) routing sp4_h_r_37 <X> lc_trk_g2_5 (15 10) routing sp4_h_r_45 <X> lc_trk_g2_5 (15 10) routing sp4_v_b_45 <X> lc_trk_g2_5 (15 10) routing tnl_op_5 <X> lc_trk_g2_5 (15 10) routing tnr_op_5 <X> lc_trk_g2_5 -(15 11) routing rgt_op_4 <X> lc_trk_g2_4 (15 11) routing sp12_v_t_3 <X> lc_trk_g2_4 (15 11) routing sp4_h_l_17 <X> lc_trk_g2_4 (15 11) routing sp4_h_r_36 <X> lc_trk_g2_4 @@ -511,18 +439,13 @@ (15 11) routing sp4_v_t_33 <X> lc_trk_g2_4 (15 11) routing tnl_op_4 <X> lc_trk_g2_4 (15 11) routing tnr_op_4 <X> lc_trk_g2_4 -(15 12) routing rgt_op_1 <X> lc_trk_g3_1 (15 12) routing sp12_v_b_1 <X> lc_trk_g3_1 -(15 12) routing sp4_h_l_20 <X> lc_trk_g3_1 (15 12) routing sp4_h_l_28 <X> lc_trk_g3_1 (15 12) routing sp4_h_r_25 <X> lc_trk_g3_1 (15 12) routing sp4_v_b_41 <X> lc_trk_g3_1 (15 12) routing tnl_op_1 <X> lc_trk_g3_1 (15 12) routing tnr_op_1 <X> lc_trk_g3_1 (15 13) routing rgt_op_0 <X> lc_trk_g3_0 -(15 13) routing sp12_v_b_0 <X> lc_trk_g3_0 -(15 13) routing sp4_h_l_13 <X> lc_trk_g3_0 -(15 13) routing sp4_h_l_21 <X> lc_trk_g3_0 (15 13) routing sp4_h_l_29 <X> lc_trk_g3_0 (15 13) routing sp4_v_b_40 <X> lc_trk_g3_0 (15 13) routing tnl_op_0 <X> lc_trk_g3_0 @@ -531,15 +454,11 @@ (15 14) routing sp12_v_b_5 <X> lc_trk_g3_5 (15 14) routing sp4_h_l_16 <X> lc_trk_g3_5 (15 14) routing sp4_h_r_37 <X> lc_trk_g3_5 -(15 14) routing sp4_h_r_45 <X> lc_trk_g3_5 (15 14) routing sp4_v_b_45 <X> lc_trk_g3_5 (15 14) routing tnl_op_5 <X> lc_trk_g3_5 (15 14) routing tnr_op_5 <X> lc_trk_g3_5 (15 15) routing rgt_op_4 <X> lc_trk_g3_4 -(15 15) routing sp12_v_t_3 <X> lc_trk_g3_4 (15 15) routing sp4_h_l_17 <X> lc_trk_g3_4 -(15 15) routing sp4_h_r_36 <X> lc_trk_g3_4 -(15 15) routing sp4_h_r_44 <X> lc_trk_g3_4 (15 15) routing sp4_v_t_33 <X> lc_trk_g3_4 (15 15) routing tnl_op_4 <X> lc_trk_g3_4 (15 15) routing tnr_op_4 <X> lc_trk_g3_4 @@ -555,14 +474,12 @@ (15 3) routing sp4_h_r_20 <X> lc_trk_g0_4 (15 3) routing sp4_h_r_4 <X> lc_trk_g0_4 (15 3) routing sp4_v_b_20 <X> lc_trk_g0_4 -(15 3) routing top_op_4 <X> lc_trk_g0_4 (15 4) routing lft_op_1 <X> lc_trk_g1_1 (15 4) routing sp12_h_r_1 <X> lc_trk_g1_1 (15 4) routing sp4_h_r_1 <X> lc_trk_g1_1 (15 4) routing sp4_h_r_17 <X> lc_trk_g1_1 (15 4) routing sp4_h_r_9 <X> lc_trk_g1_1 (15 4) routing sp4_v_b_17 <X> lc_trk_g1_1 -(15 5) routing lft_op_0 <X> lc_trk_g1_0 (15 5) routing sp12_h_r_0 <X> lc_trk_g1_0 (15 5) routing sp4_h_l_5 <X> lc_trk_g1_0 (15 5) routing sp4_h_r_0 <X> lc_trk_g1_0 @@ -580,7 +497,6 @@ (15 7) routing sp4_h_r_20 <X> lc_trk_g1_4 (15 7) routing sp4_h_r_4 <X> lc_trk_g1_4 (15 7) routing sp4_v_b_20 <X> lc_trk_g1_4 -(15 8) routing rgt_op_1 <X> lc_trk_g2_1 (15 8) routing sp12_v_b_1 <X> lc_trk_g2_1 (15 8) routing sp4_h_l_20 <X> lc_trk_g2_1 (15 8) routing sp4_h_l_28 <X> lc_trk_g2_1 @@ -589,22 +505,17 @@ (15 8) routing tnl_op_1 <X> lc_trk_g2_1 (15 8) routing tnr_op_1 <X> lc_trk_g2_1 (15 9) routing rgt_op_0 <X> lc_trk_g2_0 -(15 9) routing sp12_v_b_0 <X> lc_trk_g2_0 (15 9) routing sp4_h_l_13 <X> lc_trk_g2_0 (15 9) routing sp4_h_l_21 <X> lc_trk_g2_0 (15 9) routing sp4_h_l_29 <X> lc_trk_g2_0 (15 9) routing sp4_v_b_40 <X> lc_trk_g2_0 -(15 9) routing tnl_op_0 <X> lc_trk_g2_0 (15 9) routing tnr_op_0 <X> lc_trk_g2_0 (16 0) routing sp12_h_l_6 <X> lc_trk_g0_1 -(16 0) routing sp12_h_r_17 <X> lc_trk_g0_1 -(16 0) routing sp4_h_r_1 <X> lc_trk_g0_1 (16 0) routing sp4_h_r_17 <X> lc_trk_g0_1 (16 0) routing sp4_h_r_9 <X> lc_trk_g0_1 (16 0) routing sp4_v_b_1 <X> lc_trk_g0_1 (16 0) routing sp4_v_b_17 <X> lc_trk_g0_1 (16 0) routing sp4_v_b_9 <X> lc_trk_g0_1 -(16 1) routing sp12_h_r_16 <X> lc_trk_g0_0 (16 1) routing sp12_h_r_8 <X> lc_trk_g0_0 (16 1) routing sp4_h_l_5 <X> lc_trk_g0_0 (16 1) routing sp4_h_r_0 <X> lc_trk_g0_0 @@ -615,7 +526,6 @@ (16 10) routing sp12_v_b_21 <X> lc_trk_g2_5 (16 10) routing sp12_v_t_10 <X> lc_trk_g2_5 (16 10) routing sp4_h_l_16 <X> lc_trk_g2_5 -(16 10) routing sp4_h_r_37 <X> lc_trk_g2_5 (16 10) routing sp4_h_r_45 <X> lc_trk_g2_5 (16 10) routing sp4_v_b_29 <X> lc_trk_g2_5 (16 10) routing sp4_v_b_37 <X> lc_trk_g2_5 @@ -630,7 +540,6 @@ (16 11) routing sp4_v_t_33 <X> lc_trk_g2_4 (16 12) routing sp12_v_b_17 <X> lc_trk_g3_1 (16 12) routing sp12_v_b_9 <X> lc_trk_g3_1 -(16 12) routing sp4_h_l_20 <X> lc_trk_g3_1 (16 12) routing sp4_h_l_28 <X> lc_trk_g3_1 (16 12) routing sp4_h_r_25 <X> lc_trk_g3_1 (16 12) routing sp4_v_b_25 <X> lc_trk_g3_1 @@ -638,8 +547,6 @@ (16 12) routing sp4_v_b_41 <X> lc_trk_g3_1 (16 13) routing sp12_v_b_16 <X> lc_trk_g3_0 (16 13) routing sp12_v_t_7 <X> lc_trk_g3_0 -(16 13) routing sp4_h_l_13 <X> lc_trk_g3_0 -(16 13) routing sp4_h_l_21 <X> lc_trk_g3_0 (16 13) routing sp4_h_l_29 <X> lc_trk_g3_0 (16 13) routing sp4_v_b_40 <X> lc_trk_g3_0 (16 13) routing sp4_v_t_13 <X> lc_trk_g3_0 @@ -648,19 +555,13 @@ (16 14) routing sp12_v_t_10 <X> lc_trk_g3_5 (16 14) routing sp4_h_l_16 <X> lc_trk_g3_5 (16 14) routing sp4_h_r_37 <X> lc_trk_g3_5 -(16 14) routing sp4_h_r_45 <X> lc_trk_g3_5 (16 14) routing sp4_v_b_29 <X> lc_trk_g3_5 (16 14) routing sp4_v_b_37 <X> lc_trk_g3_5 (16 14) routing sp4_v_b_45 <X> lc_trk_g3_5 -(16 15) routing sp12_v_b_12 <X> lc_trk_g3_4 -(16 15) routing sp12_v_t_19 <X> lc_trk_g3_4 (16 15) routing sp4_h_l_17 <X> lc_trk_g3_4 -(16 15) routing sp4_h_r_36 <X> lc_trk_g3_4 -(16 15) routing sp4_h_r_44 <X> lc_trk_g3_4 (16 15) routing sp4_v_b_28 <X> lc_trk_g3_4 (16 15) routing sp4_v_t_25 <X> lc_trk_g3_4 (16 15) routing sp4_v_t_33 <X> lc_trk_g3_4 -(16 2) routing sp12_h_l_18 <X> lc_trk_g0_5 (16 2) routing sp12_h_r_13 <X> lc_trk_g0_5 (16 2) routing sp4_h_l_8 <X> lc_trk_g0_5 (16 2) routing sp4_h_r_13 <X> lc_trk_g0_5 @@ -668,8 +569,6 @@ (16 2) routing sp4_v_b_13 <X> lc_trk_g0_5 (16 2) routing sp4_v_b_5 <X> lc_trk_g0_5 (16 2) routing sp4_v_t_8 <X> lc_trk_g0_5 -(16 3) routing sp12_h_r_12 <X> lc_trk_g0_4 -(16 3) routing sp12_h_r_20 <X> lc_trk_g0_4 (16 3) routing sp4_h_r_12 <X> lc_trk_g0_4 (16 3) routing sp4_h_r_20 <X> lc_trk_g0_4 (16 3) routing sp4_h_r_4 <X> lc_trk_g0_4 @@ -684,7 +583,6 @@ (16 4) routing sp4_v_b_1 <X> lc_trk_g1_1 (16 4) routing sp4_v_b_17 <X> lc_trk_g1_1 (16 4) routing sp4_v_b_9 <X> lc_trk_g1_1 -(16 5) routing sp12_h_r_16 <X> lc_trk_g1_0 (16 5) routing sp12_h_r_8 <X> lc_trk_g1_0 (16 5) routing sp4_h_l_5 <X> lc_trk_g1_0 (16 5) routing sp4_h_r_0 <X> lc_trk_g1_0 @@ -692,16 +590,12 @@ (16 5) routing sp4_v_b_0 <X> lc_trk_g1_0 (16 5) routing sp4_v_b_16 <X> lc_trk_g1_0 (16 5) routing sp4_v_b_8 <X> lc_trk_g1_0 -(16 6) routing sp12_h_l_18 <X> lc_trk_g1_5 -(16 6) routing sp12_h_r_13 <X> lc_trk_g1_5 (16 6) routing sp4_h_l_8 <X> lc_trk_g1_5 (16 6) routing sp4_h_r_13 <X> lc_trk_g1_5 (16 6) routing sp4_h_r_5 <X> lc_trk_g1_5 (16 6) routing sp4_v_b_13 <X> lc_trk_g1_5 (16 6) routing sp4_v_b_5 <X> lc_trk_g1_5 (16 6) routing sp4_v_t_8 <X> lc_trk_g1_5 -(16 7) routing sp12_h_r_12 <X> lc_trk_g1_4 -(16 7) routing sp12_h_r_20 <X> lc_trk_g1_4 (16 7) routing sp4_h_r_12 <X> lc_trk_g1_4 (16 7) routing sp4_h_r_20 <X> lc_trk_g1_4 (16 7) routing sp4_h_r_4 <X> lc_trk_g1_4 @@ -728,8 +622,6 @@ (17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_6 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_17 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 @@ -739,8 +631,6 @@ (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 @@ -756,7 +646,6 @@ (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 @@ -766,7 +655,6 @@ (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 (17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_19 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4 @@ -781,11 +669,9 @@ (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 (17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_17 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 @@ -797,11 +683,8 @@ (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 (17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_29 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 @@ -817,7 +700,6 @@ (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 @@ -827,12 +709,7 @@ (17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 (17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_19 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 @@ -843,7 +720,6 @@ (17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_8 lc_trk_g0_5 @@ -857,8 +733,6 @@ (17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 @@ -866,7 +740,6 @@ (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => top_op_4 lc_trk_g0_4 (17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_6 lc_trk_g1_1 @@ -881,9 +754,7 @@ (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 @@ -895,8 +766,6 @@ (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 (17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 @@ -909,8 +778,6 @@ (17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 @@ -920,7 +787,6 @@ (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 (17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_17 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 @@ -936,7 +802,6 @@ (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 (17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0 @@ -947,7 +812,6 @@ (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 (18 0) routing bnr_op_1 <X> lc_trk_g0_1 (18 0) routing lft_op_1 <X> lc_trk_g0_1 @@ -958,15 +822,12 @@ (18 0) routing sp4_v_b_9 <X> lc_trk_g0_1 (18 1) routing bnr_op_1 <X> lc_trk_g0_1 (18 1) routing sp12_h_r_1 <X> lc_trk_g0_1 -(18 1) routing sp12_h_r_17 <X> lc_trk_g0_1 -(18 1) routing sp4_h_r_1 <X> lc_trk_g0_1 (18 1) routing sp4_h_r_17 <X> lc_trk_g0_1 (18 1) routing sp4_r_v_b_34 <X> lc_trk_g0_1 (18 1) routing sp4_v_b_9 <X> lc_trk_g0_1 (18 10) routing bnl_op_5 <X> lc_trk_g2_5 (18 10) routing rgt_op_5 <X> lc_trk_g2_5 (18 10) routing sp12_v_b_5 <X> lc_trk_g2_5 -(18 10) routing sp4_h_r_37 <X> lc_trk_g2_5 (18 10) routing sp4_h_r_45 <X> lc_trk_g2_5 (18 10) routing sp4_v_b_29 <X> lc_trk_g2_5 (18 10) routing sp4_v_b_37 <X> lc_trk_g2_5 @@ -979,9 +840,7 @@ (18 11) routing sp4_v_b_37 <X> lc_trk_g2_5 (18 11) routing tnl_op_5 <X> lc_trk_g2_5 (18 12) routing bnl_op_1 <X> lc_trk_g3_1 -(18 12) routing rgt_op_1 <X> lc_trk_g3_1 (18 12) routing sp12_v_b_1 <X> lc_trk_g3_1 -(18 12) routing sp4_h_l_20 <X> lc_trk_g3_1 (18 12) routing sp4_h_l_28 <X> lc_trk_g3_1 (18 12) routing sp4_v_b_25 <X> lc_trk_g3_1 (18 12) routing sp4_v_b_33 <X> lc_trk_g3_1 @@ -997,14 +856,12 @@ (18 14) routing rgt_op_5 <X> lc_trk_g3_5 (18 14) routing sp12_v_b_5 <X> lc_trk_g3_5 (18 14) routing sp4_h_r_37 <X> lc_trk_g3_5 -(18 14) routing sp4_h_r_45 <X> lc_trk_g3_5 (18 14) routing sp4_v_b_29 <X> lc_trk_g3_5 (18 14) routing sp4_v_b_37 <X> lc_trk_g3_5 (18 15) routing bnl_op_5 <X> lc_trk_g3_5 (18 15) routing sp12_v_b_21 <X> lc_trk_g3_5 (18 15) routing sp12_v_b_5 <X> lc_trk_g3_5 (18 15) routing sp4_h_l_16 <X> lc_trk_g3_5 -(18 15) routing sp4_h_r_45 <X> lc_trk_g3_5 (18 15) routing sp4_r_v_b_45 <X> lc_trk_g3_5 (18 15) routing sp4_v_b_37 <X> lc_trk_g3_5 (18 15) routing tnl_op_5 <X> lc_trk_g3_5 @@ -1016,7 +873,6 @@ (18 2) routing sp4_v_b_13 <X> lc_trk_g0_5 (18 2) routing sp4_v_b_5 <X> lc_trk_g0_5 (18 3) routing bnr_op_5 <X> lc_trk_g0_5 -(18 3) routing sp12_h_l_18 <X> lc_trk_g0_5 (18 3) routing sp12_h_r_5 <X> lc_trk_g0_5 (18 3) routing sp4_h_l_8 <X> lc_trk_g0_5 (18 3) routing sp4_h_r_5 <X> lc_trk_g0_5 @@ -1044,14 +900,12 @@ (18 6) routing sp4_v_b_13 <X> lc_trk_g1_5 (18 6) routing sp4_v_b_5 <X> lc_trk_g1_5 (18 7) routing bnr_op_5 <X> lc_trk_g1_5 -(18 7) routing sp12_h_l_18 <X> lc_trk_g1_5 (18 7) routing sp12_h_r_5 <X> lc_trk_g1_5 (18 7) routing sp4_h_l_8 <X> lc_trk_g1_5 (18 7) routing sp4_h_r_5 <X> lc_trk_g1_5 (18 7) routing sp4_r_v_b_29 <X> lc_trk_g1_5 (18 7) routing sp4_v_b_13 <X> lc_trk_g1_5 (18 8) routing bnl_op_1 <X> lc_trk_g2_1 -(18 8) routing rgt_op_1 <X> lc_trk_g2_1 (18 8) routing sp12_v_b_1 <X> lc_trk_g2_1 (18 8) routing sp4_h_l_20 <X> lc_trk_g2_1 (18 8) routing sp4_h_l_28 <X> lc_trk_g2_1 @@ -1085,13 +939,10 @@ (2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_r_18 sp4_h_l_8 (2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_r_22 (2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_l_21 sp4_h_l_10 -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/WCLK @@ -1105,7 +956,6 @@ (2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_l_13 sp4_h_r_19 (2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_r_20 (21 0) routing bnr_op_3 <X> lc_trk_g0_3 -(21 0) routing lft_op_3 <X> lc_trk_g0_3 (21 0) routing sp12_h_l_0 <X> lc_trk_g0_3 (21 0) routing sp4_h_r_11 <X> lc_trk_g0_3 (21 0) routing sp4_h_r_19 <X> lc_trk_g0_3 @@ -1113,15 +963,11 @@ (21 0) routing sp4_v_b_3 <X> lc_trk_g0_3 (21 1) routing bnr_op_3 <X> lc_trk_g0_3 (21 1) routing sp12_h_l_0 <X> lc_trk_g0_3 -(21 1) routing sp12_h_l_16 <X> lc_trk_g0_3 (21 1) routing sp4_h_r_19 <X> lc_trk_g0_3 -(21 1) routing sp4_h_r_3 <X> lc_trk_g0_3 (21 1) routing sp4_r_v_b_32 <X> lc_trk_g0_3 (21 1) routing sp4_v_b_11 <X> lc_trk_g0_3 (21 10) routing bnl_op_7 <X> lc_trk_g2_7 -(21 10) routing rgt_op_7 <X> lc_trk_g2_7 (21 10) routing sp12_v_b_7 <X> lc_trk_g2_7 -(21 10) routing sp4_h_l_26 <X> lc_trk_g2_7 (21 10) routing sp4_h_r_47 <X> lc_trk_g2_7 (21 10) routing sp4_v_t_18 <X> lc_trk_g2_7 (21 10) routing sp4_v_t_26 <X> lc_trk_g2_7 @@ -1132,7 +978,6 @@ (21 11) routing sp4_h_r_47 <X> lc_trk_g2_7 (21 11) routing sp4_r_v_b_39 <X> lc_trk_g2_7 (21 11) routing sp4_v_t_26 <X> lc_trk_g2_7 -(21 11) routing tnl_op_7 <X> lc_trk_g2_7 (21 12) routing bnl_op_3 <X> lc_trk_g3_3 (21 12) routing rgt_op_3 <X> lc_trk_g3_3 (21 12) routing sp12_v_t_0 <X> lc_trk_g3_3 @@ -1151,28 +996,21 @@ (21 14) routing bnl_op_7 <X> lc_trk_g3_7 (21 14) routing rgt_op_7 <X> lc_trk_g3_7 (21 14) routing sp12_v_b_7 <X> lc_trk_g3_7 -(21 14) routing sp4_h_l_26 <X> lc_trk_g3_7 -(21 14) routing sp4_h_r_47 <X> lc_trk_g3_7 (21 14) routing sp4_v_t_18 <X> lc_trk_g3_7 (21 14) routing sp4_v_t_26 <X> lc_trk_g3_7 (21 15) routing bnl_op_7 <X> lc_trk_g3_7 (21 15) routing sp12_v_b_23 <X> lc_trk_g3_7 (21 15) routing sp12_v_b_7 <X> lc_trk_g3_7 (21 15) routing sp4_h_l_18 <X> lc_trk_g3_7 -(21 15) routing sp4_h_r_47 <X> lc_trk_g3_7 (21 15) routing sp4_r_v_b_47 <X> lc_trk_g3_7 (21 15) routing sp4_v_t_26 <X> lc_trk_g3_7 -(21 15) routing tnl_op_7 <X> lc_trk_g3_7 (21 2) routing bnr_op_7 <X> lc_trk_g0_7 (21 2) routing lft_op_7 <X> lc_trk_g0_7 -(21 2) routing sp12_h_l_4 <X> lc_trk_g0_7 (21 2) routing sp4_h_l_10 <X> lc_trk_g0_7 (21 2) routing sp4_h_l_2 <X> lc_trk_g0_7 (21 2) routing sp4_v_b_7 <X> lc_trk_g0_7 (21 2) routing sp4_v_t_2 <X> lc_trk_g0_7 (21 3) routing bnr_op_7 <X> lc_trk_g0_7 -(21 3) routing sp12_h_l_4 <X> lc_trk_g0_7 -(21 3) routing sp12_h_r_23 <X> lc_trk_g0_7 (21 3) routing sp4_h_l_10 <X> lc_trk_g0_7 (21 3) routing sp4_h_r_7 <X> lc_trk_g0_7 (21 3) routing sp4_r_v_b_31 <X> lc_trk_g0_7 @@ -1186,27 +1024,22 @@ (21 4) routing sp4_v_b_3 <X> lc_trk_g1_3 (21 5) routing bnr_op_3 <X> lc_trk_g1_3 (21 5) routing sp12_h_l_0 <X> lc_trk_g1_3 -(21 5) routing sp12_h_l_16 <X> lc_trk_g1_3 (21 5) routing sp4_h_r_19 <X> lc_trk_g1_3 (21 5) routing sp4_h_r_3 <X> lc_trk_g1_3 (21 5) routing sp4_r_v_b_27 <X> lc_trk_g1_3 (21 5) routing sp4_v_b_11 <X> lc_trk_g1_3 (21 6) routing bnr_op_7 <X> lc_trk_g1_7 (21 6) routing lft_op_7 <X> lc_trk_g1_7 -(21 6) routing sp12_h_l_4 <X> lc_trk_g1_7 (21 6) routing sp4_h_l_10 <X> lc_trk_g1_7 (21 6) routing sp4_h_l_2 <X> lc_trk_g1_7 (21 6) routing sp4_v_b_7 <X> lc_trk_g1_7 (21 6) routing sp4_v_t_2 <X> lc_trk_g1_7 (21 7) routing bnr_op_7 <X> lc_trk_g1_7 -(21 7) routing sp12_h_l_4 <X> lc_trk_g1_7 -(21 7) routing sp12_h_r_23 <X> lc_trk_g1_7 (21 7) routing sp4_h_l_10 <X> lc_trk_g1_7 (21 7) routing sp4_h_r_7 <X> lc_trk_g1_7 (21 7) routing sp4_r_v_b_31 <X> lc_trk_g1_7 (21 7) routing sp4_v_t_2 <X> lc_trk_g1_7 (21 8) routing bnl_op_3 <X> lc_trk_g2_3 -(21 8) routing rgt_op_3 <X> lc_trk_g2_3 (21 8) routing sp12_v_t_0 <X> lc_trk_g2_3 (21 8) routing sp4_h_l_30 <X> lc_trk_g2_3 (21 8) routing sp4_h_r_35 <X> lc_trk_g2_3 @@ -1216,18 +1049,13 @@ (21 9) routing sp12_v_t_0 <X> lc_trk_g2_3 (21 9) routing sp12_v_t_16 <X> lc_trk_g2_3 (21 9) routing sp4_h_l_30 <X> lc_trk_g2_3 -(21 9) routing sp4_h_r_27 <X> lc_trk_g2_3 (21 9) routing sp4_r_v_b_35 <X> lc_trk_g2_3 (21 9) routing sp4_v_t_22 <X> lc_trk_g2_3 (21 9) routing tnl_op_3 <X> lc_trk_g2_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 @@ -1235,8 +1063,6 @@ (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 (22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_10 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_18 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 @@ -1246,21 +1072,17 @@ (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => top_op_2 lc_trk_g0_2 (22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 (22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 @@ -1313,14 +1135,11 @@ (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 (22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 @@ -1328,7 +1147,6 @@ (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 @@ -1340,9 +1158,6 @@ (22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 @@ -1353,9 +1168,7 @@ (22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_13 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_21 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 @@ -1363,12 +1176,9 @@ (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => top_op_6 lc_trk_g0_6 (22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 @@ -1380,22 +1190,16 @@ (22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_10 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_18 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => top_op_2 lc_trk_g1_2 (22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_23 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 @@ -1406,25 +1210,19 @@ (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 (22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_13 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_21 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_22 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => top_op_6 lc_trk_g1_6 (22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_16 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_30 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 @@ -1446,18 +1244,12 @@ (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 -(23 0) routing sp12_h_l_16 <X> lc_trk_g0_3 -(23 0) routing sp12_h_r_11 <X> lc_trk_g0_3 (23 0) routing sp4_h_r_11 <X> lc_trk_g0_3 (23 0) routing sp4_h_r_19 <X> lc_trk_g0_3 -(23 0) routing sp4_h_r_3 <X> lc_trk_g0_3 (23 0) routing sp4_v_b_11 <X> lc_trk_g0_3 (23 0) routing sp4_v_b_19 <X> lc_trk_g0_3 (23 0) routing sp4_v_b_3 <X> lc_trk_g0_3 -(23 1) routing sp12_h_r_10 <X> lc_trk_g0_2 -(23 1) routing sp12_h_r_18 <X> lc_trk_g0_2 (23 1) routing sp4_h_l_7 <X> lc_trk_g0_2 (23 1) routing sp4_h_r_10 <X> lc_trk_g0_2 (23 1) routing sp4_h_r_2 <X> lc_trk_g0_2 @@ -1467,7 +1259,6 @@ (23 10) routing sp12_v_b_23 <X> lc_trk_g2_7 (23 10) routing sp12_v_t_12 <X> lc_trk_g2_7 (23 10) routing sp4_h_l_18 <X> lc_trk_g2_7 -(23 10) routing sp4_h_l_26 <X> lc_trk_g2_7 (23 10) routing sp4_h_r_47 <X> lc_trk_g2_7 (23 10) routing sp4_v_b_47 <X> lc_trk_g2_7 (23 10) routing sp4_v_t_18 <X> lc_trk_g2_7 @@ -1499,28 +1290,22 @@ (23 14) routing sp12_v_b_23 <X> lc_trk_g3_7 (23 14) routing sp12_v_t_12 <X> lc_trk_g3_7 (23 14) routing sp4_h_l_18 <X> lc_trk_g3_7 -(23 14) routing sp4_h_l_26 <X> lc_trk_g3_7 -(23 14) routing sp4_h_r_47 <X> lc_trk_g3_7 (23 14) routing sp4_v_b_47 <X> lc_trk_g3_7 (23 14) routing sp4_v_t_18 <X> lc_trk_g3_7 (23 14) routing sp4_v_t_26 <X> lc_trk_g3_7 (23 15) routing sp12_v_b_14 <X> lc_trk_g3_6 (23 15) routing sp12_v_t_21 <X> lc_trk_g3_6 (23 15) routing sp4_h_l_27 <X> lc_trk_g3_6 -(23 15) routing sp4_h_r_30 <X> lc_trk_g3_6 (23 15) routing sp4_h_r_46 <X> lc_trk_g3_6 (23 15) routing sp4_v_b_30 <X> lc_trk_g3_6 (23 15) routing sp4_v_b_38 <X> lc_trk_g3_6 (23 15) routing sp4_v_b_46 <X> lc_trk_g3_6 -(23 2) routing sp12_h_l_12 <X> lc_trk_g0_7 -(23 2) routing sp12_h_r_23 <X> lc_trk_g0_7 (23 2) routing sp4_h_l_10 <X> lc_trk_g0_7 (23 2) routing sp4_h_l_2 <X> lc_trk_g0_7 (23 2) routing sp4_h_r_7 <X> lc_trk_g0_7 (23 2) routing sp4_v_b_7 <X> lc_trk_g0_7 (23 2) routing sp4_v_t_10 <X> lc_trk_g0_7 (23 2) routing sp4_v_t_2 <X> lc_trk_g0_7 -(23 3) routing sp12_h_l_13 <X> lc_trk_g0_6 (23 3) routing sp12_h_l_21 <X> lc_trk_g0_6 (23 3) routing sp4_h_l_3 <X> lc_trk_g0_6 (23 3) routing sp4_h_r_22 <X> lc_trk_g0_6 @@ -1528,8 +1313,6 @@ (23 3) routing sp4_v_b_14 <X> lc_trk_g0_6 (23 3) routing sp4_v_b_22 <X> lc_trk_g0_6 (23 3) routing sp4_v_b_6 <X> lc_trk_g0_6 -(23 4) routing sp12_h_l_16 <X> lc_trk_g1_3 -(23 4) routing sp12_h_r_11 <X> lc_trk_g1_3 (23 4) routing sp4_h_r_11 <X> lc_trk_g1_3 (23 4) routing sp4_h_r_19 <X> lc_trk_g1_3 (23 4) routing sp4_h_r_3 <X> lc_trk_g1_3 @@ -1537,33 +1320,25 @@ (23 4) routing sp4_v_b_19 <X> lc_trk_g1_3 (23 4) routing sp4_v_b_3 <X> lc_trk_g1_3 (23 5) routing sp12_h_r_10 <X> lc_trk_g1_2 -(23 5) routing sp12_h_r_18 <X> lc_trk_g1_2 (23 5) routing sp4_h_l_7 <X> lc_trk_g1_2 (23 5) routing sp4_h_r_10 <X> lc_trk_g1_2 -(23 5) routing sp4_h_r_2 <X> lc_trk_g1_2 (23 5) routing sp4_v_b_10 <X> lc_trk_g1_2 (23 5) routing sp4_v_b_2 <X> lc_trk_g1_2 (23 5) routing sp4_v_t_7 <X> lc_trk_g1_2 -(23 6) routing sp12_h_l_12 <X> lc_trk_g1_7 -(23 6) routing sp12_h_r_23 <X> lc_trk_g1_7 (23 6) routing sp4_h_l_10 <X> lc_trk_g1_7 (23 6) routing sp4_h_l_2 <X> lc_trk_g1_7 (23 6) routing sp4_h_r_7 <X> lc_trk_g1_7 (23 6) routing sp4_v_b_7 <X> lc_trk_g1_7 (23 6) routing sp4_v_t_10 <X> lc_trk_g1_7 (23 6) routing sp4_v_t_2 <X> lc_trk_g1_7 -(23 7) routing sp12_h_l_13 <X> lc_trk_g1_6 -(23 7) routing sp12_h_l_21 <X> lc_trk_g1_6 (23 7) routing sp4_h_l_3 <X> lc_trk_g1_6 (23 7) routing sp4_h_r_22 <X> lc_trk_g1_6 -(23 7) routing sp4_h_r_6 <X> lc_trk_g1_6 (23 7) routing sp4_v_b_14 <X> lc_trk_g1_6 (23 7) routing sp4_v_b_22 <X> lc_trk_g1_6 (23 7) routing sp4_v_b_6 <X> lc_trk_g1_6 (23 8) routing sp12_v_b_11 <X> lc_trk_g2_3 (23 8) routing sp12_v_t_16 <X> lc_trk_g2_3 (23 8) routing sp4_h_l_30 <X> lc_trk_g2_3 -(23 8) routing sp4_h_r_27 <X> lc_trk_g2_3 (23 8) routing sp4_h_r_35 <X> lc_trk_g2_3 (23 8) routing sp4_v_t_14 <X> lc_trk_g2_3 (23 8) routing sp4_v_t_22 <X> lc_trk_g2_3 @@ -1576,11 +1351,9 @@ (23 9) routing sp4_v_b_26 <X> lc_trk_g2_2 (23 9) routing sp4_v_t_23 <X> lc_trk_g2_2 (23 9) routing sp4_v_t_31 <X> lc_trk_g2_2 -(24 0) routing lft_op_3 <X> lc_trk_g0_3 (24 0) routing sp12_h_l_0 <X> lc_trk_g0_3 (24 0) routing sp4_h_r_11 <X> lc_trk_g0_3 (24 0) routing sp4_h_r_19 <X> lc_trk_g0_3 -(24 0) routing sp4_h_r_3 <X> lc_trk_g0_3 (24 0) routing sp4_v_b_19 <X> lc_trk_g0_3 (24 1) routing lft_op_2 <X> lc_trk_g0_2 (24 1) routing sp12_h_r_2 <X> lc_trk_g0_2 @@ -1588,14 +1361,10 @@ (24 1) routing sp4_h_r_10 <X> lc_trk_g0_2 (24 1) routing sp4_h_r_2 <X> lc_trk_g0_2 (24 1) routing sp4_v_t_7 <X> lc_trk_g0_2 -(24 1) routing top_op_2 <X> lc_trk_g0_2 -(24 10) routing rgt_op_7 <X> lc_trk_g2_7 (24 10) routing sp12_v_b_7 <X> lc_trk_g2_7 (24 10) routing sp4_h_l_18 <X> lc_trk_g2_7 -(24 10) routing sp4_h_l_26 <X> lc_trk_g2_7 (24 10) routing sp4_h_r_47 <X> lc_trk_g2_7 (24 10) routing sp4_v_b_47 <X> lc_trk_g2_7 -(24 10) routing tnl_op_7 <X> lc_trk_g2_7 (24 10) routing tnr_op_7 <X> lc_trk_g2_7 (24 11) routing rgt_op_6 <X> lc_trk_g2_6 (24 11) routing sp12_v_b_6 <X> lc_trk_g2_6 @@ -1624,32 +1393,25 @@ (24 14) routing rgt_op_7 <X> lc_trk_g3_7 (24 14) routing sp12_v_b_7 <X> lc_trk_g3_7 (24 14) routing sp4_h_l_18 <X> lc_trk_g3_7 -(24 14) routing sp4_h_l_26 <X> lc_trk_g3_7 -(24 14) routing sp4_h_r_47 <X> lc_trk_g3_7 (24 14) routing sp4_v_b_47 <X> lc_trk_g3_7 -(24 14) routing tnl_op_7 <X> lc_trk_g3_7 (24 14) routing tnr_op_7 <X> lc_trk_g3_7 (24 15) routing rgt_op_6 <X> lc_trk_g3_6 (24 15) routing sp12_v_b_6 <X> lc_trk_g3_6 (24 15) routing sp4_h_l_27 <X> lc_trk_g3_6 -(24 15) routing sp4_h_r_30 <X> lc_trk_g3_6 (24 15) routing sp4_h_r_46 <X> lc_trk_g3_6 (24 15) routing sp4_v_b_46 <X> lc_trk_g3_6 (24 15) routing tnl_op_6 <X> lc_trk_g3_6 (24 15) routing tnr_op_6 <X> lc_trk_g3_6 (24 2) routing lft_op_7 <X> lc_trk_g0_7 -(24 2) routing sp12_h_l_4 <X> lc_trk_g0_7 (24 2) routing sp4_h_l_10 <X> lc_trk_g0_7 (24 2) routing sp4_h_l_2 <X> lc_trk_g0_7 (24 2) routing sp4_h_r_7 <X> lc_trk_g0_7 (24 2) routing sp4_v_t_10 <X> lc_trk_g0_7 (24 3) routing lft_op_6 <X> lc_trk_g0_6 -(24 3) routing sp12_h_l_5 <X> lc_trk_g0_6 (24 3) routing sp4_h_l_3 <X> lc_trk_g0_6 (24 3) routing sp4_h_r_22 <X> lc_trk_g0_6 (24 3) routing sp4_h_r_6 <X> lc_trk_g0_6 (24 3) routing sp4_v_b_22 <X> lc_trk_g0_6 -(24 3) routing top_op_6 <X> lc_trk_g0_6 (24 4) routing lft_op_3 <X> lc_trk_g1_3 (24 4) routing sp12_h_l_0 <X> lc_trk_g1_3 (24 4) routing sp4_h_r_11 <X> lc_trk_g1_3 @@ -1660,11 +1422,8 @@ (24 5) routing sp12_h_r_2 <X> lc_trk_g1_2 (24 5) routing sp4_h_l_7 <X> lc_trk_g1_2 (24 5) routing sp4_h_r_10 <X> lc_trk_g1_2 -(24 5) routing sp4_h_r_2 <X> lc_trk_g1_2 (24 5) routing sp4_v_t_7 <X> lc_trk_g1_2 -(24 5) routing top_op_2 <X> lc_trk_g1_2 (24 6) routing lft_op_7 <X> lc_trk_g1_7 -(24 6) routing sp12_h_l_4 <X> lc_trk_g1_7 (24 6) routing sp4_h_l_10 <X> lc_trk_g1_7 (24 6) routing sp4_h_l_2 <X> lc_trk_g1_7 (24 6) routing sp4_h_r_7 <X> lc_trk_g1_7 @@ -1673,13 +1432,9 @@ (24 7) routing sp12_h_l_5 <X> lc_trk_g1_6 (24 7) routing sp4_h_l_3 <X> lc_trk_g1_6 (24 7) routing sp4_h_r_22 <X> lc_trk_g1_6 -(24 7) routing sp4_h_r_6 <X> lc_trk_g1_6 (24 7) routing sp4_v_b_22 <X> lc_trk_g1_6 -(24 7) routing top_op_6 <X> lc_trk_g1_6 -(24 8) routing rgt_op_3 <X> lc_trk_g2_3 (24 8) routing sp12_v_t_0 <X> lc_trk_g2_3 (24 8) routing sp4_h_l_30 <X> lc_trk_g2_3 -(24 8) routing sp4_h_r_27 <X> lc_trk_g2_3 (24 8) routing sp4_h_r_35 <X> lc_trk_g2_3 (24 8) routing sp4_v_t_30 <X> lc_trk_g2_3 (24 8) routing tnl_op_3 <X> lc_trk_g2_3 @@ -1690,7 +1445,6 @@ (24 9) routing sp4_h_r_34 <X> lc_trk_g2_2 (24 9) routing sp4_h_r_42 <X> lc_trk_g2_2 (24 9) routing sp4_v_t_31 <X> lc_trk_g2_2 -(24 9) routing tnl_op_2 <X> lc_trk_g2_2 (24 9) routing tnr_op_2 <X> lc_trk_g2_2 (25 0) routing bnr_op_2 <X> lc_trk_g0_2 (25 0) routing lft_op_2 <X> lc_trk_g0_2 @@ -1700,13 +1454,11 @@ (25 0) routing sp4_v_b_10 <X> lc_trk_g0_2 (25 0) routing sp4_v_b_2 <X> lc_trk_g0_2 (25 1) routing bnr_op_2 <X> lc_trk_g0_2 -(25 1) routing sp12_h_r_18 <X> lc_trk_g0_2 (25 1) routing sp12_h_r_2 <X> lc_trk_g0_2 (25 1) routing sp4_h_l_7 <X> lc_trk_g0_2 (25 1) routing sp4_h_r_2 <X> lc_trk_g0_2 (25 1) routing sp4_r_v_b_33 <X> lc_trk_g0_2 (25 1) routing sp4_v_b_10 <X> lc_trk_g0_2 -(25 1) routing top_op_2 <X> lc_trk_g0_2 (25 10) routing bnl_op_6 <X> lc_trk_g2_6 (25 10) routing rgt_op_6 <X> lc_trk_g2_6 (25 10) routing sp12_v_b_6 <X> lc_trk_g2_6 @@ -1747,26 +1499,22 @@ (25 15) routing bnl_op_6 <X> lc_trk_g3_6 (25 15) routing sp12_v_b_6 <X> lc_trk_g3_6 (25 15) routing sp12_v_t_21 <X> lc_trk_g3_6 -(25 15) routing sp4_h_r_30 <X> lc_trk_g3_6 (25 15) routing sp4_h_r_46 <X> lc_trk_g3_6 (25 15) routing sp4_r_v_b_46 <X> lc_trk_g3_6 (25 15) routing sp4_v_b_38 <X> lc_trk_g3_6 (25 15) routing tnl_op_6 <X> lc_trk_g3_6 (25 2) routing bnr_op_6 <X> lc_trk_g0_6 (25 2) routing lft_op_6 <X> lc_trk_g0_6 -(25 2) routing sp12_h_l_5 <X> lc_trk_g0_6 (25 2) routing sp4_h_l_3 <X> lc_trk_g0_6 (25 2) routing sp4_h_r_22 <X> lc_trk_g0_6 (25 2) routing sp4_v_b_14 <X> lc_trk_g0_6 (25 2) routing sp4_v_b_6 <X> lc_trk_g0_6 (25 3) routing bnr_op_6 <X> lc_trk_g0_6 (25 3) routing sp12_h_l_21 <X> lc_trk_g0_6 -(25 3) routing sp12_h_l_5 <X> lc_trk_g0_6 (25 3) routing sp4_h_r_22 <X> lc_trk_g0_6 (25 3) routing sp4_h_r_6 <X> lc_trk_g0_6 (25 3) routing sp4_r_v_b_30 <X> lc_trk_g0_6 (25 3) routing sp4_v_b_14 <X> lc_trk_g0_6 -(25 3) routing top_op_6 <X> lc_trk_g0_6 (25 4) routing bnr_op_2 <X> lc_trk_g1_2 (25 4) routing lft_op_2 <X> lc_trk_g1_2 (25 4) routing sp12_h_r_2 <X> lc_trk_g1_2 @@ -1775,13 +1523,10 @@ (25 4) routing sp4_v_b_10 <X> lc_trk_g1_2 (25 4) routing sp4_v_b_2 <X> lc_trk_g1_2 (25 5) routing bnr_op_2 <X> lc_trk_g1_2 -(25 5) routing sp12_h_r_18 <X> lc_trk_g1_2 (25 5) routing sp12_h_r_2 <X> lc_trk_g1_2 (25 5) routing sp4_h_l_7 <X> lc_trk_g1_2 -(25 5) routing sp4_h_r_2 <X> lc_trk_g1_2 (25 5) routing sp4_r_v_b_26 <X> lc_trk_g1_2 (25 5) routing sp4_v_b_10 <X> lc_trk_g1_2 -(25 5) routing top_op_2 <X> lc_trk_g1_2 (25 6) routing bnr_op_6 <X> lc_trk_g1_6 (25 6) routing lft_op_6 <X> lc_trk_g1_6 (25 6) routing sp12_h_l_5 <X> lc_trk_g1_6 @@ -1790,13 +1535,10 @@ (25 6) routing sp4_v_b_14 <X> lc_trk_g1_6 (25 6) routing sp4_v_b_6 <X> lc_trk_g1_6 (25 7) routing bnr_op_6 <X> lc_trk_g1_6 -(25 7) routing sp12_h_l_21 <X> lc_trk_g1_6 (25 7) routing sp12_h_l_5 <X> lc_trk_g1_6 (25 7) routing sp4_h_r_22 <X> lc_trk_g1_6 -(25 7) routing sp4_h_r_6 <X> lc_trk_g1_6 (25 7) routing sp4_r_v_b_30 <X> lc_trk_g1_6 (25 7) routing sp4_v_b_14 <X> lc_trk_g1_6 -(25 7) routing top_op_6 <X> lc_trk_g1_6 (25 8) routing bnl_op_2 <X> lc_trk_g2_2 (25 8) routing rgt_op_2 <X> lc_trk_g2_2 (25 8) routing sp12_v_b_2 <X> lc_trk_g2_2 @@ -1811,8 +1553,6 @@ (25 9) routing sp4_h_r_42 <X> lc_trk_g2_2 (25 9) routing sp4_r_v_b_34 <X> lc_trk_g2_2 (25 9) routing sp4_v_t_23 <X> lc_trk_g2_2 -(25 9) routing tnl_op_2 <X> lc_trk_g2_2 -(26 0) routing lc_trk_g0_4 <X> input0_0 (26 0) routing lc_trk_g0_6 <X> input0_0 (26 0) routing lc_trk_g1_5 <X> input0_0 (26 0) routing lc_trk_g1_7 <X> input0_0 @@ -1947,7 +1687,6 @@ (27 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_7 -(27 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7 (27 1) routing lc_trk_g1_1 <X> input0_0 (27 1) routing lc_trk_g1_3 <X> input0_0 (27 1) routing lc_trk_g1_5 <X> input0_0 @@ -1959,7 +1698,6 @@ (27 10) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_2 -(27 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_2 @@ -2005,9 +1743,7 @@ (27 15) routing lc_trk_g3_4 <X> input0_7 (27 15) routing lc_trk_g3_6 <X> input0_7 (27 2) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_6 -(27 2) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_6 -(27 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_6 @@ -2038,7 +1774,6 @@ (27 5) routing lc_trk_g3_7 <X> input0_2 (27 6) routing lc_trk_g1_1 <X> wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_4 -(27 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_4 @@ -2053,7 +1788,6 @@ (27 7) routing lc_trk_g3_4 <X> input0_3 (27 7) routing lc_trk_g3_6 <X> input0_3 (27 8) routing lc_trk_g1_0 <X> wire_bram/ram/WDATA_3 -(27 8) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_3 @@ -2075,7 +1809,6 @@ (28 0) routing lc_trk_g3_0 <X> wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_7 -(28 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7 (28 1) routing lc_trk_g2_0 <X> input0_0 (28 1) routing lc_trk_g2_2 <X> input0_0 (28 1) routing lc_trk_g2_4 <X> input0_0 @@ -2132,7 +1865,6 @@ (28 15) routing lc_trk_g3_2 <X> input0_7 (28 15) routing lc_trk_g3_4 <X> input0_7 (28 15) routing lc_trk_g3_6 <X> input0_7 -(28 2) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_6 @@ -2166,7 +1898,6 @@ (28 5) routing lc_trk_g3_7 <X> input0_2 (28 6) routing lc_trk_g2_0 <X> wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_4 -(28 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g3_1 <X> wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_4 @@ -2211,10 +1942,8 @@ (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_7 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0 @@ -2229,13 +1958,11 @@ (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_2 @@ -2324,15 +2051,10 @@ (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_6 @@ -2390,15 +2112,12 @@ (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_4 @@ -2423,9 +2142,7 @@ (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_3 @@ -2491,7 +2208,6 @@ (30 0) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_7 -(30 0) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_7 @@ -2499,19 +2215,15 @@ (30 1) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_7 -(30 1) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_7 (30 10) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_2 -(30 10) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_2 -(30 11) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_2 -(30 11) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_2 @@ -2548,18 +2260,14 @@ (30 15) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_0 -(30 2) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_6 -(30 2) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g0_2 <X> wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_6 -(30 3) routing lc_trk_g1_3 <X> wire_bram/ram/WDATA_6 -(30 3) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g2_2 <X> wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_6 @@ -2580,11 +2288,8 @@ (30 5) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_5 -(30 6) routing lc_trk_g0_4 <X> wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g0_6 <X> wire_bram/ram/WDATA_4 -(30 6) routing lc_trk_g1_5 <X> wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g1_7 <X> wire_bram/ram/WDATA_4 -(30 6) routing lc_trk_g2_4 <X> wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g2_6 <X> wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g3_5 <X> wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_4 @@ -2597,7 +2302,6 @@ (30 7) routing lc_trk_g3_3 <X> wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g3_7 <X> wire_bram/ram/WDATA_4 (30 8) routing lc_trk_g0_5 <X> wire_bram/ram/WDATA_3 -(30 8) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g1_4 <X> wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g2_5 <X> wire_bram/ram/WDATA_3 @@ -2605,63 +2309,40 @@ (30 8) routing lc_trk_g3_4 <X> wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g0_3 <X> wire_bram/ram/WDATA_3 -(30 9) routing lc_trk_g0_7 <X> wire_bram/ram/WDATA_3 -(30 9) routing lc_trk_g1_2 <X> wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g1_6 <X> wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g2_3 <X> wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g2_7 <X> wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g3_2 <X> wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g3_6 <X> wire_bram/ram/WDATA_3 -(31 0) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_7 (31 0) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_7 (31 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_7 -(31 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_7 (31 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_7 (31 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_7 (31 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_7 (31 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_7 (31 1) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_7 (31 1) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_7 (31 1) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_7 (31 1) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_7 (31 1) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_7 -(31 10) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_2 (31 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_2 (31 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_2 (31 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_2 (31 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_2 (31 11) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_2 (31 11) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_2 (31 11) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_2 (31 11) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_2 (31 11) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_2 (31 11) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_2 -(31 12) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_1 -(31 12) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_1 (31 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_1 (31 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_1 (31 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_1 -(31 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_1 (31 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_1 -(31 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_1 (31 13) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_1 (31 13) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_1 (31 13) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1 (31 14) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_0 -(31 14) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_0 (31 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_0 (31 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_0 (31 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_0 @@ -2669,17 +2350,12 @@ (31 14) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_0 (31 14) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_0 (31 15) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_0 -(31 15) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_0 -(31 15) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_0 (31 15) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_0 (31 15) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_0 (31 15) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_0 (31 15) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_0 (31 15) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_0 -(31 2) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_6 (31 2) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_6 -(31 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_6 -(31 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_6 (31 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_6 (31 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_6 (31 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_6 @@ -2687,37 +2363,23 @@ (31 3) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_6 (31 3) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_6 (31 3) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_6 -(31 3) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_6 -(31 3) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_6 (31 3) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_6 (31 3) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_6 (31 3) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_6 (31 4) routing lc_trk_g0_5 <X> wire_bram/ram/MASK_5 (31 4) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_5 (31 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_5 -(31 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_5 -(31 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_5 (31 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_5 -(31 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_5 (31 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5 (31 5) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_5 (31 5) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_5 (31 5) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_5 (31 5) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_5 (31 5) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_5 (31 5) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5 -(31 6) routing lc_trk_g0_4 <X> wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_4 (31 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_4 (31 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_4 (31 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g0_2 <X> wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g0_6 <X> wire_bram/ram/MASK_4 (31 7) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_4 (31 7) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_4 (31 7) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_4 @@ -2732,75 +2394,45 @@ (31 8) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_3 (31 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_3 (31 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3 -(31 9) routing lc_trk_g0_3 <X> wire_bram/ram/MASK_3 (31 9) routing lc_trk_g0_7 <X> wire_bram/ram/MASK_3 -(31 9) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_3 (31 9) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_3 (31 9) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_3 (31 9) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_3 (31 9) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_3 (31 9) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_7 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_2 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_1 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_4 input2_6 @@ -2819,12 +2451,9 @@ (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_7 input2_6 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_0 @@ -2849,14 +2478,8 @@ (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_6 @@ -2866,38 +2489,23 @@ (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_5 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_4 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_3 @@ -2908,17 +2516,12 @@ (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_3 -(33 0) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_7 -(33 0) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_7 (33 0) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_7 (33 0) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_7 -(33 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_7 -(33 10) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_2 (33 10) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_2 -(33 10) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_2 (33 10) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_2 (33 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_2 (33 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_2 @@ -2928,18 +2531,13 @@ (33 11) routing lc_trk_g2_3 <X> input2_5 (33 11) routing lc_trk_g2_5 <X> input2_5 (33 11) routing lc_trk_g2_7 <X> input2_5 -(33 11) routing lc_trk_g3_0 <X> input2_5 (33 11) routing lc_trk_g3_2 <X> input2_5 (33 11) routing lc_trk_g3_4 <X> input2_5 (33 11) routing lc_trk_g3_6 <X> input2_5 -(33 12) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_1 (33 12) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_1 (33 12) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_1 -(33 12) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_1 (33 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_1 -(33 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_1 (33 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_1 -(33 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1 (33 13) routing lc_trk_g2_0 <X> input2_6 (33 13) routing lc_trk_g2_2 <X> input2_6 (33 13) routing lc_trk_g2_4 <X> input2_6 @@ -2948,7 +2546,6 @@ (33 13) routing lc_trk_g3_3 <X> input2_6 (33 13) routing lc_trk_g3_5 <X> input2_6 (33 13) routing lc_trk_g3_7 <X> input2_6 -(33 14) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_0 @@ -2964,8 +2561,6 @@ (33 15) routing lc_trk_g3_2 <X> input2_7 (33 15) routing lc_trk_g3_4 <X> input2_7 (33 15) routing lc_trk_g3_6 <X> input2_7 -(33 2) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_6 -(33 2) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_6 (33 2) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_6 (33 2) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_6 (33 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_6 @@ -2973,20 +2568,14 @@ (33 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_6 (33 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_6 (33 4) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_5 -(33 4) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_5 -(33 4) routing lc_trk_g2_5 <X> wire_bram/ram/MASK_5 (33 4) routing lc_trk_g2_7 <X> wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_5 -(33 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5 -(33 6) routing lc_trk_g2_0 <X> wire_bram/ram/MASK_4 (33 6) routing lc_trk_g2_2 <X> wire_bram/ram/MASK_4 -(33 6) routing lc_trk_g2_4 <X> wire_bram/ram/MASK_4 (33 6) routing lc_trk_g2_6 <X> wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_4 -(33 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_4 (33 8) routing lc_trk_g2_1 <X> wire_bram/ram/MASK_3 (33 8) routing lc_trk_g2_3 <X> wire_bram/ram/MASK_3 @@ -2997,37 +2586,24 @@ (33 8) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_3 (33 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3 (34 0) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_7 (34 0) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_7 -(34 10) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_2 (34 10) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_2 -(34 10) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_2 (34 10) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_2 -(34 11) routing lc_trk_g1_0 <X> input2_5 -(34 11) routing lc_trk_g1_2 <X> input2_5 -(34 11) routing lc_trk_g1_4 <X> input2_5 -(34 11) routing lc_trk_g1_6 <X> input2_5 -(34 11) routing lc_trk_g3_0 <X> input2_5 (34 11) routing lc_trk_g3_2 <X> input2_5 (34 11) routing lc_trk_g3_4 <X> input2_5 (34 11) routing lc_trk_g3_6 <X> input2_5 -(34 12) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_1 (34 12) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_1 -(34 12) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_1 (34 12) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_1 -(34 12) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_1 (34 13) routing lc_trk_g1_1 <X> input2_6 (34 13) routing lc_trk_g1_3 <X> input2_6 (34 13) routing lc_trk_g1_5 <X> input2_6 @@ -3037,7 +2613,6 @@ (34 13) routing lc_trk_g3_5 <X> input2_6 (34 13) routing lc_trk_g3_7 <X> input2_6 (34 14) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_0 -(34 14) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_0 (34 14) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_0 (34 14) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_0 (34 14) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_0 @@ -3052,32 +2627,22 @@ (34 15) routing lc_trk_g3_2 <X> input2_7 (34 15) routing lc_trk_g3_4 <X> input2_7 (34 15) routing lc_trk_g3_6 <X> input2_7 -(34 2) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_6 (34 2) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_6 -(34 2) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_6 -(34 2) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_6 -(34 4) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_5 (34 4) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_5 (34 4) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_5 -(34 4) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_2 <X> wire_bram/ram/MASK_5 -(34 4) routing lc_trk_g3_4 <X> wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_5 -(34 6) routing lc_trk_g1_1 <X> wire_bram/ram/MASK_4 (34 6) routing lc_trk_g1_3 <X> wire_bram/ram/MASK_4 -(34 6) routing lc_trk_g1_5 <X> wire_bram/ram/MASK_4 (34 6) routing lc_trk_g1_7 <X> wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_1 <X> wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_3 <X> wire_bram/ram/MASK_4 -(34 6) routing lc_trk_g3_5 <X> wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_7 <X> wire_bram/ram/MASK_4 (34 8) routing lc_trk_g1_0 <X> wire_bram/ram/MASK_3 -(34 8) routing lc_trk_g1_2 <X> wire_bram/ram/MASK_3 (34 8) routing lc_trk_g1_4 <X> wire_bram/ram/MASK_3 (34 8) routing lc_trk_g1_6 <X> wire_bram/ram/MASK_3 (34 8) routing lc_trk_g3_0 <X> wire_bram/ram/MASK_3 @@ -3086,16 +2651,11 @@ (34 8) routing lc_trk_g3_6 <X> wire_bram/ram/MASK_3 (35 10) routing lc_trk_g0_5 <X> input2_5 (35 10) routing lc_trk_g0_7 <X> input2_5 -(35 10) routing lc_trk_g1_4 <X> input2_5 -(35 10) routing lc_trk_g1_6 <X> input2_5 (35 10) routing lc_trk_g2_5 <X> input2_5 (35 10) routing lc_trk_g2_7 <X> input2_5 (35 10) routing lc_trk_g3_4 <X> input2_5 (35 10) routing lc_trk_g3_6 <X> input2_5 -(35 11) routing lc_trk_g0_3 <X> input2_5 (35 11) routing lc_trk_g0_7 <X> input2_5 -(35 11) routing lc_trk_g1_2 <X> input2_5 -(35 11) routing lc_trk_g1_6 <X> input2_5 (35 11) routing lc_trk_g2_3 <X> input2_5 (35 11) routing lc_trk_g2_7 <X> input2_5 (35 11) routing lc_trk_g3_2 <X> input2_5 @@ -3133,21 +2693,16 @@ (35 15) routing lc_trk_g3_2 <X> input2_7 (35 15) routing lc_trk_g3_6 <X> input2_7 (36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_7 sp4_h_l_21 -(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_7 sp4_h_r_0 -(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_2 sp4_h_r_42 (36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_2 sp4_h_r_10 (36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_1 sp4_h_r_44 (36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_1 sp4_h_r_12 -(36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_0 sp4_h_r_46 (36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_0 sp4_h_l_3 (36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_6 sp4_h_r_34 -(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_6 sp4_h_r_2 (36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_5 sp4_h_r_36 (36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_5 sp4_h_r_4 (36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_4 sp4_h_l_27 (36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_4 sp4_h_r_6 (36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_3 sp4_h_l_29 -(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_3 sp4_h_r_8 (37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_7 sp12_h_r_8 (37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_7 sp4_h_l_5 (37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_2 sp12_h_r_2 @@ -3166,7 +2721,6 @@ (37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_3 sp4_h_l_13 (38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_7 sp4_v_t_21 (38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_7 sp4_v_b_0 -(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_2 sp4_v_b_26 (38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_2 sp12_h_r_18 (38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_1 sp4_v_b_28 (38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_1 sp12_h_r_20 @@ -3260,7 +2814,6 @@ (4 9) routing sp4_h_l_47 <X> sp4_h_r_6 (4 9) routing sp4_v_b_0 <X> sp4_h_r_6 (4 9) routing sp4_v_t_36 <X> sp4_h_r_6 -(40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_17 (40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_7 sp12_v_b_16 (40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_27 (40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_2 sp12_v_t_9 @@ -3268,7 +2821,6 @@ (40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_1 sp12_v_b_12 (40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_31 (40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_0 sp12_v_b_14 -(40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_19 (40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_6 sp12_v_t_17 (40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_21 (40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_5 sp12_v_t_19 @@ -3277,7 +2829,6 @@ (40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_25 (40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_3 sp12_v_t_7 (41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_33 -(41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_1 (41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_43 (41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_11 (41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_45 @@ -3433,20 +2984,16 @@ (7 4) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_5 -(7 4) Cascade buffer Enable bit: MEMT_LC03_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_5 -(7 4) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC06_inmux02_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC07_inmux02_bram_cbit_5 (7 5) Cascade bit: MEMT_LC00_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC01_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC02_inmux00_bram_cbit_4 -(7 5) Cascade bit: MEMT_LC03_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC04_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC05_inmux00_bram_cbit_4 -(7 5) Cascade bit: MEMT_LC06_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC06_inmux02_bram_cbit_4 (7 5) Cascade bit: MEMT_LC07_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC07_inmux02_bram_cbit_4 diff --git a/icefuzz/database.py b/icefuzz/database.py index f8f3ccf..a0caca6 100644 --- a/icefuzz/database.py +++ b/icefuzz/database.py @@ -28,7 +28,7 @@ def read_database(filename, tile_type): line = re.sub(r"^Ram config bit:", "RamConfig", line) line = re.sub(r"^PLL config bit:", "PLL", line) line = re.sub(r"^Icegate Enable bit:", "Icegate", line) - line = re.sub(r"^MAC16 functional bit:", "DspConfig", line) + line = re.sub(r"^MAC16 functional bit:", "IpConfig", line) line = re.sub(r"^Hard IP config bit:", "IpConfig", line) line = line.split() @@ -57,14 +57,14 @@ def read_database(filename, tile_type): elif line[0] == "ColBufCtrl": line[1] = re.sub(r"B?IO(LEFT|RIGHT)_", "IO_", line[1]) line[1] = re.sub(r"IO_half_column_clock_enable_", "glb_netwk_", line[1]) - line[1] = re.sub(r"(LH|MEM[BT])_colbuf_cntl_", "glb_netwk_", line[1]) + line[1] = re.sub(r"(LH|MEM[BT]|MULT\d|IPCON)_colbuf_cntl_", "glb_netwk_", line[1]) if m.group(1) == "7": line[1] = re.sub(r"glb_netwk_", "8k_glb_netwk_", line[1]) elif m.group(1) in ["1", "2"]: line[1] = re.sub(r"glb_netwk_", "1k_glb_netwk_", line[1]) raw_db.append((bit, (line[0], line[1]))) elif line[0] == "Cascade": - match = re.match("(MULT\d|LH)_LC0(\d)_inmux02_5", line[1]) + match = re.match("LH_LC0(\d)_inmux02_5", line[1]) if match: raw_db.append((bit, ("buffer", "wire_logic_cluster/lc_%d/lout" % (int(match.group(1))-1), "input_2_%s" % match.group(1)))) else: @@ -90,11 +90,10 @@ def read_database(filename, tile_type): raw_db.append((bit, (line[0],))) elif line[0] == "Carry_In_Mux": continue - elif line[0] == "DspConfig": - line[1] = re.sub(r"MULT\d_bram_cbit_", "CBIT_", line[1]) elif line[0] == "IpConfig": line[1] = re.sub(r"MULT\d_bram_cbit_", "CBIT_", line[1]) #not a typo, sometimes IP config bits are in DSP tiles and use a MULT prefix... - line[1] = re.sub(r"IPCON_bram_cbit_", "CBIT_", line[1]) + line[1] = re.sub(r"IPCON_bram_cbit_", "CBIT_", line[1]) + raw_db.append((bit, (line[0], line[1]))) else: print("unsupported statement: %s: %s" % (bit, line)) assert False @@ -157,11 +156,11 @@ for device_class in ["5k", "8k"]: with open("database_ramt_%s.txt" % (device_class, ), "w") as f: for entry in read_database("bitdata_ramt_%s.txt" % (device_class, ), "ramt_" + device_class): print("\t".join(entry), file=f) -if device_class == "5k": - for dsp_idx in range(4): - with open("database_dsp%d_5k.txt" % (dsp_idx, ), "w") as f: - for entry in read_database("bitdata_dsp%d_5k.txt" % (dsp_idx, ), "dsp%d_5" % (dsp_idx, )): - print("\t".join(entry), file=f) - with open("database_ipcon.txt", "w") as f: - for entry in read_database("bitdata_ipcon.txt", "ipcon"): - print("\t".join(entry), file=f)
\ No newline at end of file + +for dsp_idx in range(4): + with open("database_dsp%d_5k.txt" % (dsp_idx, ), "w") as f: + for entry in read_database("bitdata_dsp%d_5k.txt" % (dsp_idx, ), "dsp%d_5" % (dsp_idx, )): + print("\t".join(entry), file=f) +with open("database_ipcon_5k.txt", "w") as f: + for entry in read_database("bitdata_ipcon_5k.txt", "ipcon"): + print("\t".join(entry), file=f)
\ No newline at end of file diff --git a/icefuzz/fuzzconfig.py b/icefuzz/fuzzconfig.py index a5c1e2c..a50cce5 100644 --- a/icefuzz/fuzzconfig.py +++ b/icefuzz/fuzzconfig.py @@ -7,6 +7,7 @@ device_class = os.getenv("ICEDEVICE") if device_class == "8k": num_ramb40 = 32 num_iobanks = 4 + num_dsp = 0 pins=""" A1 A2 A5 A6 A7 A9 A10 A11 A15 A16 @@ -32,6 +33,7 @@ if device_class == "8k": elif device_class == "384": num_ramb40 = 0 num_iobanks = 3 + num_dsp = 0 pins = """ A1 A2 A3 A4 A5 A6 A7 @@ -48,6 +50,7 @@ elif device_class == "384": elif device_class == "1k": num_ramb40 = 16 num_iobanks = 4 + num_dsp = 0 pins = """ 1 2 3 4 7 8 9 10 11 12 19 22 23 24 25 26 28 29 31 32 33 34 @@ -60,7 +63,8 @@ elif device_class == "1k": elif device_class == "5k": num_ramb40 = 30 num_iobanks = 2 - + num_dsp = 8 + num_spram256ka = 4 #TODO(tannewt): Add 39, 40, 41 to this list. It causes placement failures for some reason. # Also add 14 15 16 17 which are constrained to SPI. #TODO(daveshah1): Add back I3C IO 23 which cause placement failures when assigned to @@ -73,7 +77,7 @@ elif device_class == "5k": #TODO(tannewt): Add 39, 40, 41 to this list. It causes placement failures for some reason. gpins = "20 35 37 44".split() - + led_pins = "39 40 41".split() def output_makefile(working_dir, fuzzname): with open(working_dir + "/Makefile", "w") as f: print("all: %s" % " ".join(["%s_%02d.bin" % (fuzzname, i) for i in range(num)]), file=f) diff --git a/icefuzz/glbcheck.py b/icefuzz/glbcheck.py index 49008ca..04a2580 100644 --- a/icefuzz/glbcheck.py +++ b/icefuzz/glbcheck.py @@ -6,26 +6,32 @@ asc_bits = set() glb_bits = set() # parsing .asc file -with open(argv[1]) as f: - current_tile = None - current_line = None - for line in f: - if line.startswith("."): - if line.find("_tile ") >= 0: - f = line.split() - current_tile = "%02d.%02d" % (int(f[1]), int(f[2])) - current_line = 0 - else: - current_tile = None - current_line = None - continue - - if current_tile is not None: - for i in range(len(line)): - if line[i] == '1': - asc_bits.add("%s.%02d.%02d" % (current_tile, current_line, i)) - current_line += 1 +try: + with open(argv[1]) as f: + current_tile = None + current_line = None + for line in f: + if line.startswith("."): + if line.find("_tile ") >= 0: + f = line.split() + current_tile = "%02d.%02d" % (int(f[1]), int(f[2])) + current_line = 0 + else: + current_tile = None + current_line = None + continue + if current_tile is not None: + for i in range(len(line)): + if line[i] == '1': + asc_bits.add("%s.%02d.%02d" % (current_tile, current_line, i)) + current_line += 1 +except FileNotFoundError: + print("ASC file doesn't exist, skipping glbcheck!.") + # The asc file may not exist for innocent reasons, such as + # the icecube router failing. So exit with code 0 to keep + # the fuzz Makefile happy + exit(0) # parsing .glb file with open(argv[2]) as f: current_tile = None diff --git a/icefuzz/make_dsp.py b/icefuzz/make_dsp.py new file mode 100755 index 0000000..e97f5c0 --- /dev/null +++ b/icefuzz/make_dsp.py @@ -0,0 +1,206 @@ +#!/usr/bin/env python3 + +from fuzzconfig import * +import numpy as np +import os + +device_class = os.getenv("ICEDEVICE") + +assert device_class == "5k" + +working_dir = "work_%s_dsp" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) + +def randbin(n): + return "".join([np.random.choice(["0", "1"]) for i in range(n)]) + +#Only certain combinations are allowed in icecube, list them here +#This is not a complete set, but enough to cover all bits except cbit13, which +#is not set in any allowed config (?) +allowed_configs = ["0010000010000001001110110", "1110000010000001001110110", "0010000010000001000000000", "1110000010000001000000000", + "0000000011000001111110110", "1100000011000001111110110", "0000000011000001110000110", "0010000101000010111111111", + "0000001001100100111111111", "0001001001100100111111111", "0001101001100100111111111", "0001111000101100000000000"] + +coverage = set() +for c in allowed_configs: + for i in range(25): + if c[i] == "1": + coverage.add(i) + +assert len(coverage) >= 24 + +#print(len(coverage)) +#print(coverage) + +for idx in range(num): + with open(working_dir + "/dsp_%02d.v" % idx, "w") as f: + glbs = ["glb[%d]" % i for i in range(np.random.randint(8)+1)] + # TODO: ce should be on this list, but causes routing failures + glbs_choice = ["clk", "a", "b", "c", "d,", "ah", "bh", "ch", "dh", "irt", "irb", "ort", "orb", "olt", "olb", "ast", "asb", "oht", "ohb", "sei"] + print(""" + module top ( + input [%d:0] glb_pins, + input [%d:0] in_pins, + output [15:0] out_pins + ); + wire [%d:0] glb, glb_pins; + SB_GB gbufs [%d:0] ( + .USER_SIGNAL_TO_GLOBAL_BUFFER(glb_pins), + .GLOBAL_BUFFER_OUTPUT(glb) + ); + """ % (len(glbs)-1, len(pins) - len(glbs) - 16 - 1, len(glbs)-1, len(glbs)-1), file=f) + bits = ["in_pins[%d]" % i for i in range(100)] + bits = list(np.random.permutation(bits)) + for i in range(num_dsp): + tmp = list(np.random.permutation(bits)) + bits_c = [tmp.pop() for k in range(16)] + bits_a = [tmp.pop() for k in range(16)] + bits_b = [tmp.pop() for k in range(16)] + bits_d = [tmp.pop() for k in range(16)] + bit_ce = tmp.pop() + bit_clk = tmp.pop() + bit_ahold = tmp.pop() + bit_bhold = tmp.pop() + bit_chold = tmp.pop() + bit_dhold = tmp.pop() + bit_irsttop = tmp.pop() + bit_irstbot = tmp.pop() + bit_orsttop = tmp.pop() + bit_orstbot = tmp.pop() + bit_oloadtop = tmp.pop() + bit_oloadbot = tmp.pop() + bit_addsubtop = tmp.pop() + bit_addsubbot = tmp.pop() + bit_oholdtop = tmp.pop() + bit_oholdbot = tmp.pop() + + aci_opts = ["1'b0"] + if i > 0 and i % 4 != 0: + aci_opts.append("out_%d[33]" % (i-1)); + sei_opts = ["1'b0"] + if i > 0 and i % 4 != 0: + sei_opts.append("out_%d[34]" % (i - 1)); + + bit_ci = tmp.pop() + bit_accumci = np.random.choice(aci_opts) + bit_signextin = np.random.choice(sei_opts) + + if len(glbs) != 0: + s = np.random.choice(glbs_choice) + glbs_choice.remove(s) + if s == "clk": bit_clk = glbs.pop() + if s == "a": bits_a[np.random.randint(len(bits_a))] = glbs.pop() + if s == "b": bits_b[np.random.randint(len(bits_b))] = glbs.pop() + if s == "c": bits_c[np.random.randint(len(bits_c))] = glbs.pop() + if s == "d": bits_d[np.random.randint(len(bits_d))] = glbs.pop() + if s == "ah": bit_ahold = glbs.pop() + if s == "bh": bit_bhold = glbs.pop() + if s == "ch": bit_chold = glbs.pop() + if s == "dh": bit_dhold = glbs.pop() + if s == "irt": bit_irsttop = glbs.pop() + if s == "irb": bit_irstbot = glbs.pop() + if s == "ort": bit_orsttop = glbs.pop() + if s == "orb": bit_orstbot = glbs.pop() + if s == "olt": bit_oloadtop = glbs.pop() + if s == "olb": bit_oloadbot = glbs.pop() + if s == "ast": bit_addsubtop = glbs.pop() + if s == "asb": bit_addsubbot = glbs.pop() + if s == "oht": bit_oholdtop = glbs.pop() + if s == "ohb": bit_oholdbot = glbs.pop() + if s == "ci": bit_ci = glbs.pop() + + + bits_a = "{%s}" % ", ".join(bits_a) + bits_b = "{%s}" % ", ".join(bits_b) + bits_c = "{%s}" % ", ".join(bits_c) + bits_d = "{%s}" % ", ".join(bits_d) + + negclk = randbin(1) + params = np.random.choice(allowed_configs) + params = params[::-1] + print(""" + wire [34:0] out_%d; + SB_MAC16 #( + .NEG_TRIGGER(1'b%s), + .C_REG(1'b%s), + .A_REG(1'b%s), + .B_REG(1'b%s), + .D_REG(1'b%s), + .TOP_8x8_MULT_REG(1'b%s), + .BOT_8x8_MULT_REG(1'b%s), + .PIPELINE_16x16_MULT_REG1(1'b%s), + .PIPELINE_16x16_MULT_REG2(1'b%s), + .TOPOUTPUT_SELECT(2'b%s), + .TOPADDSUB_LOWERINPUT(2'b%s), + .TOPADDSUB_UPPERINPUT(1'b%s), + .TOPADDSUB_CARRYSELECT(2'b%s), + .BOTOUTPUT_SELECT(2'b%s), + .BOTADDSUB_LOWERINPUT(2'b%s), + .BOTADDSUB_UPPERINPUT(1'b%s), + .BOTADDSUB_CARRYSELECT(2'b%s), + .MODE_8x8(1'b%s), + .A_SIGNED(1'b%s), + .B_SIGNED(1'b%s) + ) dsp_%d ( + .CLK(%s), + .CE(%s), + .C(%s), + .A(%s), + .B(%s), + .D(%s), + .AHOLD(%s), + .BHOLD(%s), + .CHOLD(%s), + .DHOLD(%s), + .IRSTTOP(%s), + .IRSTBOT(%s), + .ORSTTOP(%s), + .ORSTBOT(%s), + .OLOADTOP(%s), + .OLOADBOT(%s), + .ADDSUBTOP(%s), + .ADDSUBBOT(%s), + .OHOLDTOP(%s), + .OHOLDBOT(%s), + .CI(%s), + .ACCUMCI(%s), + .SIGNEXTIN(%s), + .O(out_%d[31:0]), + .CO(out_%d[32]), + .ACCUMCO(out_%d[33]), + .SIGNEXTOUT(out_%d[34]) + );""" + % ( + i, + negclk, + params[0], params[1], params[2], params[3], + params[4], params[5], params[6], params[7], + params[8:10][::-1], params[10:12][::-1], params[12], params[13:15][::-1], + params[15:17][::-1], params[17:19][::-1], params[19], params[20:22][::-1], + params[22], params[23], params[24], + i, + bit_clk, bit_ce, bits_c, bits_a, bits_b, bits_d, + bit_ahold, bit_bhold, bit_chold, bit_dhold, + bit_irsttop, bit_irstbot, bit_orsttop, bit_orstbot, + bit_oloadtop, bit_oloadbot, bit_addsubtop, bit_addsubbot, + bit_oholdtop, bit_oholdbot, + bit_ci, bit_accumci, bit_signextin, + i, i, i, i + ), file=f) + bits = list(np.random.permutation(bits)) + for k in range(33): + bits[k] = "out_%d[%d] ^ %s" % (i, k, bits[k]) + for k in range(16): + print("assign out_pins[%d] = out_%d[%d] ^ out_%d[%d];" % (k, i, np.random.randint(33), i, np.random.randint(33)), file=f) + print("endmodule", file=f) + with open(working_dir + "/dsp_%02d.pcf" % idx, "w") as f: + p = list(np.random.permutation(pins)) + for i in range(len(pins) - len(glbs) - 16): + print("set_io in_pins[%d] %s" % (i, p.pop()), file=f) + for i in range(16): + print("set_io out_pins[%d] %s" % (i, p.pop()), file=f) + + +output_makefile(working_dir, "dsp") diff --git a/icefuzz/make_upip.py b/icefuzz/make_upip.py new file mode 100755 index 0000000..be6c5e0 --- /dev/null +++ b/icefuzz/make_upip.py @@ -0,0 +1,218 @@ +#!/usr/bin/env python3 + +from fuzzconfig import * +import numpy as np +import os + +device_class = os.getenv("ICEDEVICE") + +assert device_class == "5k" + +working_dir = "work_%s_upip" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) +def randbin(n): + return "".join([np.random.choice(["0", "1"]) for i in range(n)]) +for idx in range(num): + with open(working_dir + "/upip_%02d.v" % idx, "w") as f: + glbs = ["glb[%d]" % i for i in range(np.random.randint(6)+1)] + + print(""" + module top ( + input [%d:0] glb_pins, + input [%d:0] in_pins, + output [15:0] out_pins, + output [%d:0] led_pins + ); + wire [%d:0] glb, glb_pins; + SB_GB gbufs [%d:0] ( + .USER_SIGNAL_TO_GLOBAL_BUFFER(glb_pins), + .GLOBAL_BUFFER_OUTPUT(glb) + ); + """ % (len(glbs)-1, len(pins) - len(glbs) - 16 - 1, len(led_pins)-1, len(glbs)-1, len(glbs)-1), file=f) + bits = ["in_pins[%d]" % (i % (len(pins) - len(glbs) - 16 - 1)) for i in range(60)] + bits = list(np.random.permutation(bits)) + #Internal oscillators + tmp = ["in_pins[%d]" % i for i in range(len(pins) - len(glbs) - 16 - 1)] + tmp = list(np.random.permutation(tmp)) + for osc in ["LF", "HF"]: + bit_pu = tmp.pop() + bit_en = tmp.pop() + bit_clk = "clk_" + osc + glbs.append(bit_clk) + param = "" + if osc == "HF": #only HFOSC has a divider: + param = "#(.CLKHF_DIV(\"0b%s\"))" % randbin(2) + + route = np.random.choice(["", "/* synthesis ROUTE_THROUGH_FABRIC = 1 */"]) + + print(""" + SB_%sOSC %s osc_%s ( + .CLK%sPU(%s), + .CLK%sEN(%s), + .CLK%s(%s) + ) %s; + """ % ( + osc, param, osc, osc, bit_pu, + osc, bit_en, osc, bit_clk, route + ), file=f) + glbs_orig = list(glbs) + #256k SPRAM blocks + for i in range(num_spram256ka): + tmp = list(np.random.permutation(bits)) + + bits_addr = [tmp.pop() for k in range(14)] + bits_mask = [tmp.pop() for k in range(4)] + bits_wdata = [tmp.pop() for k in range(16)] + bit_wren = tmp.pop() + bit_cs = tmp.pop() + bit_clock = tmp.pop() + bit_standby = tmp.pop() + bit_sleep = tmp.pop() + bit_poweroff = tmp.pop() + + glbs_choice = ["clk", "a", "msk", "wd", "we", "cs", "stb", "slp", "po"] + + if len(glbs) != 0: + s = np.random.choice(glbs_choice) + glbs_choice.remove(s) + if s == "clk": bit_clock = glbs.pop() + if s == "a": bits_addr[np.random.randint(len(bits_addr))] = glbs.pop() + if s == "msk": bits_mask [np.random.randint(len(bits_mask ))] = glbs.pop() + if s == "wd": bits_wdata[np.random.randint(len(bits_wdata))] = glbs.pop() + if s == "we": bit_wren = glbs.pop() + if s == "cs": bit_cs = glbs.pop() + if s == "stb": bit_standby = glbs.pop() + if s == "slp": bit_sleep = glbs.pop() + if s == "po": bit_poweroff = glbs.pop() + bits_addr = "{%s}" % ", ".join(bits_addr) + bits_mask = "{%s}" % ", ".join(bits_mask) + bits_wdata = "{%s}" % ", ".join(bits_wdata) + + print(""" + wire [15:0] rdata_%d; + SB_SPRAM256KA spram_%d ( + .ADDRESS(%s), + .DATAIN(%s), + .MASKWREN(%s), + .WREN(%s), + .CHIPSELECT(%s), + .CLOCK(%s), + .STANDBY(%s), + .SLEEP(%s), + .POWEROFF(%s), + .DATAOUT(rdata_%d) + ); + """ % ( + i, i, + bits_addr, bits_wdata, bits_mask, bit_wren, + bit_cs, bit_clock, bit_standby, bit_sleep, + bit_poweroff, i + ), file=f) + bits = list(np.random.permutation(bits)) + if np.random.choice(["XOR", "MULT"]) == "MULT": + #stress routing at sides more with a multiply + print(""" + wire [31:0] mult_res_%d; + assign mult_res_%d = rdata_%d * %s; + """ % ( + i, i, i, ("{%s}" % ", ".join(bits[0:32])) + ), file=f) + for k in range(32): + bits[k] = "mult_res_%d[%d]" % (i, k) + else: + for k in range(16): + bits[k] = "rdata_%d[%d] ^ %s" % (i, k, bits[k]) + + # Internal PWM IP + tmp = list(np.random.permutation(bits)) + glbs = list(glbs_orig) + bit_cs = tmp.pop() + bit_clk = np.random.choice([glbs.pop(), tmp.pop()]) + bit_rst = np.random.choice([glbs.pop(), tmp.pop()]) + bit_den = tmp.pop() + bit_exe = tmp.pop() + + bits_dat = [tmp.pop() for k in range(8)] + bits_addr = [tmp.pop() for k in range(4)] + + print(""" + wire [2:0] pwm_out; + SB_LEDDA_IP ledda ( + .LEDDCS(%s), + .LEDDCLK(%s), + .LEDDDAT7(%s), + .LEDDDAT6(%s), + .LEDDDAT5(%s), + .LEDDDAT4(%s), + .LEDDDAT3(%s), + .LEDDDAT2(%s), + .LEDDDAT1(%s), + .LEDDDAT0(%s), + .LEDDADDR3(%s), + .LEDDADDR2(%s), + .LEDDADDR1(%s), + .LEDDADDR0(%s), + .LEDDDEN(%s), + .LEDDEXE(%s), + .LEDDRST(%s), + .PWMOUT0(pwm_out[0]), + .PWMOUT1(pwm_out[1]), + .PWMOUT2(pwm_out[2]) + ); + """ % ( + bit_cs, bit_clk, bits_dat[7], bits_dat[6], bits_dat[5], bits_dat[4], + bits_dat[3], bits_dat[2], bits_dat[1], bits_dat[0], bits_addr[3], + bits_addr[2], bits_addr[1], bits_addr[0], bit_den, bit_exe, bit_rst + ), file=f) + + bits.append("pwm_out[0]") + bits.append("pwm_out[1]") + bits.append("pwm_out[2]") + + # Constant current LED driver + current_choices = ["0b000000", "0b000001", "0b000011", "0b000111", "0b001111", "0b011111", "0b111111"] + current_modes = ["0b0", "0b1"] + + currents = [np.random.choice(current_choices) for i in range(3)] + + bit_curren = np.random.choice(bits) + bit_rgbleden = np.random.choice(bits) + bits_pwm = [np.random.choice([np.random.choice(bits), "pwm_out[%d]" % i]) for i in range(3)] + + print(""" + SB_RGBA_DRV #( + .CURRENT_MODE(\"%s\"), + .RGB0_CURRENT(\"%s\"), + .RGB1_CURRENT(\"%s\"), + .RGB2_CURRENT(\"%s\") + ) rgba_drv ( + .CURREN(%s), + .RGBLEDEN(%s), + .RGB0PWM(%s), + .RGB1PWM(%s), + .RGB2PWM(%s), + .RGB0(led_pins[0]), + .RGB1(led_pins[1]), + .RGB2(led_pins[2]) + ); + """ % ( + np.random.choice(current_modes), currents[0], currents[1], currents[2], + bit_curren, bit_rgbleden, bits_pwm[0], bits_pwm[1], bits_pwm[2] + ), file = f) + + # TODO: I2C and SPI + + print("assign out_pins = rdata_%d;" % i, file=f) + print("endmodule", file=f) + with open(working_dir + "/upip_%02d.pcf" % idx, "w") as f: + p = list(np.random.permutation(pins)) + for i in range(len(pins) - len(glbs) - 16): + print("set_io in_pins[%d] %s" % (i, p.pop()), file=f) + for i in range(16): + print("set_io out_pins[%d] %s" % (i, p.pop()), file=f) + for i in range(len(led_pins)): + print("set_io led_pins[%d] %s" % (i, led_pins[i]), file=f) + +output_makefile(working_dir, "upip") |