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+<title>Project IceStorm &ndash; LOGIC Tile Documentation</title>
+<h1>Project IceStorm &ndash; LOGIC Tile Documentation</h1>
+
+<p>
+<i><a href=".">Project IceStorm</a> aims at documenting the bitstream format of Lattice iCE40
+FPGAs and providing simple tools for analyzing and creating bitstream files.
+This is work in progress.</i>
+</p>
+
+<h2>Span-4 and Span-12 Wires</h2>
+
+<p>
+The <i>span-4</i> and <i>span-12</i> wires are the main interconnect resource in iCE40 FPGAs. They "span" (have a length of)
+4 or 12 cells in horizontal or vertical direction.
+</p>
+
+<p>
+The bits marked <tt>routing</tt> in the bitstream do enable switches (transfer gates) that can
+be used to connect wire segments bidirectionally to each other in order to create larger
+segments. The bits marked <tt>buffer</tt> in the bitstream enable tristate buffers that drive
+the signal in one direction from one wire to another. Both types of bits exist for routing between
+span-wires. See the auto generated documentation for the LOGIC Tile configuration bits for details.
+</p>
+
+<p>
+Only directional tristate buffers are used to route signals between the span-wires and the logic cells.
+</p>
+
+<h3 style="clear:both">Span-4 Horizontal</h3>
+
+<p><a href="sp4h.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="sp4h.svg" border="0"></a></p>
+
+<p>
+The image on the right shows the <i>horizontal span-4</i> wires of a logic or ram cell (click to enlarge).
+</p>
+
+<p>
+On the left side of the cell there are 48 connections named <tt>sp4_h_l_0</tt> to <tt>sp4_h_l_47</tt>. The lower 36 of those
+wires are connected to <tt>sp4_h_r_12</tt> to <tt>sp4_h_r_47</tt> on the right side of the cell. (IceStorm normalizes this
+wire names to <tt>sp4_h_r_0</tt> to <tt>sp4_h_r_35</tt>. Note: the Lattice tools use a different normalization scheme
+for this wire names.) The wires connecting the left and right horizontal span-4 ports are pairwise crossed-out.
+</p>
+
+<p>
+The wires <tt>sp4_h_l_36</tt> to <tt>sp4_h_l_47</tt> terminate in the cell, so do the wires <tt>sp4_h_r_0</tt> to <tt>sp4_h_r_11</tt>.
+</p>
+
+<p>
+This wires "span" 4 cells, i.e. they connect 5 cells if you count the cells on
+both ends of the wire.
+</p>
+
+<p>
+For example, the wire <tt>sp4_h_r_0</tt> in cell (x, y) has the following names:
+</p>
+
+<p align="center">
+<table border>
+<tr><th>Cell Coordinates</th><th>sp4_h_l_* wire name</th><th>sp4_h_r_* wire name</th></tr>
+<tr><td>x, y</td><td><tt>-</tt></td><td><tt>sp4_h_r_0</tt></td></tr>
+<tr><td>x+1, y</td><td><tt>sp4_h_l_0</tt></td><td><tt>sp4_h_r_13</tt></td></tr>
+<tr><td>x+2, y</td><td><tt>sp4_h_l_13</tt></td><td><tt>sp4_h_r_24</tt></td></tr>
+<tr><td>x+3, y</td><td><tt>sp4_h_l_24</tt></td><td><tt>sp4_h_r_37</tt></td></tr>
+<tr><td>x+4, y</td><td><tt>sp4_h_l_37</tt></td><td><tt>-</tt></td></tr>
+</table>
+</p>
+
+<h3 style="clear:both">Span-4 Vertical</h3>
+
+<p><a href="sp4v.svg"><img style="float:right; padding:1em; padding-top:0" height="200" src="sp4v.svg" border="0"></a></p>
+
+<p>
+The image on the right shows the <i>veritical span-4</i> wires of a logic or ram cell (click to enlarge).
+</p>
+
+<p>
+Similar to the horizontal span-4 wires there are 48 connections on the top (<tt>sp4_v_t_0</tt> to <tt>sp4_v_t_47</tt>) and
+48 connections on the bottom (<tt>sp4_v_b_0</tt> to <tt>sp4_v_b_47</tt>). The wires <tt>sp4_v_t_0</tt> to <tt>sp4_v_t_35</tt>
+are connected to <tt>sp4_v_b_12</tt> to <tt>sp4_v_b_47</tt> (with pairwise crossing out). Wire names are normalized
+to <tt>sp4_v_b_12</tt> to <tt>sp4_v_b_47</tt>.
+</p>
+
+<p>
+But in addition to that, each cell also has access to <tt>sp4_v_b_0</tt> to <tt>sp4_v_b_47</tt> of its right neighbour.
+This are the wires <tt>sp4_r_v_b_0</tt> to <tt>sp4_r_v_b_47</tt>. So over all a single veritical span-4 wire
+connects 9 cells. For example, the wire <tt>sp4_v_b_0</tt> in cell (x, y) has the following names:
+</p>
+
+<p align="center">
+<table border>
+<tr><th>Cell Coordinates</th><th>sp4_v_t_* wire name</th><th>sp4_v_b_* wire name</th><th>sp4_r_v_b_* wire name</th></tr>
+<tr><td>x, y</td><td><tt>-</tt></td><td><tt>sp4_v_b_0</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x, y-1</td><td><tt>sp4_v_t_0</tt></td><td><tt>sp4_v_b_13</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x, y-2</td><td><tt>sp4_v_t_13</tt></td><td><tt>sp4_v_b_24</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x, y-3</td><td><tt>sp4_v_t_24</tt></td><td><tt>sp4_v_b_37</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x, y-4</td><td><tt>sp4_v_t_37</tt></td><td><tt>-</tt></td><td><tt>-</tt></td></tr>
+<tr><td>x-1, y</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_0</tt></td></tr>
+<tr><td>x-1, y-1</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_13</tt></td></tr>
+<tr><td>x-1, y-2</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_24</tt></td></tr>
+<tr><td>x-1, y-3</td><td><tt>-</tt></td><td><tt>-</tt></td><td><tt>sp4_r_v_b_37</tt></td></tr>
+</table>
+</p>
+
+<h3 style="clear:both">Span-12 Horizontal and Vertical</h3>
+
+<p>
+Similar to the span-4 wires there are also longer horizontal and vertical span-12 wires.
+</p>
+
+<p>
+There are 24 connections <tt>sp12_v_t_0</tt> to <tt>sp12_v_t_23</tt> on the top of the
+cell and 24 connections <tt>sp12_v_b_0</tt> to <tt>sp12_v_b_23</tt> on the bottom of the
+cell. The wires <tt>sp12_v_t_0</tt> to <tt>sp12_v_t_21</tt> are connected to
+<tt>sp12_v_b_2</tt> to <tt>sp12_v_b_23</tt> (with pairwise crossing out). The connections
+<tt>sp12_v_b_0</tt>, <tt>sp12_v_b_1</tt>, <tt>sp12_v_t_22</tt>, and <tt>sp12_v_t_23</tt>
+terminate in the cell. Wire names are normalized to <tt>sp12_v_b_2</tt> to <tt>sp12_v_b_23</tt>.
+</p>
+
+<p>
+There are also 24 connections <tt>sp12_h_l_0</tt> to <tt>sp12_h_l_23</tt> on the left of the
+cell and 24 connections <tt>sp12_h_r_0</tt> to <tt>sp12_h_r_23</tt> on the right of the
+cell. The wires <tt>sp12_h_l_0</tt> to <tt>sp12_h_l_21</tt> are connected to
+<tt>sp12_h_r_2</tt> to <tt>sp12_h_r_23</tt> (with pairwise crossing out). The connections
+<tt>sp12_h_r_0</tt>, <tt>sp12_h_r_1</tt>, <tt>sp12_h_l_22</tt>, and <tt>sp12_h_l_23</tt>
+terminate in the cell. Wire names are normalized to <tt>sp12_v_r_2</tt> to <tt>sp12_h_r_23</tt>.
+</p>
+
+<h2>Local Tracks</h2>
+
+<p>
+The <i>local tracks</i> are the gateway to the logic cell inputs. Signals from the span-wires
+and the logic cell ouputs of the eight neighbour cells can be routed to the local tracks and
+signals from the local tracks can be routed to the logic cell inputs.
+</p>
+
+<p>
+Each logic tile has 32 local tracks. They are organized in 4 groups of 8 wires each:
+<tt>local_g0_0</tt> to <tt>local_g3_7</tt>.
+</p>
+
+<p>
+The span wires, global signals, and neighbour outputs can be routed to the local tracks. But not
+every of those signals can be routed to every of the local tracks. Instead there is a different
+mix of 16 signals for each local track.
+</p>
+
+<p>
+The buffer driving the local track has 5 configuration bits. One enable bit and 4 bits that select
+the input wire. For example for <tt>local_g0_0</tt> (copy&amp;paste from the bitstream doku):
+</p>
+
+<p align="center">
+<table border=""><tbody><tr>
+<th style="width:5em"><a name="B.0.14">B0[14]</a></th>
+<th style="width:5em"><a name="B.1.14">B1[14]</a></th>
+<th style="width:5em"><a name="B.1.15">B1[15]</a></th>
+<th style="width:5em"><a name="B.1.16">B1[16]</a></th>
+<th style="width:5em"><a name="B.1.17">B1[17]</a></th>
+<th style="width:5em">Function</th><th style="width:15em">Source-Net</th><th style="width:15em">Destination-Net</th></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_r_v_b_24</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp12_h_r_8</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_bot_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_v_b_16</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_r_v_b_35</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp12_h_r_16</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_top_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_h_r_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>lutff_0/out</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_v_b_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_lft_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_h_r_8</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>neigh_op_bnr_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_v_b_8</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp12_h_r_0</tt></td><td><tt>local_g0_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>sp4_h_r_16</tt></td><td><tt>local_g0_0</tt></td></tr>
+</tbody></table>
+</p>
+
+<p>
+Then the signals on the local tracks can be routed to the input pins of the logic cells. Like before,
+not every local track can be routed to every logic cell input pin. Instead there is a different mix
+of 16 local track for each logic cell input. For example for <tt>lutff_0/in_0</tt>:
+</p>
+
+<p align="center">
+<table border=""><tbody><tr>
+<th style="width:5em"><a name="B.0.26">B0[26]</a></th>
+<th style="width:5em"><a name="B.1.26">B1[26]</a></th>
+<th style="width:5em"><a name="B.1.27">B1[27]</a></th>
+<th style="width:5em"><a name="B.1.28">B1[28]</a></th>
+<th style="width:5em"><a name="B.1.29">B1[29]</a></th>
+<th style="width:5em">Function</th><th style="width:15em">Source-Net</th><th style="width:15em">Destination-Net</th></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_0</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_0</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_1</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_1</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_2</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_2</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_3</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_3</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_4</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_4</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_5</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_5</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g0_6</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g2_6</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g1_7</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">buffer</td><td><tt>local_g3_7</tt></td><td><tt>lutff_0/in_0</tt></td></tr>
+</tbody></table>
+</p>
+
+<p>
+The 8 global nets on the iCE40 can be routed to the local track via the <tt>glb2local_0</tt> to <tt>glb2local_3</tt>
+nets using a similar two-stage process. The logic block clock-enable and set-reset inputs can be driven
+directly from one of 4 global nets or from one of 4 local tracks. The logic block clock input can be driven
+from any of the global nets and from a few local tracks. See the bitstream documentation for details.
+</p>
+
+<h2>Logic Block</h2>
+
+<p>
+Each logic tile has a logic block containing 8 logic cells. Each logic cell contains a 4-input LUT, a carry
+unit and a flip-flop. Clock, clock enable, and set/reset inputs are shared along the 8 logic cells. So is the
+bit that configures positive/negative edge for the flip flops. But the three configuration bits that specify if
+the flip flop should be used, if it is set or reset by the set/reset input, and if the set/reset is synchronous
+or asynchrouns exist for each logic cell individually.
+</p>
+
+<p>
+Each LUT <i>i</i> has four input wires <tt>lutff_<i>i</i>/in_0</tt> to <tt>lutff_<i>i</i>/in_3</tt>. Input
+<tt>lutff_<i>i</i>/in_3</tt> can be configured to be driven by the carry output of the previous logic cell,
+or by <tt>carry_in_mux</tt> in case of <i>i</i>=0. Input <tt>lutff_<i>i</i>/in_2</tt> can be configured to
+be driven by the output of the previous LUT for <i>i</i>&gt;0. The LUT uses its 4 input signals to
+calculate <tt>lutff_<i>i</i>/out</tt>.
+</p>
+
+<p>
+The carry unit calculates <tt>lutff_<i>i</i>/cout</tt> = <tt>lutff_<i>i</i>/in_1</tt> + <tt>lutff_<i>i</i>/in_2</tt> + <tt>lutff_<i>(i-1)</i>/cout</tt> &gt; 1</tt>. In case of <i>i</i>=0, <tt>carry_in_mux</tt> is used as third input. <tt>carry_in_mux</tt> can be configured to be constant 0, 1 or the <tt>lutff_7/cout</tt> signal from the logic tile below.
+</p>
+
+<p>
+Part of the functionality described above is documented as part of the routing
+bitstream documentation (see the buffers for <tt>luttff_</tt> inputs). The <tt>NegClk</tt>
+bit switches all 8 FFs in the tile to negative edge mode. The <tt>CarryInSet</tt>
+bit drives the <tt>carry_in_mux</tt> high (it defaults to low when not driven via the buffer from
+<tt>carry_in</tt>).
+</p>
+
+<p>
+The remaining functions of the logic cell are configured via the <tt>LC_<i>i</i></tt> bits. This
+are 20 bit per logic cell. We have arbitrarily labeld those bits as follows:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>Label</th><th>LC_0</th><th>LC_1</th><th>LC_2</th><th>LC_3</th><th>LC_4</th><th>LC_5</th><th>LC_6</th><th>LC_7</th></tr>
+<tr><td>LC_<i>i</i>[0]</tt></td><td>B0[36]</td><td>B2[36]</td><td>B4[36]</td><td>B6[36]</td><td>B8[36]</td><td>B10[36]</td><td>B12[36]</td><td>B14[36]</td></tr>
+<tr><td>LC_<i>i</i>[1]</tt></td><td>B0[37]</td><td>B2[37]</td><td>B4[37]</td><td>B6[37]</td><td>B8[37]</td><td>B10[37]</td><td>B12[37]</td><td>B14[37]</td></tr>
+<tr><td>LC_<i>i</i>[2]</tt></td><td>B0[38]</td><td>B2[38]</td><td>B4[38]</td><td>B6[38]</td><td>B8[38]</td><td>B10[38]</td><td>B12[38]</td><td>B14[38]</td></tr>
+<tr><td>LC_<i>i</i>[3]</tt></td><td>B0[39]</td><td>B2[39]</td><td>B4[39]</td><td>B6[39]</td><td>B8[39]</td><td>B10[39]</td><td>B12[39]</td><td>B14[39]</td></tr>
+<tr><td>LC_<i>i</i>[4]</tt></td><td>B0[40]</td><td>B2[40]</td><td>B4[40]</td><td>B6[40]</td><td>B8[40]</td><td>B10[40]</td><td>B12[40]</td><td>B14[40]</td></tr>
+<tr><td>LC_<i>i</i>[5]</tt></td><td>B0[41]</td><td>B2[41]</td><td>B4[41]</td><td>B6[41]</td><td>B8[41]</td><td>B10[41]</td><td>B12[41]</td><td>B14[41]</td></tr>
+<tr><td>LC_<i>i</i>[6]</tt></td><td>B0[42]</td><td>B2[42]</td><td>B4[42]</td><td>B6[42]</td><td>B8[42]</td><td>B10[42]</td><td>B12[42]</td><td>B14[42]</td></tr>
+<tr><td>LC_<i>i</i>[7]</tt></td><td>B0[43]</td><td>B2[43]</td><td>B4[43]</td><td>B6[43]</td><td>B8[43]</td><td>B10[43]</td><td>B12[43]</td><td>B14[43]</td></tr>
+<tr><td>LC_<i>i</i>[8]</tt></td><td>B0[44]</td><td>B2[44]</td><td>B4[44]</td><td>B6[44]</td><td>B8[44]</td><td>B10[44]</td><td>B12[44]</td><td>B14[44]</td></tr>
+<tr><td>LC_<i>i</i>[9]</tt></td><td>B0[45]</td><td>B2[45]</td><td>B4[45]</td><td>B6[45]</td><td>B8[45]</td><td>B10[45]</td><td>B12[45]</td><td>B14[45]</td></tr>
+<tr><td>LC_<i>i</i>[10]</tt></td><td>B1[36]</td><td>B3[36]</td><td>B5[36]</td><td>B7[36]</td><td>B9[36]</td><td>B11[36]</td><td>B13[36]</td><td>B15[36]</td></tr>
+<tr><td>LC_<i>i</i>[11]</tt></td><td>B1[37]</td><td>B3[37]</td><td>B5[37]</td><td>B7[37]</td><td>B9[37]</td><td>B11[37]</td><td>B13[37]</td><td>B15[37]</td></tr>
+<tr><td>LC_<i>i</i>[12]</tt></td><td>B1[38]</td><td>B3[38]</td><td>B5[38]</td><td>B7[38]</td><td>B9[38]</td><td>B11[38]</td><td>B13[38]</td><td>B15[38]</td></tr>
+<tr><td>LC_<i>i</i>[13]</tt></td><td>B1[39]</td><td>B3[39]</td><td>B5[39]</td><td>B7[39]</td><td>B9[39]</td><td>B11[39]</td><td>B13[39]</td><td>B15[39]</td></tr>
+<tr><td>LC_<i>i</i>[14]</tt></td><td>B1[40]</td><td>B3[40]</td><td>B5[40]</td><td>B7[40]</td><td>B9[40]</td><td>B11[40]</td><td>B13[40]</td><td>B15[40]</td></tr>
+<tr><td>LC_<i>i</i>[15]</tt></td><td>B1[41]</td><td>B3[41]</td><td>B5[41]</td><td>B7[41]</td><td>B9[41]</td><td>B11[41]</td><td>B13[41]</td><td>B15[41]</td></tr>
+<tr><td>LC_<i>i</i>[16]</tt></td><td>B1[42]</td><td>B3[42]</td><td>B5[42]</td><td>B7[42]</td><td>B9[42]</td><td>B11[42]</td><td>B13[42]</td><td>B15[42]</td></tr>
+<tr><td>LC_<i>i</i>[17]</tt></td><td>B1[43]</td><td>B3[43]</td><td>B5[43]</td><td>B7[43]</td><td>B9[43]</td><td>B11[43]</td><td>B13[43]</td><td>B15[43]</td></tr>
+<tr><td>LC_<i>i</i>[18]</tt></td><td>B1[44]</td><td>B3[44]</td><td>B5[44]</td><td>B7[44]</td><td>B9[44]</td><td>B11[44]</td><td>B13[44]</td><td>B15[44]</td></tr>
+<tr><td>LC_<i>i</i>[19]</tt></td><td>B1[45]</td><td>B3[45]</td><td>B5[45]</td><td>B7[45]</td><td>B9[45]</td><td>B11[45]</td><td>B13[45]</td><td>B15[45]</td></tr>
+</table>
+</p>
+
+<p>
+<tt>LC_<i>i</i>[8]</tt> is the <tt>CarryEnable</tt> bit. This bit must be set if the carry logic is used.
+</p>
+
+<p>
+<tt>LC_<i>i</i>[9]</tt> is the <tt>DffEnable</tt> bit. It enables the output flip-flop for the LUT.
+</p>
+
+<p>
+<tt>LC_<i>i</i>[18]</tt> is the <tt>Set_NoReset</tt> bit. When this bit is set then the set/reset signal will set, not reset the flip-flop.
+</p>
+
+<p>
+<tt>LC_<i>i</i>[19]</tt> is the <tt>AsyncSetReset</tt> bit. When this bit is set then the set/reset signal is asynchronous to the clock.
+</p>
+
+<p>
+The LUT implements the following truth table:
+</p>
+
+<p align="center">
+<table cellpadding="3" border>
+<tr><th>in_3</th><th>in_2</th><th>in_1</th><th>in_0</th><th>out</th></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[4]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[14]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[15]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[5]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[6]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[16]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[17]</tt></td></tr>
+<tr><td align="center">0</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[7]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[3]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[13]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[12]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">0</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[2]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">0</td><td><tt>LC_<i>i</i>[1]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">0</td><td align="center">1</td><td><tt>LC_<i>i</i>[11]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">0</td><td><tt>LC_<i>i</i>[10]</tt></td></tr>
+<tr><td align="center">1</td><td align="center">1</td><td align="center">1</td><td align="center">1</td><td><tt>LC_<i>i</i>[0]</tt></td></tr>
+</table>
+</p>
+
+<p>
+LUT inputs that are not connected to anything are driven low. The set/reset
+signal is also driven low if not connected to any other driver, and the clock
+enable signal is driven high when left unconnected.
+</p>
+