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| author | Clifford Wolf <clifford@clifford.at> | 2016-01-01 00:32:28 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-01-01 00:32:28 +0100 |
| commit | ed545ce4ce569bb96b2cba017daf2731afdaa926 (patch) | |
| tree | 33e7629f0ae099a64c25dde8a657031c937a074e /icetime/cells.v | |
| parent | 3ee30532106d4aa92a0547730c992a06f0bbdef5 (diff) | |
| download | icestorm-ed545ce4ce569bb96b2cba017daf2731afdaa926.tar.gz icestorm-ed545ce4ce569bb96b2cba017daf2731afdaa926.tar.bz2 icestorm-ed545ce4ce569bb96b2cba017daf2731afdaa926.zip | |
icetime progress
Diffstat (limited to 'icetime/cells.v')
| -rw-r--r-- | icetime/cells.v | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/icetime/cells.v b/icetime/cells.v index 32ee1a7..c4b2045 100644 --- a/icetime/cells.v +++ b/icetime/cells.v @@ -864,3 +864,12 @@ module INTERCONN(I, O); input I; output O; endmodule + +module SB_RAM40_4K(RDATA, RCLK, RCLKE, RE, RADDR, WCLK, WCLKE, WE, WADDR, MASK, WDATA); + output [15:0] RDATA; + input RCLK, RCLKE, RE; + input [10:0] RADDR; + input WCLK, WCLKE, WE; + input [10:0] WADDR; + input [15:0] MASK, WDATA; +endmodule |