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authorScott Shawcroft <scott.shawcroft@gmail.com>2017-07-02 15:39:14 -0700
committerClifford Wolf <clifford@clifford.at>2017-07-04 12:12:13 +0200
commit15bcbb7c333ee184d87427e9fe734fd8ee6d5bd2 (patch)
tree102ea36cedc3d4aeebebaafc1ad5ce99fa1cde72 /icepack
parente395b747995758c2ce70c65924dcdf7cbca4f880 (diff)
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Correct cram mapping so glbcheck actually passes.
Diffstat (limited to 'icepack')
-rw-r--r--icepack/icepack.cc74
1 files changed, 63 insertions, 11 deletions
diff --git a/icepack/icepack.cc b/icepack/icepack.cc
index 327a092..ff12267 100644
--- a/icepack/icepack.cc
+++ b/icepack/icepack.cc
@@ -848,8 +848,48 @@ void FpgaConfig::write_cram_pbm(std::ostream &ofs, int bank_num) const
debug("## %s\n", __PRETTY_FUNCTION__);
info("Writing cram pbm file..\n");
- ofs << "P1\n";
+ ofs << "P3\n";
ofs << stringf("%d %d\n", 2*this->cram_width, 2*this->cram_height);
+ ofs << "255\n";
+ uint32_t tile_type[4][this->cram_width][this->cram_height];
+ for (int y = 0; y <= this->chip_height()+1; y++)
+ for (int x = 0; x <= this->chip_width()+1; x++)
+ {
+ CramIndexConverter cic(this, x, y);
+
+ uint32_t color = 0x000000;
+ if (cic.tile_type == "io") {
+ color = 0x00aa00;
+ } else if (cic.tile_type == "logic") {
+ if ((x + y) %2 == 0) {
+ color = 0x0000ff;
+ } else {
+ color = 0x0000aa;
+ }
+ if (x == 12 && y == 25) {
+ color = 0xaa00aa;
+ }
+ if (x == 12 && y == 24) {
+ color = 0x888888;
+ }
+ } else if (cic.tile_type == "ramt") {
+ color = 0xff0000;
+ } else if (cic.tile_type == "ramb") {
+ color = 0xaa0000;
+ } else if (cic.tile_type == "unsupported") {
+ color = 0x333333;
+ } else {
+ info("%s\n", cic.tile_type.c_str());
+ }
+
+ for (int bit_y = 0; bit_y < 16; bit_y++)
+ for (int bit_x = 0; bit_x < cic.tile_width; bit_x++) {
+ int cram_bank, cram_x, cram_y;
+ cic.get_cram_index(bit_x, bit_y, cram_bank, cram_x, cram_y);
+
+ tile_type[cram_bank][cram_x][cram_y] = color;
+ }
+ }
for (int y = 2*this->cram_height-1; y >= 0; y--) {
for (int x = 0; x < 2*this->cram_width; x++) {
int bank = 0, bank_x = x, bank_y = y;
@@ -858,9 +898,16 @@ void FpgaConfig::write_cram_pbm(std::ostream &ofs, int bank_num) const
if (bank_y >= this->cram_height)
bank |= 2, bank_y = 2*this->cram_height - bank_y - 1;
if (bank_num >= 0 && bank != bank_num)
- ofs << " 0";
- else
- ofs << (this->cram[bank][bank_x][bank_y] ? " 1" : " 0");
+ ofs << " 255 255 255";
+ else if (this->cram[bank][bank_x][bank_y]) {
+ ofs << " 255 255 255";
+ } else {
+ uint32_t color = tile_type[bank][bank_x][bank_y];
+ uint8_t r = color >> 16;
+ uint8_t g = color >> 8;
+ uint8_t b = color & 0xff;
+ ofs << stringf(" %d %d %d", r, g, b);
+ }
}
ofs << '\n';
}
@@ -880,6 +927,7 @@ void FpgaConfig::write_bram_pbm(std::ostream &ofs, int bank_num) const
bank |= 1, bank_x = 2*this->bram_width - bank_x - 1;
if (bank_y >= this->bram_height)
bank |= 2, bank_y = 2*this->bram_height - bank_y - 1;
+ info("%d %d %d\n", bank, bank_x, bank_y);
if (bank_num >= 0 && bank != bank_num)
ofs << " 0";
else
@@ -932,7 +980,7 @@ string FpgaConfig::tile_type(int x, int y) const
}
if (this->device == "5k") {
- if (x == 6 || x == 18) return y % 2 == 1 ? "ramb" : "ramt";
+ if (x == 6 || x == 19) return y % 2 == 1 ? "ramb" : "ramt";
return "logic";
}
@@ -1015,7 +1063,7 @@ CramIndexConverter::CramIndexConverter(const FpgaConfig *fpga, int tile_x, int t
this->left_right_io = this->tile_x == 0 || this->tile_x == chip_width+1;
this->right_half = this->tile_x > chip_width / 2;
if (this->fpga->device == "5k") {
- this->top_half = this->tile_y > chip_height / 3;
+ this->top_half = this->tile_y > (chip_height * 2 / 3);
} else {
this->top_half = this->tile_y > chip_height / 2;
}
@@ -1089,11 +1137,11 @@ BramIndexConverter::BramIndexConverter(const FpgaConfig *fpga, int tile_x, int t
bool right_half = this->tile_x > chip_width / 2;
bool top_half = this->tile_y > chip_height / 2;
- // The UltraPlus 5k line is special because the bottom quarter of the chip is
- // used for SRAM instead of logic. Therefore the bitstream for the bottom two
- // quadrants are half the height of the top.
+ // The UltraPlus 5k line is special because the top quarter of the chip is
+ // used for SRAM instead of logic. Therefore the bitstream for the top two
+ // quadrants are half the height of the bottom.
if (this->fpga->device == "5k") {
- top_half = this->tile_y > chip_height / 3;
+ top_half = this->tile_y > (chip_height / 3);
}
this->bank_num = 0;
@@ -1101,7 +1149,7 @@ BramIndexConverter::BramIndexConverter(const FpgaConfig *fpga, int tile_x, int t
if (!top_half) {
this->bank_num |= 1;
} else if (this->fpga->device == "5k") {
- y_offset = this->tile_y - chip_height / 3;
+ y_offset = this->tile_y - (chip_height / 3);
} else {
y_offset = this->tile_y - chip_height / 2;
}
@@ -1243,9 +1291,13 @@ int main(int argc, char **argv)
fpga_config.cram_clear();
fpga_config.cram_checkerboard(checkerboard_m);
}
+
+ info("netpbm\n");
if (netpbm_fill_tiles)
fpga_config.cram_fill_tiles();
+
+ info("fill done\n");
if (netpbm_mode) {
if (netpbm_bram)