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| author | Clifford Wolf <clifford@clifford.at> | 2015-08-02 10:10:07 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-08-02 10:10:07 +0200 |
| commit | fb015a44474485c910871a7b1ed3f09c399dd677 (patch) | |
| tree | 8e703d0ec95689ae3b678d96b56edde8b935023e /icefuzz/tests | |
| parent | dd00d41fb22f9b1f2715d1f8d93de43dc63ba88d (diff) | |
| download | icestorm-fb015a44474485c910871a7b1ed3f09c399dd677.tar.gz icestorm-fb015a44474485c910871a7b1ed3f09c399dd677.tar.bz2 icestorm-fb015a44474485c910871a7b1ed3f09c399dd677.zip | |
Improved colbufs test case
Diffstat (limited to 'icefuzz/tests')
| -rw-r--r-- | icefuzz/tests/colbufs.pcf | 22 | ||||
| -rw-r--r-- | icefuzz/tests/colbufs.v | 43 |
2 files changed, 48 insertions, 17 deletions
diff --git a/icefuzz/tests/colbufs.pcf b/icefuzz/tests/colbufs.pcf index 61c3d41..578f126 100644 --- a/icefuzz/tests/colbufs.pcf +++ b/icefuzz/tests/colbufs.pcf @@ -1,8 +1,14 @@ -set_io clk[0] J3 -set_io clk[1] G1 -set_io clk[2] R9 -set_io clk[3] F7 -set_io clk[4] K9 -set_io clk[5] C8 -set_io clk[6] H11 -set_io clk[7] H16 +# set_io clk[0] J3 +# set_io clk[1] G1 +# set_io clk[2] R9 +# set_io clk[3] F7 +# set_io clk[4] K9 +# set_io clk[5] C8 +# set_io clk[6] H11 +# set_io clk[7] H16 + +set_io clk[0] H16 + +set_location bitslice[0].ram40_upper 8 11 0 +set_location bitslice[0].ram40_lower 25 5 0 + diff --git a/icefuzz/tests/colbufs.v b/icefuzz/tests/colbufs.v index b84c189..fe086a9 100644 --- a/icefuzz/tests/colbufs.v +++ b/icefuzz/tests/colbufs.v @@ -1,18 +1,17 @@ module top #( - parameter NUM_BITS = 8 + parameter NUM_BITS = 1 ) ( input [NUM_BITS-1:0] clk, - output reg [NUM_BITS-1:0] y + output [NUM_BITS-1:0] y ); - wire [NUM_BITS-1:0] t1; - reg [NUM_BITS-1:0] t2; + wire [NUM_BITS-1:0] t1, t2, t3; genvar i; generate for (i = 0; i < NUM_BITS; i = i+1) begin:bitslice SB_RAM40_4K #( .READ_MODE(0), .WRITE_MODE(0) - ) ram40 ( + ) ram40_upper ( .WADDR(8'b0), .RADDR(8'b0), .MASK(~16'b0), @@ -26,9 +25,35 @@ module top #( .RCLK(clk[i]) ); - always @(posedge clk[i]) begin - t2[i] <= t1[i]; - y[i] <= t2[i]; - end + SB_RAM40_4K #( + .READ_MODE(0), + .WRITE_MODE(0) + ) ram40_lower ( + .WADDR(8'b0), + .RADDR(8'b0), + .MASK(~16'b0), + .WDATA(8'b0), + .RDATA(t2[i]), + .WE(1'b1), + .WCLKE(1'b1), + .WCLK(clk[i]), + .RE(1'b1), + .RCLKE(1'b1), + .RCLK(clk[i]) + ); + + SB_DFF dff ( + .C(clk[i]), + .D(t1[i] ^ t2[i]), + .Q(t3[i]) + ); + + SB_IO #( + .PIN_TYPE(6'b 0101_01) + ) out ( + .PACKAGE_PIN(y[i]), + .OUTPUT_CLK(clk[i]), + .D_OUT_0(t3[i]) + ); end endgenerate endmodule |