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| author | Clifford Wolf <clifford@clifford.at> | 2017-11-28 15:54:58 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-11-28 15:54:58 +0100 |
| commit | 14b44ca866665352e7146778bb932e45b5fdedbd (patch) | |
| tree | e4fe11646f421323406a8464aa605d4a84e2c73d /icefuzz/tests/sb_i2c.v | |
| parent | 6e9a2da5c46edf00f1dc87c86053b5edbc17d5d7 (diff) | |
| parent | 411bcc53ffc095379f20494cce2da9424e4c5465 (diff) | |
| download | icestorm-14b44ca866665352e7146778bb932e45b5fdedbd.tar.gz icestorm-14b44ca866665352e7146778bb932e45b5fdedbd.tar.bz2 icestorm-14b44ca866665352e7146778bb932e45b5fdedbd.zip | |
Merge pull request #110 from daveshah1/up5k_ip
UltraPlus Hard IP and icetime Support
Diffstat (limited to 'icefuzz/tests/sb_i2c.v')
| -rw-r--r-- | icefuzz/tests/sb_i2c.v | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/icefuzz/tests/sb_i2c.v b/icefuzz/tests/sb_i2c.v new file mode 100644 index 0000000..987f476 --- /dev/null +++ b/icefuzz/tests/sb_i2c.v @@ -0,0 +1,74 @@ +module top ( + input sbclki, sbrwi, sbstbi, + input sbadri0, sbadri1, sbadri7, + input sbdati0, sbdati1, sbdati7, + output sbdato0, sbdato1, sbdato7, + output sbacko, i2cirq, i2cwkup, + input scli, sdai, scli2, + output sclo, scloe, sdao, sdaoe +); + +SB_I2C #( + .I2C_SLAVE_INIT_ADDR("0b1111100001"), + .BUS_ADDR74("0b0001") +) i2c_ip ( + .SBCLKI(sbclki), + .SBRWI(sbrwi), + .SBSTBI(sbstbi), + + .SBADRI0(sbadri0), + .SBADRI1(sbadri1), + .SBADRI7(sbadri7), + + .SBDATI0(sbdati0), + .SBDATI1(sbdati1), + .SBDATI7(sbdati7), + + .SBDATO0(sbdato0), + .SBDATO1(sbdato1), + + .SBACKO(sbacko), + .I2CIRQ(i2cirq), + .I2CWKUP(i2cwkup), + + .SCLI(scli), + .SCLO(sclo), + .SCLOE(scloe), + + .SDAI(sdai), + .SDAO(sdao), + .SDAOE(sdaoe) +) +/* synthesis SDA_INPUT_DELAYED=0 */ +/* synthesis SDA_OUTPUT_DELAYED=0 */ +/* synthesis SCL_INPUT_FILTERED=1 */ +; + + + +SB_I2C #( + .I2C_SLAVE_INIT_ADDR("0b1111100010"), + .BUS_ADDR74("0b0011") +) i2c_ip2 ( + .SBCLKI(sbclki), + .SBRWI(sbrwi), + .SBSTBI(sbstbi), + + .SBADRI0(sbadri0), + .SBADRI1(sbadri1), + .SBADRI7(sbadri7), + + .SBDATI0(sbdati0), + .SBDATI1(sbdati1), + .SBDATI7(sbdati7), + + .SBDATO7(sbdato7), + + .SCLI(scli2) + +) +/* synthesis SDA_INPUT_DELAYED=0 */ +/* synthesis SDA_OUTPUT_DELAYED=0 */ +/* synthesis SCL_INPUT_FILTERED=1 */ +; +endmodule |