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| author | Clifford Wolf <clifford@clifford.at> | 2016-01-09 12:45:43 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-01-09 12:45:43 +0100 |
| commit | 2fe704227f4f5caa95aa0c79aee21c847d0236f0 (patch) | |
| tree | a9a379a8ae069ae06cbbab9e66154c1781fd4719 /icefuzz/cached_ramt.txt | |
| parent | c4e5a5e57f692cf88f08ad365e418fb5eb6119f0 (diff) | |
| download | icestorm-2fe704227f4f5caa95aa0c79aee21c847d0236f0.tar.gz icestorm-2fe704227f4f5caa95aa0c79aee21c847d0236f0.tar.bz2 icestorm-2fe704227f4f5caa95aa0c79aee21c847d0236f0.zip | |
Fuzzed RamCascade bits
Diffstat (limited to 'icefuzz/cached_ramt.txt')
| -rw-r--r-- | icefuzz/cached_ramt.txt | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/icefuzz/cached_ramt.txt b/icefuzz/cached_ramt.txt index 84c2126..d03bb92 100644 --- a/icefuzz/cached_ramt.txt +++ b/icefuzz/cached_ramt.txt @@ -3459,6 +3459,42 @@ (7 1) Ram config bit: MEMT_bram_cbit_0 (7 2) Ram config bit: MEMT_bram_cbit_3 (7 3) Ram config bit: MEMT_bram_cbit_2 +(7 4) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC01_inmux02_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_5 +(7 4) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_5 +(7 5) Cascade bit: MEMT_LC00_inmux00_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC01_inmux00_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC01_inmux02_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC02_inmux00_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC04_inmux00_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC05_inmux00_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC06_inmux00_bram_cbit_4 +(7 5) Cascade bit: MEMT_LC07_inmux00_bram_cbit_4 +(7 6) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC00_inmux02_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC01_inmux02_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC03_inmux00_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_7 +(7 6) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_7 +(7 7) Cascade bit: MEMT_LC00_inmux00_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC00_inmux02_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC01_inmux00_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC01_inmux02_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC02_inmux00_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC03_inmux00_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC04_inmux00_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC05_inmux00_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC06_inmux00_bram_cbit_6 +(7 7) Cascade bit: MEMT_LC07_inmux00_bram_cbit_6 (8 0) routing sp4_h_l_36 <X> sp4_h_r_1 (8 0) routing sp4_h_l_40 <X> sp4_h_r_1 (8 0) routing sp4_v_b_1 <X> sp4_h_r_1 |