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author | Clifford Wolf <clifford@clifford.at> | 2016-01-09 12:45:43 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-01-09 12:45:43 +0100 |
commit | 2fe704227f4f5caa95aa0c79aee21c847d0236f0 (patch) | |
tree | a9a379a8ae069ae06cbbab9e66154c1781fd4719 /icebox | |
parent | c4e5a5e57f692cf88f08ad365e418fb5eb6119f0 (diff) | |
download | icestorm-2fe704227f4f5caa95aa0c79aee21c847d0236f0.tar.gz icestorm-2fe704227f4f5caa95aa0c79aee21c847d0236f0.tar.bz2 icestorm-2fe704227f4f5caa95aa0c79aee21c847d0236f0.zip |
Fuzzed RamCascade bits
Diffstat (limited to 'icebox')
-rwxr-xr-x | icebox/icebox_html.py | 2 | ||||
-rw-r--r-- | icebox/iceboxdb.py | 8 |
2 files changed, 10 insertions, 0 deletions
diff --git a/icebox/icebox_html.py b/icebox/icebox_html.py index 82389c0..d0288ce 100755 --- a/icebox/icebox_html.py +++ b/icebox/icebox_html.py @@ -254,6 +254,8 @@ configuration bits it has and how it is connected to its neighbourhood.</p>""" % bitmap_cells[idx1][idx2]["label"] = "A" elif entry[1].startswith("RamConfig"): bitmap_cells[idx1][idx2]["label"] = "M" + elif entry[1].startswith("RamCascade"): + bitmap_cells[idx1][idx2]["label"] = "M" elif entry[1].startswith("PLL"): bitmap_cells[idx1][idx2]["label"] = "P" else: diff --git a/icebox/iceboxdb.py b/icebox/iceboxdb.py index dbbe765..ebf07ff 100644 --- a/icebox/iceboxdb.py +++ b/icebox/iceboxdb.py @@ -3896,6 +3896,10 @@ B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 """ database_ramt_txt = """ B0[0] NegClk +B5[7] RamCascade CBIT_4 +B4[7] RamCascade CBIT_5 +B7[7] RamCascade CBIT_6 +B6[7] RamCascade CBIT_7 B1[7] RamConfig CBIT_0 B0[7] RamConfig CBIT_1 B3[7] RamConfig CBIT_2 @@ -6759,6 +6763,10 @@ B12[7] ColBufCtrl 8k_glb_netwk_5 B15[7] ColBufCtrl 8k_glb_netwk_6 B14[7] ColBufCtrl 8k_glb_netwk_7 B0[0] NegClk +B5[7] RamCascade CBIT_4 +B4[7] RamCascade CBIT_5 +B7[7] RamCascade CBIT_6 +B6[7] RamCascade CBIT_7 B1[7] RamConfig CBIT_0 B0[7] RamConfig CBIT_1 B3[7] RamConfig CBIT_2 |