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authorClifford Wolf <clifford@clifford.at>2015-07-21 18:18:33 +0200
committerClifford Wolf <clifford@clifford.at>2015-07-21 18:20:57 +0200
commit1abd4d027ef3fcf8a08018bce594173cc8d00244 (patch)
tree0ded3b3b3b024bb811db5f0c1b99f1e466d3dc39 /icebox/icebox_vlog.py
parent828291051abd97536ef7204abfb634ac797d11a2 (diff)
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Added ram init support to icebox_vlog
Diffstat (limited to 'icebox/icebox_vlog.py')
-rwxr-xr-xicebox/icebox_vlog.py4
1 files changed, 3 insertions, 1 deletions
diff --git a/icebox/icebox_vlog.py b/icebox/icebox_vlog.py
index 11207f9..28d12e2 100755
--- a/icebox/icebox_vlog.py
+++ b/icebox/icebox_vlog.py
@@ -718,7 +718,9 @@ for tile in ic.ramb_tiles:
text_func.append("// RAM TILE %d %d" % tile)
text_func.append("SB_RAM40_4K #(");
text_func.append(" .READ_MODE(%d)," % ((1 if get_ram_config('CBIT_2') else 0) + (2 if get_ram_config('CBIT_3') else 0)));
- text_func.append(" .WRITE_MODE(%d)" % ((1 if get_ram_config('CBIT_0') else 0) + (2 if get_ram_config('CBIT_1') else 0)));
+ text_func.append(" .WRITE_MODE(%d)," % ((1 if get_ram_config('CBIT_0') else 0) + (2 if get_ram_config('CBIT_1') else 0)));
+ for i in range(16):
+ text_func.append(" .INIT_%X(256'h%s)%s" % (i, ic.ram_data[tile][i], "," if i < 15 else ""));
text_func.append(") ram40_%d_%d (" % tile);
text_func.append(" .WADDR(%s)," % get_ram_wire('WADDR', 10, 0))
text_func.append(" .RADDR(%s)," % get_ram_wire('RADDR', 10, 0))