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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-31 14:57:24 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-31 14:57:24 +0200 |
| commit | 872e333cf75c6fc1bdf985f09565c70d16567434 (patch) | |
| tree | 11a7b2336faaf12e84d8890c1674c04b0c8093a6 /docs/io_tile.html | |
| parent | f704149b7298c7c6b56520d104dc4b20abf455b2 (diff) | |
| parent | 81e943e050dad652da795d21375bb700064116f4 (diff) | |
| download | icestorm-872e333cf75c6fc1bdf985f09565c70d16567434.tar.gz icestorm-872e333cf75c6fc1bdf985f09565c70d16567434.tar.bz2 icestorm-872e333cf75c6fc1bdf985f09565c70d16567434.zip | |
Merge branch 'master' into ice5k
Diffstat (limited to 'docs/io_tile.html')
| -rw-r--r-- | docs/io_tile.html | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/docs/io_tile.html b/docs/io_tile.html index c683ff7..82cf65b 100644 --- a/docs/io_tile.html +++ b/docs/io_tile.html @@ -47,9 +47,9 @@ to <span style="font-family:monospace">span12_horz_23</span>. </p> <p> -A top/bottom io cell has 16 connections named <span style="font-family:monospace">span4_vert_l_0</span> to <span style="font-family:monospace">span4_vert_l_15</span> on its top edge and -16 connections named <span style="font-family:monospace">span4_vert_r_0</span> to <span style="font-family:monospace">span4_vert_r_15</span> on its bottom edge. The nets <span style="font-family:monospace">span4_vert_l_0</span> -to <span style="font-family:monospace">span4_vert_l_11</span> are connected to <span style="font-family:monospace">span4_vert_r_4</span> to <span style="font-family:monospace">span4_vert_r_15</span>. The span-4 and span-12 wires +A top/bottom io cell has 16 connections named <span style="font-family:monospace">span4_horz_l_0</span> to <span style="font-family:monospace">span4_horz_l_15</span> on its left edge and +16 connections named <span style="font-family:monospace">span4_horz_r_0</span> to <span style="font-family:monospace">span4_horz_r_15</span> on its right edge. The nets <span style="font-family:monospace">span4_horz_l_0</span> +to <span style="font-family:monospace">span4_horz_l_11</span> are connected to <span style="font-family:monospace">span4_horz_r_4</span> to <span style="font-family:monospace">span4_horz_r_15</span>. The span-4 and span-12 wires of the adjacent logic cell are connected to the nets <span style="font-family:monospace">span4_vert_0</span> to <span style="font-family:monospace">span4_vert_47</span> and <span style="font-family:monospace">span12_vert_0</span> to <span style="font-family:monospace">span12_vert_23</span>. </p> @@ -489,9 +489,9 @@ of the 1k chip: <tr><td>1 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">BYPASS</span></td></tr> <tr><td>2 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">RESETB</span></td></tr> <tr><td>5 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">LATCHINPUTVALUE</span></td></tr> -<tr><td>12 1</td><td><span style="font-family:monospace">neigh_op_bnl_1</span></td><td rowspan="1"><span style="font-family:monospace">SDO</span></td></tr> +<tr><td>12 1</td><td><span style="font-family:monospace">neigh_op_bnr_3</span></td><td rowspan="1"><span style="font-family:monospace">SDO</span></td></tr> <tr><td>4 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">SDI</span></td></tr> -<tr><td>5 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">SCLK</span></td></tr> +<tr><td>3 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">SCLK</span></td></tr> </table> <p> |