Spelling fixes in documentation (by Larry Doolittle)

1 files changed, 7 insertions, 7 deletions

diff --git a/docs/index.html b/docs/index.html
index e30ff1c..312d780 100644
--- a/docs/index.html
+++ b/docs/index.html
@@ -2,7 +2,7 @@
 <h1>Project IceStorm</h1>
 
 <p>
-<b>2015-07-19:</b> Released support for 8k chips. Moved IceStorm sourcecode to GitHub.<br/>
+<b>2015-07-19:</b> Released support for 8k chips. Moved IceStorm source code to GitHub.<br/>
 <b>2015-05-27:</b> We have a working fully Open Source flow with <a href="http://www.clifford.at/yosys/">Yosys</a> and <a href="https://github.com/cseed/arachne-pnr">Arachne-pnr</a>! Video: <a href="http://youtu.be/yUiNlmvVOq8">http://youtu.be/yUiNlmvVOq8</a><br/>
 <b>2015-04-13:</b> Complete rewrite of IceUnpack, added IcePack, some major documentation updates<br/>
 <b>2015-03-22:</b> First public release and short YouTube video demonstrating our work: <a href="http://youtu.be/u1ZHcSNDQMM">http://youtu.be/u1ZHcSNDQMM</a>
@@ -34,7 +34,7 @@ for all kinds of projects.
 <h2>What is the Status of the Project?</h2>
 
 <p>
-We have enough bits mapped that we can create a functional verilog model for almost all 
+We have enough bits mapped that we can create a functional Verilog model for almost all 
 bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144 and the iCE40 HX8K-CT256.
 </p>
 
@@ -56,7 +56,7 @@ iceprog rot.bin</pre>
 <h2>Where are the Tools? How to install?</h2>
 
 <p>
-Installing the <a hreaf="https://github.com/cliffordwolf/icestorm">IceStorm Tools</a> (icepack, icebox, iceprog):
+Installing the <a href="https://github.com/cliffordwolf/icestorm">IceStorm Tools</a> (icepack, icebox, iceprog):
 </p>
 
 <pre style="padding-left: 3em">git clone https://github.com/cliffordwolf/icestorm.git icestorm
@@ -97,13 +97,13 @@ that has blocks of <tt>0</tt> and <tt>1</tt> for the config bits for each tile i
 <p>
 A python library and various tools for working with IceBox ASCII files and accessing
 the device database. For example <tt>icebox_vlog.py</tt> converts our ASCII file
-dump of a bitstream into a verilog file that implements an equivalent circuit.
+dump of a bitstream into a Verilog file that implements an equivalent circuit.
 </p>
 
 <h3>IceProg</h3>
 
 <p>
-A small driver programm for the FTDI-based programmer used on the iCEstick and HX8K development boards.
+A small driver program for the FTDI-based programmer used on the iCEstick and HX8K development boards.
 </p>
 
 <h3>ChipDB</h3>
@@ -191,8 +191,8 @@ an example program that does that.
 <p>
 The recommended approach for learning how to use this documentation is to synthesize very simple circuits using
 Lattice iCEcube2, run our toolchain on the resulting bitstream files, and analyze the results using the HTML export of the database
-mentioned above. <tt>icebox_vlog.py</tt> can be used to convert the bitstream to verilog. The output file of
-this tool will also outline the signal paths in comments added to the generated verilog.
+mentioned above. <tt>icebox_vlog.py</tt> can be used to convert the bitstream to Verilog. The output file of
+this tool will also outline the signal paths in comments added to the generated Verilog.
 </p>
 
 <p>