UltraPlus DSPs working

5 files changed, 95 insertions, 1 deletions

diff --git a/examples/up5k_mac16/.gitignore b/examples/up5k_mac16/.gitignore
new file mode 100644
index 0000000..dd32bfb
--- /dev/null
+++ b/examples/up5k_mac16/.gitignore
@@ -0,0 +1,12 @@
+*.bin
+*.blif
+*.asc
+*.rpt
+*.glb
+*.psb
+*.sdf
+*.vsb
+*.bin
+*.tmp/
+*.exp
+*.vlog
diff --git a/examples/up5k_mac16/mac16.pcf b/examples/up5k_mac16/mac16.pcf
new file mode 100644
index 0000000..24b9b45
--- /dev/null
+++ b/examples/up5k_mac16/mac16.pcf
@@ -0,0 +1,4 @@
+set_io clk 44
+set_io rstn 27
+set_io LED1 12
+set_io LED2 13
\ No newline at end of file
diff --git a/examples/up5k_mac16/mac16.v b/examples/up5k_mac16/mac16.v
new file mode 100644
index 0000000..73740e3
--- /dev/null
+++ b/examples/up5k_mac16/mac16.v
@@ -0,0 +1,71 @@
+module top(
+  input clk,
+  input rstn,
+  output LED1,
+  output LED2);
+  
+wire reset = !rstn;
+  
+wire [15:0] A    = 16'd999;
+wire [15:0] B    = 16'd12345;
+wire [31:0] RES  = 32'd12332655;
+
+wire [31:0] dsp_out;
+
+SB_MAC16 i_sbmac16
+  (
+    .A(A),
+    .B(B),
+    .C(16'b0),
+    .D(16'b0),
+    .CLK(clk),
+    .CE(1'b1),
+    .IRSTTOP(reset),
+    .IRSTBOT(reset),
+    .ORSTTOP(reset),
+    .ORSTBOT(reset),
+    .AHOLD(1'b0),
+    .BHOLD(1'b0),
+    .CHOLD(1'b0),
+    .DHOLD(1'b0),
+    .OHOLDTOP(1'b0),
+    .OHOLDBOT(1'b0),
+    .OLOADTOP(1'b0),
+    .OLOADBOT(1'b0),
+    .ADDSUBTOP(1'b0),
+    .ADDSUBBOT(1'b0),
+    .CO(),
+    .CI(1'b0),
+    .O(dsp_out)
+  );
+
+//16x16 => 32 unsigned pipelined multiply
+defparam i_sbmac16. B_SIGNED                  = 1'b0;
+defparam i_sbmac16. A_SIGNED                  = 1'b0;
+defparam i_sbmac16. MODE_8x8                  = 1'b0;
+
+defparam i_sbmac16. BOTADDSUB_CARRYSELECT     = 2'b00;
+defparam i_sbmac16. BOTADDSUB_UPPERINPUT      = 1'b0;
+defparam i_sbmac16. BOTADDSUB_LOWERINPUT      = 2'b00;
+defparam i_sbmac16. BOTOUTPUT_SELECT          = 2'b11;
+
+defparam i_sbmac16. TOPADDSUB_CARRYSELECT     = 2'b00;
+defparam i_sbmac16. TOPADDSUB_UPPERINPUT      = 1'b0;
+defparam i_sbmac16. TOPADDSUB_LOWERINPUT      = 2'b00;
+defparam i_sbmac16. TOPOUTPUT_SELECT          = 2'b11;
+
+defparam i_sbmac16. PIPELINE_16x16_MULT_REG2  = 1'b1;
+defparam i_sbmac16. PIPELINE_16x16_MULT_REG1  = 1'b1;
+defparam i_sbmac16. BOT_8x8_MULT_REG          = 1'b1;
+defparam i_sbmac16. TOP_8x8_MULT_REG          = 1'b1;
+defparam i_sbmac16. D_REG                     = 1'b0;
+defparam i_sbmac16. B_REG                     = 1'b1;
+defparam i_sbmac16. A_REG                     = 1'b1;
+defparam i_sbmac16. C_REG                     = 1'b0;
+
+assign LED1 = (dsp_out == RES) ? 1'b1 : 1'b0;
+assign LED2 = 1'b0;
+
+
+
+endmodule
\ No newline at end of file
diff --git a/icebox/icebox.py b/icebox/icebox.py
index 60c73d1..12e1fca 100644
--- a/icebox/icebox.py
+++ b/icebox/icebox.py
@@ -4462,6 +4462,13 @@ dsp1_5k_db.append([["B4[7]"], "IpConfig", "CBIT_5"])
 dsp2_5k_db = parse_db(iceboxdb.database_dsp2_5k_txt, "5k")
 dsp3_5k_db = parse_db(iceboxdb.database_dsp3_5k_txt, "5k")
 
+#Add missing LC_ bits to DSP and IPCon databases
+for db_to_fix in [ipcon_5k_db, dsp0_5k_db, dsp1_5k_db, dsp2_5k_db, dsp3_5k_db]:
+    for entry in db_to_fix:
+        if len(entry) >= 2 and entry[1].startswith("LC_"):
+            for lentry in logictile_5k_db:
+                if len(lentry) >= 2 and lentry[1] == entry[1]:
+                    entry[0] = lentry[0]
 
 iotile_l_db = list()
 iotile_r_db = list()
diff --git a/icebox/icebox_explain.py b/icebox/icebox_explain.py
index 3b9875f..4e678ff 100755
--- a/icebox/icebox_explain.py
+++ b/icebox/icebox_explain.py
@@ -117,7 +117,7 @@ def print_tile(stmt, ic, x, y, tile, db):
         bitinfo.append("")
         extra_text = ""
         for i in range(len(line)):
-            if 36 <= i <= 45 and re.search(r"logic_tile", stmt):
+            if 36 <= i <= 45 and re.search(r"(logic_tile|dsp\d_tile|ipcon_tile)", stmt):
                 lutff_idx = k // 2
                 lutff_bitnum = (i-36) + 10*(k%2)
                 if line[i] == "1":