More work figuring out values in icebox.py

7 files changed, 223 insertions, 29 deletions

diff --git a/icebox/icebox.py b/icebox/icebox.py
index 79608be..577eaca 100644
--- a/icebox/icebox.py
+++ b/icebox/icebox.py
@@ -208,20 +208,28 @@ class iceconfig:
         assert False
 
     def tile_db(self, x, y):
-        if x == 0: return iotile_l_db
+        # Only these devices have IO on the left and right sides.
+        if self.device in ["384", "1k", "8k"]:
+          if x == 0: return iotile_l_db
+          if x == self.max_x: return iotile_r_db
         if y == 0: return iotile_b_db
-        if x == self.max_x: return iotile_r_db
         if y == self.max_y: return iotile_t_db
         if self.device == "1k":
             if (x, y) in self.logic_tiles: return logictile_db
             if (x, y) in self.ramb_tiles: return rambtile_db
             if (x, y) in self.ramt_tiles: return ramttile_db
-        if self.device == "8k":
+        elif self.device == "5k":
+            if (x, y) in self.logic_tiles: return logictile_5k_db
+            if (x, y) in self.ramb_tiles: return rambtile_5k_db
+            if (x, y) in self.ramt_tiles: return ramttile_5k_db
+        elif self.device == "8k":
             if (x, y) in self.logic_tiles: return logictile_8k_db
             if (x, y) in self.ramb_tiles: return rambtile_8k_db
             if (x, y) in self.ramt_tiles: return ramttile_8k_db
-        if self.device == "384":
+        elif self.device == "384":
             if (x, y) in self.logic_tiles: return logictile_384_db
+
+        print("Tile type unknown at (%d, %d)" % (x, y))
         assert False
 
     def tile_type(self, x, y):
@@ -568,7 +576,9 @@ class iceconfig:
                 for s in self.expand_net(queue.pop()):
                     if s not in segments:
                         segments.add(s)
-                        assert s not in seen_segments
+                        if s in seen_segments:
+                          print("//", s, "has already been seen. Check your bitmapping.")
+                          assert False
                         seen_segments.add(s)
                         seed_segments.discard(s)
                         if s in connected_segments:
@@ -1012,7 +1022,8 @@ def key_netname(netname):
 def run_checks_neigh():
     print("Running consistency checks on neighbour finder..")
     ic = iceconfig()
-    ic.setup_empty_1k()
+    # ic.setup_empty_1k()
+    ic.setup_empty_5k()
     # ic.setup_empty_8k()
     # ic.setup_empty_384()
 
@@ -1028,8 +1039,12 @@ def run_checks_neigh():
 
     for x in range(ic.max_x+1):
         for y in range(ic.max_x+1):
+            # Skip the corners.
             if x in (0, ic.max_x) and y in (0, ic.max_y):
                 continue
+            # Skip the sides of a 5k device.
+            if ic.device == "5k" and x in (0, ic.max_x):
+                continue
             add_segments((x, y), ic.tile_db(x, y))
             if (x, y) in ic.logic_tiles:
                 all_segments.add((x, y, "lutff_7/cout"))
@@ -1091,6 +1106,16 @@ extra_bits_db = {
         (0, 330, 143): ("padin_glb_netwk", "6"),
         (0, 331, 143): ("padin_glb_netwk", "7"),
     },
+    "5k": {
+        (0, 870, 270): ("padin_glb_netwk", "0"),
+        (0, 871, 270): ("padin_glb_netwk", "1"),
+        (1, 870, 271): ("padin_glb_netwk", "2"),
+        (1, 871, 271): ("padin_glb_netwk", "3"),
+        (1, 870, 270): ("padin_glb_netwk", "4"),
+        (1, 871, 270): ("padin_glb_netwk", "5"),
+        (0, 870, 271): ("padin_glb_netwk", "6"),
+        (0, 871, 271): ("padin_glb_netwk", "7"),
+    },
     "8k": {
         (0, 870, 270): ("padin_glb_netwk", "0"),
         (0, 871, 270): ("padin_glb_netwk", "1"),
@@ -1124,6 +1149,8 @@ gbufin_db = {
         ( 6,  0,  5),
         ( 6, 17,  4),
     ],
+    "5k": [
+    ],
     "8k": [
         (33, 16,  7),
         ( 0, 16,  6),
@@ -1146,6 +1173,14 @@ gbufin_db = {
     ]
 }
 
+# To figure these out:
+#   1. Copy io_latched.sh and convert it for your pinout (like io_latched_5k.sh).
+#   2. Run it. It will create an io_latched_<device>.work directory with a bunch of files.
+#   3. Grep the *.ve files in that directory for "'fabout')". The coordinates
+#      before it are where the io latches are.
+#
+# Note: This may not work if your icepack configuration of cell sizes is incorrect because
+# icebox_vlog.py won't correctly interpret the meaning of particular bits.
 iolatch_db = {
     "1k": [
         ( 0,  7),
@@ -1153,6 +1188,10 @@ iolatch_db = {
         ( 5,  0),
         ( 8, 17),
     ],
+    "5k": [
+        (14, 0),
+        (14, 31),
+    ],
     "8k": [
         ( 0, 15),
         (33, 18),
@@ -1167,12 +1206,20 @@ iolatch_db = {
     ],
 }
 
+# The x, y cell locations of the WARMBOOT controls. Run tests/sb_warmboot.v
+# through icecube.sh to determine these values.
 warmbootinfo_db = {
     "1k": {
         "BOOT": ( 12, 0, "fabout" ),
         "S0":   ( 13, 1, "fabout" ),
         "S1":   ( 13, 2, "fabout" ),
     },
+    "5k": {
+        # These are the right locations but may be the wrong order.
+        "BOOT": ( 22, 0, "fabout" ),
+        "S0":   ( 23, 0, "fabout" ),
+        "S1":   ( 24, 0, "fabout" ),
+    },
     "8k": {
         "BOOT": ( 31, 0, "fabout" ),
         "S0":   ( 33, 1, "fabout" ),
@@ -1293,6 +1340,99 @@ pllinfo_db = {
         "SDI":                  ( 4,  0, "fabout"),
         "SCLK":                 ( 3,  0, "fabout"),
     },
+    "5k": {
+        "LOC" : (16, 0),
+
+        # 3'b000 = "DISABLED"
+        # 3'b010 = "SB_PLL40_PAD"
+        # 3'b100 = "SB_PLL40_2_PAD"
+        # 3'b110 = "SB_PLL40_2F_PAD"
+        # 3'b011 = "SB_PLL40_CORE"
+        # 3'b111 = "SB_PLL40_2F_CORE"
+        "PLLTYPE_0":            ( 16, 0, "PLLCONFIG_5"),
+        "PLLTYPE_1":            ( 18, 0, "PLLCONFIG_1"),
+        "PLLTYPE_2":            ( 18, 0, "PLLCONFIG_3"),
+
+        # 3'b000 = "DELAY"
+        # 3'b001 = "SIMPLE"
+        # 3'b010 = "PHASE_AND_DELAY"
+        # 3'b110 = "EXTERNAL"
+        "FEEDBACK_PATH_0":      ( 18, 0, "PLLCONFIG_5"),
+        "FEEDBACK_PATH_1":      ( 15, 0, "PLLCONFIG_9"),
+        "FEEDBACK_PATH_2":      ( 16, 0, "PLLCONFIG_1"),
+
+        # 1'b0 = "FIXED"
+        # 1'b1 = "DYNAMIC" (also set FDA_FEEDBACK=4'b1111)
+        "DELAY_ADJMODE_FB":     ( 17, 0, "PLLCONFIG_4"),
+
+        # 1'b0 = "FIXED"
+        # 1'b1 = "DYNAMIC" (also set FDA_RELATIVE=4'b1111)
+        "DELAY_ADJMODE_REL":    ( 17, 0, "PLLCONFIG_9"),
+
+        # 2'b00 = "GENCLK"
+        # 2'b01 = "GENCLK_HALF"
+        # 2'b10 = "SHIFTREG_90deg"
+        # 2'b11 = "SHIFTREG_0deg"
+        "PLLOUT_SELECT_A_0":    ( 16, 0, "PLLCONFIG_6"),
+        "PLLOUT_SELECT_A_1":    ( 16, 0, "PLLCONFIG_7"),
+
+        # 2'b00 = "GENCLK"
+        # 2'b01 = "GENCLK_HALF"
+        # 2'b10 = "SHIFTREG_90deg"
+        # 2'b11 = "SHIFTREG_0deg"
+        "PLLOUT_SELECT_B_0":    ( 16, 0, "PLLCONFIG_2"),
+        "PLLOUT_SELECT_B_1":    ( 16, 0, "PLLCONFIG_3"),
+
+        # Numeric Parameters
+        "SHIFTREG_DIV_MODE":    ( 16, 0, "PLLCONFIG_4"),
+        "FDA_FEEDBACK_0":       ( 16, 0, "PLLCONFIG_9"),
+        "FDA_FEEDBACK_1":       ( 17, 0, "PLLCONFIG_1"),
+        "FDA_FEEDBACK_2":       ( 17, 0, "PLLCONFIG_2"),
+        "FDA_FEEDBACK_3":       ( 17, 0, "PLLCONFIG_3"),
+        "FDA_RELATIVE_0":       ( 17, 0, "PLLCONFIG_5"),
+        "FDA_RELATIVE_1":       ( 17, 0, "PLLCONFIG_6"),
+        "FDA_RELATIVE_2":       ( 17, 0, "PLLCONFIG_7"),
+        "FDA_RELATIVE_3":       ( 17, 0, "PLLCONFIG_8"),
+        "DIVR_0":               ( 14, 0, "PLLCONFIG_1"),
+        "DIVR_1":               ( 14, 0, "PLLCONFIG_2"),
+        "DIVR_2":               ( 14, 0, "PLLCONFIG_3"),
+        "DIVR_3":               ( 14, 0, "PLLCONFIG_4"),
+        "DIVF_0":               ( 14, 0, "PLLCONFIG_5"),
+        "DIVF_1":               ( 14, 0, "PLLCONFIG_6"),
+        "DIVF_2":               ( 14, 0, "PLLCONFIG_7"),
+        "DIVF_3":               ( 14, 0, "PLLCONFIG_8"),
+        "DIVF_4":               ( 14, 0, "PLLCONFIG_9"),
+        "DIVF_5":               ( 15, 0, "PLLCONFIG_1"),
+        "DIVF_6":               ( 15, 0, "PLLCONFIG_2"),
+        "DIVQ_0":               ( 15, 0, "PLLCONFIG_3"),
+        "DIVQ_1":               ( 15, 0, "PLLCONFIG_4"),
+        "DIVQ_2":               ( 15, 0, "PLLCONFIG_5"),
+        "FILTER_RANGE_0":       ( 15, 0, "PLLCONFIG_6"),
+        "FILTER_RANGE_1":       ( 15, 0, "PLLCONFIG_7"),
+        "FILTER_RANGE_2":       ( 15, 0, "PLLCONFIG_8"),
+        "TEST_MODE":            ( 16, 0, "PLLCONFIG_8"),
+
+        # PLL Ports
+        "PLLOUT_A":             ( 16, 0, 1),
+        "PLLOUT_B":             ( 17, 0, 0),
+        "REFERENCECLK":         ( 13, 0, "fabout"),
+        "EXTFEEDBACK":          ( 14, 0, "fabout"),
+        "DYNAMICDELAY_0":       (  5, 0, "fabout"),
+        "DYNAMICDELAY_1":       (  6, 0, "fabout"),
+        "DYNAMICDELAY_2":       (  7, 0, "fabout"),
+        "DYNAMICDELAY_3":       (  8, 0, "fabout"),
+        "DYNAMICDELAY_4":       (  9, 0, "fabout"),
+        "DYNAMICDELAY_5":       ( 10, 0, "fabout"),
+        "DYNAMICDELAY_6":       ( 11, 0, "fabout"),
+        "DYNAMICDELAY_7":       ( 12, 0, "fabout"),
+        "LOCK":                 (  1, 1, "neigh_op_bnl_1"),
+        "BYPASS":               ( 19, 0, "fabout"),
+        "RESETB":               ( 20, 0, "fabout"),
+        "LATCHINPUTVALUE":      ( 15, 0, "fabout"),
+        "SDO":                  ( 32, 1, "neigh_op_bnr_3"),
+        "SDI":                  ( 22, 0, "fabout"),
+        "SCLK":                 ( 21, 0, "fabout"),
+    },
     "8k_0": {
         "LOC" : (16, 0),
 
@@ -1481,8 +1621,6 @@ pllinfo_db = {
     },
 }
 
-# TODO(tannewt): Correct these values for 5k once we figure out how to get the
-# info.
 padin_pio_db = {
     "1k": [
         (13,  8, 1),  # glb_netwk_0
@@ -1495,14 +1633,11 @@ padin_pio_db = {
         ( 6, 17, 1),  # glb_netwk_7
     ],
     "5k": [
-        (33, 16, 1),
-        ( 0, 16, 1),
-        (17, 33, 0),
-        (17,  0, 0),
-        ( 0, 17, 0),
-        (33, 17, 0),
-        (16,  0, 1),
-        (16, 33, 1),
+        ( 6,  0, 1),
+        (19,  0, 1),
+        ( 6, 31, 0),
+        (12, 31, 1),
+        (13, 31, 0),
     ],
     "8k": [
         (33, 16, 1),
diff --git a/icebox/icebox_vlog.py b/icebox/icebox_vlog.py
index 4033f01..e046de1 100755
--- a/icebox/icebox_vlog.py
+++ b/icebox/icebox_vlog.py
@@ -728,7 +728,7 @@ for tile in ic.ramb_tiles:
         if len(wire_bits) > 1:
             return "{%s}" % ", ".join(wire_bits)
         return wire_bits[0]
-    if get_ram_config('PowerUp') == (ic.device == "8k"):
+    if get_ram_config('PowerUp') == (ic.device in ("8k", "5k")):
         if not strip_comments:
             text_func.append("// RAM TILE %d %d" % tile)
         text_func.append("SB_RAM40_4K%s%s #(" % ("NR" if negclk_rd else "", "NW" if negclk_wr else ""));
diff --git a/icefuzz/Makefile b/icefuzz/Makefile
index 47aeb0c..b3e3b95 100644
--- a/icefuzz/Makefile
+++ b/icefuzz/Makefile
@@ -47,9 +47,14 @@ database: bitdata_io.txt bitdata_logic.txt bitdata_ramb$(RAM_SUFFIX).txt bitdata
 ifneq ($(RAM_SUFFIX),)
 	cp cached_ramb.txt bitdata_ramb.txt
 	cp cached_ramt.txt bitdata_ramt.txt
-else
-	cp cached_ramb$(RAM_SUFFIX).txt bitdata_ramb$(RAM_SUFFIX).txt
-	cp cached_ramt$(RAM_SUFFIX).txt bitdata_ramt$(RAM_SUFFIX).txt
+endif
+ifneq ($(RAM_SUFFIX),_8k)
+	cp cached_ramb_8k.txt bitdata_ramb_8k.txt
+	cp cached_ramt_8k.txt bitdata_ramt_8k.txt
+endif
+ifneq ($(RAM_SUFFIX),_5k)
+	cp cached_ramb_5k.txt bitdata_ramb_5k.txt
+	cp cached_ramt_5k.txt bitdata_ramt_5k.txt
 endif
 	ICEDEVICE=$(DEVICECLASS) python3 database.py
 	python3 export.py
diff --git a/icefuzz/cached_io.txt b/icefuzz/cached_io.txt
index ceab399..eb247af 100644
--- a/icefuzz/cached_io.txt
+++ b/icefuzz/cached_io.txt
@@ -553,9 +553,12 @@
 (2 2) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_4
 (2 2) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_4
 (2 2) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_4
+(2 2) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_4
+(2 2) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_4
 (2 2) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_4
 (2 2) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_4
 (2 2) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_4
+(2 2) PLL config bit: CLOCK_T_14_31_IOUP_cf_bit_4
 (2 2) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_4
 (2 2) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_4
 (2 2) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_4
@@ -671,8 +674,12 @@
 (3 2) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_5
 (3 2) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_5
 (3 2) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_5
+(3 2) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_5
+(3 2) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_5
+(3 2) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_5
 (3 2) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_5
 (3 2) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_5
+(3 2) PLL config bit: CLOCK_T_14_31_IOUP_cf_bit_5
 (3 2) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_5
 (3 2) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_5
 (3 2) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_5
@@ -682,7 +689,9 @@
 (3 3) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_3
 (3 3) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_3
 (3 3) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_3
+(3 3) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_3
 (3 3) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_3
+(3 3) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_3
 (3 3) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_3
 (3 3) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_3
 (3 3) PLL config bit: CLOCK_T_14_31_IOUP_cf_bit_3
@@ -704,7 +713,9 @@
 (3 5) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_6
 (3 5) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_6
 (3 5) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_6
+(3 5) PLL config bit: CLOCK_T_10_31_IOUP_cf_bit_6
 (3 5) PLL config bit: CLOCK_T_11_31_IOUP_cf_bit_6
+(3 5) PLL config bit: CLOCK_T_12_31_IOUP_cf_bit_6
 (3 5) PLL config bit: CLOCK_T_13_31_IOUP_cf_bit_6
 (3 5) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_6
 (3 5) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_6
diff --git a/icefuzz/database.py b/icefuzz/database.py
index 979b92b..50a28fc 100644
--- a/icefuzz/database.py
+++ b/icefuzz/database.py
@@ -138,11 +138,11 @@ with open("database_ramt.txt", "w") as f:
     for entry in read_database("bitdata_ramt.txt", "ramt"):
         print("\t".join(entry), file=f)
 
-if device_class in ["5k", "8k"]:
+for device_class in ["5k", "8k"]:
   with open("database_ramb_%s.txt" % (device_class, ), "w") as f:
       for entry in read_database("bitdata_ramb_%s.txt" % (device_class, ), "ramb_" + device_class):
           print("\t".join(entry), file=f)
 
-  with open("database_ramt_8k.txt", "w") as f:
+  with open("database_ramt_%s.txt" % (device_class, ), "w") as f:
       for entry in read_database("bitdata_ramt_%s.txt" % (device_class, ), "ramt_" + device_class):
           print("\t".join(entry), file=f)
diff --git a/icefuzz/tests/io_latched_5k.sh b/icefuzz/tests/io_latched_5k.sh
new file mode 100644
index 0000000..a43c77f
--- /dev/null
+++ b/icefuzz/tests/io_latched_5k.sh
@@ -0,0 +1,27 @@
+#!/bin/bash
+
+set -ex
+
+mkdir -p io_latched_5k.work
+cd io_latched_5k.work
+
+pins="
+2 3 4 6 9 10 11 12
+13 18 19 20 21 23
+25 26 27 28 31 32 34 35 36
+37 38 42 43 44 45 46 47 48
+"
+pins="$( echo $pins )"
+
+for pin in $pins ; do
+	pf="io_latched_$pin"
+	cp ../io_latched.v ${pf}.v
+	read pin_latch pin_data < <( echo $pins | tr ' ' '\n' | grep -v $pin | sort -R; )
+	{
+		echo "set_io pin $pin"
+		echo "set_io latch_in $pin_latch"
+		echo "set_io data_out $pin_data"
+	} > ${pf}.pcf
+	ICEDEV=up5k-sg48 bash ../../icecube.sh ${pf}.v
+	../../../icebox/icebox_vlog.py -SP ${pf}.psb ${pf}.asc > ${pf}.ve
+done
diff --git a/icepack/icepack.cc b/icepack/icepack.cc
index 90c5eb1..327a092 100644
--- a/icepack/icepack.cc
+++ b/icepack/icepack.cc
@@ -415,10 +415,11 @@ void FpgaConfig::write_bits(std::ostream &ofs) const
 	for (auto byte : this->initblop)
 		ofs << byte;
 
-	debug("Writing preamble.\n");
+	info("Writing preamble.\n");
 	write_byte(ofs, crc_value, file_offset, 0x7E);
 	write_byte(ofs, crc_value, file_offset, 0xAA);
 	write_byte(ofs, crc_value, file_offset, 0x99);
+	info("blah");
 	write_byte(ofs, crc_value, file_offset, 0x7E);
 
 	debug("Setting freqrange to '%s'.\n", this->freqrange.c_str());
@@ -773,7 +774,7 @@ void FpgaConfig::write_ascii(std::ostream &ofs) const
 	{
 		CramIndexConverter cic(this, x, y);
 
-		if (cic.tile_type == "corner")
+		if (cic.tile_type == "corner" || cic.tile_type == "unsupported")
 			continue;
 
 		ofs << stringf(".%s_tile %d %d\n", cic.tile_type.c_str(), x, y);
@@ -783,6 +784,12 @@ void FpgaConfig::write_ascii(std::ostream &ofs) const
 				int cram_bank, cram_x, cram_y;
 				cic.get_cram_index(bit_x, bit_y, cram_bank, cram_x, cram_y);
 				tile_bits.insert(tile_bit_t(cram_bank, cram_x, cram_y));
+				if (cram_x > int(this->cram[cram_bank].size())) {
+					error("cram_x %d (bit %d, %d) larger than bank size %lu\n", cram_x, bit_x, bit_y, this->cram[cram_bank].size());
+				}
+				if (cram_y > int(this->cram[cram_bank][cram_x].size())) {
+						error("cram_y %d larger than bank size %lu\n", cram_y, this->cram[cram_bank][cram_x].size());
+				}
 				ofs << (this->cram[cram_bank][cram_x][cram_y] ? '1' : '0');
 			}
 			ofs << '\n';
@@ -800,11 +807,11 @@ void FpgaConfig::write_ascii(std::ostream &ofs) const
 						int bram_bank, bram_x, bram_y;
 						bic.get_bram_index(bit_x+i, bit_y, bram_bank, bram_x, bram_y);
 						if (bram_x >= int(this->bram[bram_bank].size())) {
-							error("bram_x %u higher than loaded bram size %lu\n", bram_x,  this->bram[bram_bank].size());
+							error("%d %d bram_x %d higher than loaded bram size %lu\n",bit_x+i, bit_y, bram_x,  this->bram[bram_bank].size());
 							break;
 						}
 						if (bram_y >= int(this->bram[bram_bank][bram_x].size())) {
-							error("bram_y %u higher than loaded bram size %lu\n", bram_y,  this->bram[bram_bank][bram_x].size());
+							error("bram_y %d higher than loaded bram size %lu\n", bram_y,  this->bram[bram_bank][bram_x].size());
 							break;
 						}
 						if (this->bram[bram_bank][bram_x][bram_y])
@@ -905,7 +912,7 @@ vector<int> FpgaConfig::chip_cols() const
 	if (this->device == "384") return vector<int>({18, 54, 54, 54, 54});
 	if (this->device == "1k") return vector<int>({18, 54, 54, 42, 54, 54, 54});
 	// Its IPConnect or Mutiplier block, five logic, ram, six logic.
-	if (this->device == "5k") return vector<int>({18, 54, 54, 54, 54, 54, 42, 54, 54, 54, 54, 54, 54});
+	if (this->device == "5k") return vector<int>({54, 54, 54, 54, 54, 54, 42, 54, 54, 54, 54, 54, 54});
 	if (this->device == "8k") return vector<int>({18, 54, 54, 54, 54, 54, 54, 54, 42, 54, 54, 54, 54, 54, 54, 54, 54});
 	panic("Unknown chip type '%s'.\n", this->device.c_str());
 }
@@ -913,6 +920,8 @@ vector<int> FpgaConfig::chip_cols() const
 string FpgaConfig::tile_type(int x, int y) const
 {
 	if ((x == 0 || x == this->chip_width()+1) && (y == 0 || y == this->chip_height()+1)) return "corner";
+	// The sides on the 5k devices are unsupported tile types.
+	if (this->device == "5k" && (x == 0 || x == this->chip_width()+1)) return "unsupported";
 	if ((x == 0 || x == this->chip_width()+1) || (y == 0 || y == this->chip_height()+1)) return "io";
 
 	if (this->device == "384") return "logic";
@@ -942,6 +951,7 @@ int FpgaConfig::tile_width(const string &type) const
 	if (type == "ramb")   return 42;
 	if (type == "ramt")   return 42;
 	if (type == "io")     return 18;
+	if (type == "unsupported")     return 76;
 	panic("Unknown tile type '%s'.\n", type.c_str());
 }
 
@@ -1004,7 +1014,11 @@ CramIndexConverter::CramIndexConverter(const FpgaConfig *fpga, int tile_x, int t
 
 	this->left_right_io = this->tile_x == 0 || this->tile_x == chip_width+1;
 	this->right_half = this->tile_x > chip_width / 2;
-	this->top_half = this->tile_y > chip_height / 2;
+	if (this->fpga->device == "5k") {
+		this->top_half = this->tile_y > chip_height / 3;
+	} else {
+		this->top_half = this->tile_y > chip_height / 2;
+	}
 
 	this->bank_num = 0;
 	if (this->top_half) this->bank_num |= 1;
@@ -1086,8 +1100,10 @@ BramIndexConverter::BramIndexConverter(const FpgaConfig *fpga, int tile_x, int t
 	int y_offset = this->tile_y - 1;
 	if (!top_half) {
 		this->bank_num |= 1;
-	} else {
+	} else if (this->fpga->device == "5k") {
 		y_offset = this->tile_y - chip_height / 3;
+	} else {
+		y_offset = this->tile_y - chip_height / 2;
 	}
 	if (right_half) this->bank_num |= 2;