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| author | Tim 'mithro' Ansell <me@mith.ro> | 2018-06-12 19:15:17 -0700 |
|---|---|---|
| committer | Tim 'mithro' Ansell <me@mith.ro> | 2018-06-12 19:18:50 -0700 |
| commit | 82f2f3d278fe64a8053cb633e98287b21bb4b684 (patch) | |
| tree | 4ae5735580b8d61ccff8fd2540bcedca9cec3fe7 | |
| parent | d8d30fa63000fab66e770db996c4bb90dcb90420 (diff) | |
| download | icestorm-82f2f3d278fe64a8053cb633e98287b21bb4b684.tar.gz icestorm-82f2f3d278fe64a8053cb633e98287b21bb4b684.tar.bz2 icestorm-82f2f3d278fe64a8053cb633e98287b21bb4b684.zip | |
HLC: Use '~>' instead of '<->' for routing switches.
As mentioned in ca6b2d9ebd521ecec58b9b5627c9380355adeab1, the 'routing'
switches are not actually bidirectional. This makes the '<->' specifier
very misleading.
Instead use '~>' to differentiate it from the 'buffer' switches.
| -rwxr-xr-x | icebox/icebox_asc2hlc.py | 2 | ||||
| -rwxr-xr-x | icebox/icebox_hlc2asc.py | 12 |
2 files changed, 7 insertions, 7 deletions
diff --git a/icebox/icebox_asc2hlc.py b/icebox/icebox_asc2hlc.py index 4f0f6fa..facca4b 100755 --- a/icebox/icebox_asc2hlc.py +++ b/icebox/icebox_asc2hlc.py @@ -797,7 +797,7 @@ class Tile: self.ic.max_y - 1, entry[3]) if dst == 'fabout': dst = lookup_fabout(*self.xy) - self.buffer_and_routing.add((src, '<->', dst)) + self.buffer_and_routing.add((src, '~>', dst)) continue if entry[1] == 'buffer': if match: diff --git a/icebox/icebox_hlc2asc.py b/icebox/icebox_hlc2asc.py index 3b9ee38..00ed050 100755 --- a/icebox/icebox_hlc2asc.py +++ b/icebox/icebox_hlc2asc.py @@ -775,7 +775,7 @@ clearing:{:<30} - current set :{}""".format( if (src, dst) not in self.buffers: self.buffers.append((src, dst)) self.apply_directive('buffer', src, dst) - elif len(fields) == 3 and fields[1] == '<->': + elif len(fields) == 3 and fields[1] == '~>': src = untranslate_netname(self.x, self.y, self.ic.max_x - 1, self.ic.max_y - 1, fields[0]) @@ -786,7 +786,7 @@ clearing:{:<30} - current set :{}""".format( if (src, dst) not in self.routings: self.routings.append((src, dst)) self.apply_directive('routing', src, dst) - elif len(fields) >= 5 and (fields[1] == '->' or fields[1] == '<->'): + elif len(fields) >= 5 and (fields[1] == '->' or fields[1] == '~>'): self.read(fields[:3]) self.read(fields[2:]) else: @@ -840,11 +840,11 @@ class LogicCell: self.seq_bits[2] = '1' elif fields == ['async_setreset']: self.seq_bits[3] = '1' - elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '<->'): + elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '~>'): self.read(fields[:3]) self.read(fields[2:]) return - elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '<->'): + elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '~>'): prefix = 'lutff_%d/' % self.index # Strip prefix if it is given @@ -1001,10 +1001,10 @@ class IOBlock: == ("padin_glb_netwk", fields[2][10:])] assert len(bit) == 1 self.tile.ic.extra_bits.add(bit[0]) - elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '<->'): + elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '~>'): self.read(fields[:3]) self.read(fields[2:]) - elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '<->'): + elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '~>'): prefix = 'io_%d/' % self.index # Strip prefix if it is given |