blob: ca7f103b2427d611eab9643814f2405a9467bca3 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
|
library ieee;
use ieee.std_logic_1164.all;
entity var06 is
port (mask : std_logic_vector (1 downto 0);
val : std_logic_vector (15 downto 0);
res : out std_logic_vector (15 downto 0));
end var06;
architecture behav of var06 is
begin
process (all)
variable t : std_logic_vector (15 downto 0);
begin
t := (others => '0');
if mask (0) = '1' then
t (7 downto 0) := val (7 downto 0);
end if;
if mask (1) = '1' then
t (15 downto 8) := val (15 downto 8);
end if;
res <= t;
end process;
end behav;
|
