blob: b8c085cd95dddd47a1f4c4831e4f73d7887d68d3 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
|
library ieee;
use ieee.std_logic_1164.all;
entity uassoc02_sub is
port (i : std_logic_vector;
o : out std_logic_vector);
end uassoc02_sub;
architecture behav of uassoc02_sub is
begin
o <= not i;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity uassoc02 is
port (i1 : std_logic_vector(3 downto 0);
i2 : std_logic_vector(7 downto 0);
o : out std_logic_vector(3 downto 0));
end uassoc02;
architecture rtl of uassoc02 is
component uassoc02_sub is
port (i : std_logic_vector;
o : out std_logic_vector);
end component;
signal o1: std_logic_vector(3 downto 0);
signal o2: std_logic_vector(7 downto 0);
begin
dut1: uassoc02_sub
port map (i => i1, o => o1);
dut2: uassoc02_sub
port map (i => i2, o => o2);
o <= o1 xor o2 (3 downto 0);
end rtl;
|
