testsuite/synth/synth50/slv_negation.vhdl


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library ieee;
  use ieee.std_logic_1164.all;

entity slv_negation is
  port (
    a : in std_logic_vector(7 downto 0);
    b : out std_logic_vector(7 downto 0)
  );
end slv_negation;

architecture rtl of slv_negation is
begin
  b <= not a(7 downto 0);
end rtl;