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library ieee;
use ieee.std_logic_1164.all;
entity submodule is
port (
clk : in std_logic;
a : in std_logic_vector(7 downto 0);
b : out std_logic_vector(7 downto 0)
);
end submodule;
architecture rtl of submodule is
begin
process(clk)
begin
if rising_edge(clk) then
b <= a;
end if;
end process;
end rtl;
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