testsuite/synth/synth26/int_test.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

library ieee;
use ieee.std_logic_1164.all;

entity int_test is
  port (clk : in std_logic;
        a, b : in integer range 0 to 1;
        c : out std_logic);
end int_test;

architecture rtl of int_test is
begin
  process (clk)
  begin
    if rising_edge (clk) then
      if a < b then
        c <= '0';
      end if;
    end if;
  end process;
end rtl;