blob: aec306ea211194bd3102a14b6d82bb20a21f5448 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
|
library ieee;
use ieee.std_logic_1164.all;
entity top is
port(
clk : in std_logic;
di : in std_logic;
do : out std_logic
);
end top;
architecture behavioral of top is
signal data : std_logic;
begin
mylabel: process (clk)
variable tmp : std_logic;
begin
if rising_edge(clk) then
tmp := di; -- Post-synthesis name : mylabel.tmp
end if;
data <= not(tmp);
end process;
do <= not(data);
end behavioral;
|
