blob: 6610b0f232b25496d45c13aed6f38d4f993fd0f7 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
|
entity tb_ram3 is
end tb_ram3;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ram3 is
signal clkA : std_logic;
signal enA : std_logic;
signal weA : std_logic;
signal addrA : std_logic_vector(7 downto 0);
signal rdatA : std_logic_vector(7 downto 0);
signal wdatA : std_logic_vector(7 downto 0);
signal clkB : std_logic;
signal enB : std_logic;
signal weB : std_logic;
signal addrB : std_logic_vector(5 downto 0);
signal rdatB : std_logic_vector(31 downto 0);
signal wdatB : std_logic_vector(31 downto 0);
begin
dut: entity work.ram3
port map (clkA => clkA, clkB => clkB,
enA => enA, enB => enB,
weA => weA, weB => weB,
addrA => addrA, addrB => addrB,
diA => wdatA, diB => wdatB,
doA => rdatA, doB => rdatB);
process
procedure pulseB is
begin
clkB <= '0';
wait for 1 ns;
clkB <= '1';
wait for 1 ns;
end pulseB;
begin
clkA <= '0';
enA <= '0';
enB <= '1';
weB <= '1';
addrB <= b"00_0000";
wdatB <= x"11_22_33_f0";
pulseB;
pulseB;
assert rdatB = x"11_22_33_f0" severity failure;
addrB <= b"00_0001";
wdatB <= x"11_22_33_f1";
pulseB;
pulseB;
assert rdatB = x"11_22_33_f1" severity failure;
-- Read.
weB <= '0';
addrB <= b"00_0000";
wdatB <= x"ff_22_33_f1";
pulseB;
pulseB;
assert rdatB = x"11_22_33_f0" severity failure;
addrB <= b"00_0001";
wdatB <= x"ff_22_33_f1";
pulseB;
pulseB;
assert rdatB = x"11_22_33_f1" severity failure;
-- Disable.
enB <= '0';
weB <= '1';
addrB <= b"00_0000";
wdatB <= x"11_22_33_f0";
pulseB;
assert rdatB = x"11_22_33_f1" severity failure;
wait;
end process;
end behav;
|
