blob: 0d62d499f27e96c217de53d6c6586d988cc743cb (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
|
entity tb_ram1 is
end tb_ram1;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ram1 is
signal clk : std_logic;
signal en : std_logic;
signal we : std_logic;
signal addr : std_logic_vector(5 downto 0);
signal rdat : std_logic_vector(31 downto 0);
signal wdat : std_logic_vector(31 downto 0);
begin
dut: entity work.ram1
port map (clkB => clk, enB => en, weB => we, addrB => addr,
diB => wdat, doB => rdat);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
en <= '1';
we <= '1';
addr <= b"00_0000";
wdat <= x"11_22_33_f0";
pulse;
assert rdat = x"11_22_33_f0" severity failure;
addr <= b"00_0001";
wdat <= x"11_22_33_f1";
pulse;
assert rdat = x"11_22_33_f1" severity failure;
-- Read.
we <= '0';
addr <= b"00_0000";
wdat <= x"ff_22_33_f1";
pulse;
assert rdat = x"11_22_33_f0" severity failure;
addr <= b"00_0001";
wdat <= x"ff_22_33_f1";
pulse;
assert rdat = x"11_22_33_f1" severity failure;
-- Disable.
en <= '0';
we <= '1';
addr <= b"00_0000";
wdat <= x"11_22_33_f0";
pulse;
assert rdat = x"11_22_33_f1" severity failure;
wait;
end process;
end behav;
|
