blob: 9a21cbb8c12b5ad3a81d20693492eac90b359dec (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
|
library ieee;
use ieee.std_logic_1164.all;
entity subprg01 is
port (a : std_logic_vector (3 downto 0);
na : out std_logic_vector (3 downto 0));
end subprg01;
architecture behav of subprg01 is
procedure neg (v : inout std_logic_vector(3 downto 0)) is
begin
v := not v;
end neg;
begin
process(A)
variable t : std_logic_vector(3 downto 0);
begin
t := a;
neg (t);
na <= t;
end process;
end behav;
|
