blob: a8f3b7e60084a62832765f5d2846602a15b774ff (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity sns01 is
port (a : natural range 0 to 15;
b : out unsigned (3 downto 0);
clk : std_logic);
end sns01;
architecture behav of sns01 is
begin
process (clk)
begin
if rising_edge(clk) then
b <= conv_unsigned (a, 4);
end if;
end process;
end behav;
|
