testsuite/synth/range01/tb_revrng01.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

entity tb_revrng01 is
end tb_revrng01;

library ieee;
use ieee.std_logic_1164.all;

architecture behav of tb_revrng01 is
  signal a, z : std_logic_vector (7 downto 0);
begin
  dut: entity work.revrng01
    port map (a, z);

  process
  begin
    a <= x"a1";
    wait for 1 ns;
    assert z = x"85" severity failure;
    wait;
  end process;
end behav;