blob: a563dadd12b2e56aa7411ea735d1e2ff7cad01bc (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity assert1 is
port (clk, rst: std_logic;
cnt : out unsigned(3 downto 0));
end assert1;
architecture behav of assert1 is
signal val : unsigned (3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
val <= (others => '0');
else
val <= val + 1;
end if;
end if;
end process;
cnt <= val;
end behav;
vunit verif1 (assert1)
{
default clock is rising_edge(clk);
assert always cnt /= 5 abort rst;
}
|