testsuite/synth/oper02/tb_min01.vhdl


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entity tb_min01 is
end tb_min01;

library ieee;
use ieee.std_logic_1164.all;

architecture behav of tb_min01 is
  signal l, r  : natural;
  signal res : natural;
begin
  min01_1: entity work.min01
    port map (
      a  => l,
      b  => r,
      o => res);

  process
  begin
    l <= 12;
    r <= 15;
    wait for 1 ns;
    assert res = 12 severity failure;

    wait;
  end process;
end behav;