testsuite/synth/oper01/tb_uns01.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

entity tb_uns01 is
end tb_uns01;

library ieee;
use ieee.std_logic_1164.all;

architecture behav of tb_uns01 is
  signal r : boolean;
begin
  cmp01_1: entity work.uns01
    port map (r);

  process
  begin
    wait for 1 ns;
    assert r severity failure;

    wait;
  end process;
end behav;