blob: 9165d14a0d0d0f6f79cb163fd0913d92be8be21e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
|
entity tb_cmp02 is
end tb_cmp02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_cmp02 is
signal l : std_logic_vector(3 downto 0);
signal r : natural;
signal eq : std_logic;
signal ne : std_logic;
signal lt : std_logic;
signal le : std_logic;
signal ge : std_logic;
signal gt : std_logic;
begin
cmp02_1: entity work.cmp02
port map (
l => l,
r => r,
eq => eq,
ne => ne,
lt => lt,
le => le,
ge => ge,
gt => gt);
process
begin
l <= x"5";
r <= 7;
wait for 1 ns;
assert eq = '0' severity failure;
assert ne = '1' severity failure;
assert lt = '1' severity failure;
assert le = '1' severity failure;
assert ge = '0' severity failure;
assert gt = '0' severity failure;
l <= x"a";
r <= 7;
wait for 1 ns;
assert eq = '0' severity failure;
assert ne = '1' severity failure;
assert lt = '0' severity failure;
assert le = '0' severity failure;
assert ge = '1' severity failure;
assert gt = '1' severity failure;
l <= x"9";
r <= 9;
wait for 1 ns;
assert eq = '1' severity failure;
assert ne = '0' severity failure;
assert lt = '0' severity failure;
assert le = '1' severity failure;
assert ge = '1' severity failure;
assert gt = '0' severity failure;
wait;
end process;
end behav;
|
