blob: da2150ebe71364c46282ddb7aec80a6c34526c39 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
|
entity tb_test_addsub is
end tb_test_addsub;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_test_addsub is
signal s_slv : std_logic_vector(3 downto 0);
signal s_nat : natural range 0 to 15;
signal s_add_slvslv : std_logic_vector(3 downto 0);
signal s_add_slvnat : std_logic_vector(3 downto 0);
signal s_add_natslv : std_logic_vector(3 downto 0);
signal s_sub_slvslv : std_logic_vector(3 downto 0);
signal s_sub_slvnat : std_logic_vector(3 downto 0);
signal s_sub_natslv : std_logic_vector(3 downto 0);
begin
dut: entity work.test_addsub
port map (s_slv,
s_nat,
s_add_slvslv,
s_add_slvnat,
s_add_natslv,
s_sub_slvslv,
s_sub_slvnat,
s_sub_natslv);
process
begin
s_slv <= x"6";
s_nat <= 6;
wait for 1 ns;
assert s_add_slvslv = x"C" severity failure;
assert s_add_slvnat = x"C" severity failure;
assert s_add_natslv = x"C" severity failure;
assert s_sub_slvslv = x"0" severity failure;
assert s_sub_slvnat = x"0" severity failure;
assert s_sub_natslv = x"0" severity failure;
s_slv <= x"6";
s_nat <= 10;
wait for 1 ns;
assert s_add_slvslv = x"C" severity failure;
assert s_add_slvnat = x"0" severity failure;
assert s_add_natslv = x"0" severity failure;
assert s_sub_slvslv = x"0" severity failure;
assert s_sub_slvnat = x"C" severity failure;
assert s_sub_natslv = x"4" severity failure;
wait;
end process;
end behav;
|
