blob: 55b56c680bf4b580a8f30faf49512c837feb08d5 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
entity tb_areset is
end tb_areset;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_areset is
signal clk : std_logic;
signal rst_n : std_logic;
signal din : std_logic;
signal dout : std_logic_vector(1 downto 0);
begin
dut: entity work.areset
port map (
clk_sys => clk,
reset_n => rst_n,
d => din,
q => dout);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= '0';
rst_n <= '0';
pulse;
assert dout (0) = '0' severity failure;
din <= '1';
pulse;
assert dout (0) = '0' severity failure;
rst_n <= '1';
pulse;
assert dout (0) = '1' severity failure;
assert dout (1) = '1' severity failure;
din <= '0';
pulse;
assert dout (0) = '1' severity failure;
assert dout (1) = '0' severity failure;
din <= '1';
rst_n <= '0';
pulse;
assert dout (0) = '0' severity failure;
assert dout (1) = '0' severity failure;
wait;
end process;
end behav;
|
