blob: 342713dc890b0a60d9cf4f3c2ed2ac6264e20652 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (o : out std_ulogic);
end;
architecture a of ent is
procedure proc (
signal pin : out std_ulogic;
constant drive_pin : boolean := false
) is
begin
if drive_pin then
pin <= '1';
end if;
end procedure;
begin
o <= '1';
proc(pin => o);
end;
|