blob: 21d8b7c643df09f2d7b7a0778b644a220e6d4b7f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
|
library ieee;
use ieee.std_logic_1164.all;
entity crash is
port (
clk : in std_logic
);
end entity crash;
architecture rtl of crash is
signal index : std_logic := '0';
begin
-- process (clk) is
-- begin
-- if rising_edge(clk) then
-- >> This prints an error, but doesn't crash ghdl
-- index <= index = index'LAST_VALUE;
-- end if;
-- end process;
-- psl default clock is rising_edge(clk);
-- psl crash_my_ghdl2 : cover
-- {not index'active or index'event};
end architecture rtl;
|
