testsuite/synth/issue2177/testsuite.sh


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#! /bin/sh

. ../../testenv.sh


synth --out=verilog vlm5030_pack.vhd clock_functions_pack.vhd vlm5030_subcircuits.vhd vlm5030_gl.vhd -e > syn_vlm5030.v

echo "Test successful"