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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mul is
port(
a : in unsigned( 7 downto 0);
b : in unsigned(15 downto 0);
r : out unsigned(23 downto 0)
);
end entity;
architecture rtl of mul is
begin
r <= resize(a*b, 24);
end architecture;
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