testsuite/synth/issue2124/a.vhdl


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library ieee;
use ieee.std_logic_1164.all;

entity a is
end entity;

architecture behaviour of a is

  component b
    port (
      c : in  std_logic;
      q : out std_logic
      );
  end component;
  
begin

  inst : b
    port map (
      c => '0',
      q => open
      );
  
end architecture;