testsuite/synth/issue2109/testsuite.sh


1
2
3
4
5
6
7
8
9
10
11

#! /bin/sh

. ../../testenv.sh

synth --out=verilog bug.vhdl -e > syn_bug.v

if grep val syn_bug.v; then
  exit 1
fi

echo "Test successful"