testsuite/synth/issue2081/ent.vhdl


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library ieee;
use ieee.std_logic_1164.all;

entity ent is
end entity;

architecture a of ent is
	signal foo : std_logic_vector(7 downto 0);
begin
	process(foo)
	begin
		if foo /= x"00" then
			assert false;
		end if;
	end process;
end architecture;