blob: a51e970f462e39e2632729c5c2559b171276b041 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
|
#! /bin/sh
. ../../testenv.sh
synth --out=verilog flip_flop.vhdl -e > syn_flip_flop.v
if grep "input wire" syn_flip_flop.v; then
exit 1
fi
synth --out=verilog testcase2.vhdl -e > syn_testcase2.v
if grep "assign edge" syn_testcase2.v; then
exit 1
fi
synth --out=verilog testcase3.vhdl -e > syn_testcase3.v
if grep "edge =" syn_testcase3.v; then
exit 1
fi
echo "Test successful"
|
