testsuite/synth/issue2035/cdc_fifo_rtl.vhdl


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ENTITY cdc_fifo IS
END ENTITY cdc_fifo;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ARCHITECTURE rtl OF cdc_fifo IS
  SIGNAL ver_clk : std_logic;
  ATTRIBUTE gclk : boolean;
  ATTRIBUTE gclk OF ver_clk : SIGNAL is true;
BEGIN
END ARCHITECTURE;