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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end ent;
architecture ent of ent is
type my_record is record
field_a : std_logic_vector; -- Parametrized on instantiation
field_b : std_logic_vector(31 downto 0); -- Width set by generic
end record;
signal bar : my_record(field_a(7 downto 0));
signal baz : my_record(field_a(7 downto 0));
begin
end ent;
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