blob: 619469500354a8b1039872c523ddb0527687e8f6 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shiftMux2 is
Port (
clk : in std_logic;
--inputA
inputA : in std_logic;
outputB : out std_logic
);
end shiftMux2;
architecture Rtl of shiftMux2 is
begin
process (clk) is
begin
if rising_edge(clk) then
outputB <= inputA;
end if;
end process;
end Rtl;
|
