testsuite/synth/issue1628/test.vhdl


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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;

entity test is
end entity test;

architecture synthesis of test is

   signal a : std_logic_vector(3 downto 0);

begin

   a <= to_stdlogicvector(10, 4);

end architecture synthesis;