blob: c0ef4f21a01d26561c40fe212cbf1e81a2e97522 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
|
library ieee;
use ieee.std_logic_1164.all;
entity repro1 is
port (clk : in std_logic);
end entity repro1;
architecture psl of repro1 is
begin
testG : if true generate
signal b : boolean := true;
begin
-- All is sensitive to rising edge of clk
default clock is rising_edge(clk);
-- This assertion generates an ghdl-yosys-plugin error
-- ERROR: Assert `n.id != 0' failed in src/ghdl.cc:204.
INITIAL_1_a : assert always b;
end generate testG;
end architecture psl;
|