testsuite/synth/issue1509/pass01.vhdl


1
2
3
4
5
6
7
8
9
10
11

entity pass01 is
    port (
        i: in integer range -4 to 4;
        o: out integer range -4 to 4
    );
end entity;

architecture arch of pass01 is
begin
    o <= i;
end architecture;